2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include "skeleton.dtsi"
51 compatible = "rockchip,rk3288";
53 interrupt-parent = <&gic>;
77 compatible = "arm,cortex-a12-pmu";
78 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
82 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 enable-method = "rockchip,rk3066-smp";
89 rockchip,pmu = <&pmu>;
93 compatible = "arm,cortex-a12";
95 resets = <&cru SRST_CORE0>;
111 #cooling-cells = <2>; /* min followed by max */
112 clock-latency = <40000>;
113 clocks = <&cru ARMCLK>;
117 compatible = "arm,cortex-a12";
119 resets = <&cru SRST_CORE1>;
123 compatible = "arm,cortex-a12";
125 resets = <&cru SRST_CORE2>;
129 compatible = "arm,cortex-a12";
131 resets = <&cru SRST_CORE3>;
136 compatible = "arm,amba-bus";
137 #address-cells = <1>;
141 dmac_peri: dma-controller@ff250000 {
142 compatible = "arm,pl330", "arm,primecell";
143 reg = <0xff250000 0x4000>;
144 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
147 arm,pl330-broken-no-flushp;
148 peripherals-req-type-burst;
149 clocks = <&cru ACLK_DMAC2>;
150 clock-names = "apb_pclk";
153 dmac_bus_ns: dma-controller@ff600000 {
154 compatible = "arm,pl330", "arm,primecell";
155 reg = <0xff600000 0x4000>;
156 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
159 arm,pl330-broken-no-flushp;
160 peripherals-req-type-burst;
161 clocks = <&cru ACLK_DMAC1>;
162 clock-names = "apb_pclk";
166 dmac_bus_s: dma-controller@ffb20000 {
167 compatible = "arm,pl330", "arm,primecell";
168 reg = <0xffb20000 0x4000>;
169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
172 arm,pl330-broken-no-flushp;
173 peripherals-req-type-burst;
174 clocks = <&cru ACLK_DMAC1>;
175 clock-names = "apb_pclk";
180 #address-cells = <1>;
185 * The rk3288 cannot use the memory area above 0xfe000000
186 * for dma operations for some reason. While there is
187 * probably a better solution available somewhere, we
188 * haven't found it yet and while devices with 2GB of ram
189 * are not affected, this issue prevents 4GB from booting.
190 * So to make these devices at least bootable, block
191 * this area for the time being until the real solution
194 dma-unusable@fe000000 {
195 reg = <0xfe000000 0x1000000>;
200 compatible = "fixed-clock";
201 clock-frequency = <24000000>;
202 clock-output-names = "xin24m";
207 compatible = "arm,armv7-timer";
208 arm,cpu-registers-not-fw-configured;
209 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
210 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
211 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
213 clock-frequency = <24000000>;
216 timer: timer@ff810000 {
217 compatible = "rockchip,rk3288-timer";
218 reg = <0xff810000 0x20>;
219 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&xin24m>, <&cru PCLK_TIMER>;
221 clock-names = "timer", "pclk";
225 compatible = "rockchip,display-subsystem";
226 ports = <&vopl_out>, <&vopb_out>;
229 sdmmc: dwmmc@ff0c0000 {
230 compatible = "rockchip,rk3288-dw-mshc";
231 clock-freq-min-max = <400000 150000000>;
232 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
233 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
234 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
235 fifo-depth = <0x100>;
236 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
237 reg = <0xff0c0000 0x4000>;
241 sdio0: dwmmc@ff0d0000 {
242 compatible = "rockchip,rk3288-dw-mshc";
243 clock-freq-min-max = <400000 150000000>;
244 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
245 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
246 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
247 fifo-depth = <0x100>;
248 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
249 reg = <0xff0d0000 0x4000>;
253 sdio1: dwmmc@ff0e0000 {
254 compatible = "rockchip,rk3288-dw-mshc";
255 clock-freq-min-max = <400000 150000000>;
256 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
257 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
258 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
259 fifo-depth = <0x100>;
260 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
261 reg = <0xff0e0000 0x4000>;
265 emmc: dwmmc@ff0f0000 {
266 compatible = "rockchip,rk3288-dw-mshc";
267 clock-freq-min-max = <400000 150000000>;
268 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
269 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
270 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
271 fifo-depth = <0x100>;
272 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
273 reg = <0xff0f0000 0x4000>;
277 saradc: saradc@ff100000 {
278 compatible = "rockchip,saradc";
279 reg = <0xff100000 0x100>;
280 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
281 #io-channel-cells = <1>;
282 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
283 clock-names = "saradc", "apb_pclk";
288 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
289 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
290 clock-names = "spiclk", "apb_pclk";
291 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
292 dma-names = "tx", "rx";
293 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
296 reg = <0xff110000 0x1000>;
297 #address-cells = <1>;
303 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
304 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
305 clock-names = "spiclk", "apb_pclk";
306 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
307 dma-names = "tx", "rx";
308 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
311 reg = <0xff120000 0x1000>;
312 #address-cells = <1>;
318 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
319 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
320 clock-names = "spiclk", "apb_pclk";
321 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
322 dma-names = "tx", "rx";
323 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
326 reg = <0xff130000 0x1000>;
327 #address-cells = <1>;
333 compatible = "rockchip,rk3288-i2c";
334 reg = <0xff140000 0x1000>;
335 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
336 #address-cells = <1>;
339 clocks = <&cru PCLK_I2C1>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&i2c1_xfer>;
346 compatible = "rockchip,rk3288-i2c";
347 reg = <0xff150000 0x1000>;
348 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
349 #address-cells = <1>;
352 clocks = <&cru PCLK_I2C3>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&i2c3_xfer>;
359 compatible = "rockchip,rk3288-i2c";
360 reg = <0xff160000 0x1000>;
361 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
362 #address-cells = <1>;
365 clocks = <&cru PCLK_I2C4>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&i2c4_xfer>;
372 compatible = "rockchip,rk3288-i2c";
373 reg = <0xff170000 0x1000>;
374 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
375 #address-cells = <1>;
378 clocks = <&cru PCLK_I2C5>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&i2c5_xfer>;
384 uart0: serial@ff180000 {
385 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
386 reg = <0xff180000 0x100>;
387 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
391 clock-names = "baudclk", "apb_pclk";
392 pinctrl-names = "default";
393 pinctrl-0 = <&uart0_xfer>;
397 uart1: serial@ff190000 {
398 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
399 reg = <0xff190000 0x100>;
400 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
404 clock-names = "baudclk", "apb_pclk";
405 pinctrl-names = "default";
406 pinctrl-0 = <&uart1_xfer>;
410 uart2: serial@ff690000 {
411 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
412 reg = <0xff690000 0x100>;
413 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
417 clock-names = "baudclk", "apb_pclk";
418 pinctrl-names = "default";
419 pinctrl-0 = <&uart2_xfer>;
423 uart3: serial@ff1b0000 {
424 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
425 reg = <0xff1b0000 0x100>;
426 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
430 clock-names = "baudclk", "apb_pclk";
431 pinctrl-names = "default";
432 pinctrl-0 = <&uart3_xfer>;
436 uart4: serial@ff1c0000 {
437 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
438 reg = <0xff1c0000 0x100>;
439 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
443 clock-names = "baudclk", "apb_pclk";
444 pinctrl-names = "default";
445 pinctrl-0 = <&uart4_xfer>;
450 #include "rk3288-thermal.dtsi"
453 tsadc: tsadc@ff280000 {
454 compatible = "rockchip,rk3288-tsadc";
455 reg = <0xff280000 0x100>;
456 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
458 clock-names = "tsadc", "apb_pclk";
459 resets = <&cru SRST_TSADC>;
460 reset-names = "tsadc-apb";
461 pinctrl-names = "init", "default", "sleep";
462 pinctrl-0 = <&otp_gpio>;
463 pinctrl-1 = <&otp_out>;
464 pinctrl-2 = <&otp_gpio>;
465 #thermal-sensor-cells = <1>;
466 rockchip,hw-tshut-temp = <95000>;
470 gmac: ethernet@ff290000 {
471 compatible = "rockchip,rk3288-gmac";
472 reg = <0xff290000 0x10000>;
473 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
474 interrupt-names = "macirq";
475 rockchip,grf = <&grf>;
476 clocks = <&cru SCLK_MAC>,
477 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
478 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
479 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
480 clock-names = "stmmaceth",
481 "mac_clk_rx", "mac_clk_tx",
482 "clk_mac_ref", "clk_mac_refout",
483 "aclk_mac", "pclk_mac";
484 resets = <&cru SRST_MAC>;
485 reset-names = "stmmaceth";
489 usb_host0_ehci: usb@ff500000 {
490 compatible = "generic-ehci";
491 reg = <0xff500000 0x100>;
492 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&cru HCLK_USBHOST0>;
494 clock-names = "usbhost";
500 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
502 usb_host1: usb@ff540000 {
503 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
505 reg = <0xff540000 0x40000>;
506 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&cru HCLK_USBHOST1>;
511 phy-names = "usb2-phy";
515 usb_otg: usb@ff580000 {
516 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
518 reg = <0xff580000 0x40000>;
519 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&cru HCLK_OTG0>;
523 g-np-tx-fifo-size = <16>;
524 g-rx-fifo-size = <275>;
525 g-tx-fifo-size = <256 128 128 64 64 32>;
528 phy-names = "usb2-phy";
532 usb_hsic: usb@ff5c0000 {
533 compatible = "generic-ehci";
534 reg = <0xff5c0000 0x100>;
535 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&cru HCLK_HSIC>;
537 clock-names = "usbhost";
542 compatible = "rockchip,rk3288-i2c";
543 reg = <0xff650000 0x1000>;
544 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
545 #address-cells = <1>;
548 clocks = <&cru PCLK_I2C0>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&i2c0_xfer>;
555 compatible = "rockchip,rk3288-i2c";
556 reg = <0xff660000 0x1000>;
557 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
558 #address-cells = <1>;
561 clocks = <&cru PCLK_I2C2>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&i2c2_xfer>;
568 compatible = "rockchip,rk3288-pwm";
569 reg = <0xff680000 0x10>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&pwm0_pin>;
573 clocks = <&cru PCLK_PWM>;
579 compatible = "rockchip,rk3288-pwm";
580 reg = <0xff680010 0x10>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&pwm1_pin>;
584 clocks = <&cru PCLK_PWM>;
590 compatible = "rockchip,rk3288-pwm";
591 reg = <0xff680020 0x10>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&pwm2_pin>;
595 clocks = <&cru PCLK_PWM>;
601 compatible = "rockchip,rk3288-pwm";
602 reg = <0xff680030 0x10>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&pwm3_pin>;
606 clocks = <&cru PCLK_PWM>;
611 bus_intmem@ff700000 {
612 compatible = "mmio-sram";
613 reg = <0xff700000 0x18000>;
614 #address-cells = <1>;
616 ranges = <0 0xff700000 0x18000>;
618 compatible = "rockchip,rk3066-smp-sram";
624 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
625 reg = <0xff720000 0x1000>;
628 pmu: power-management@ff730000 {
629 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
630 reg = <0xff730000 0x100>;
632 power: power-controller {
633 compatible = "rockchip,rk3288-power-controller";
634 #power-domain-cells = <1>;
635 #address-cells = <1>;
639 * Note: Although SCLK_* are the working clocks
640 * of device without including on the NOC, needed for
643 * The clocks on the which NOC:
644 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
645 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
646 * ACLK_RGA is on ACLK_RGA_NIU.
647 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
649 * Which clock are device clocks:
651 * *_IEP IEP:Image Enhancement Processor
652 * *_ISP ISP:Image Signal Processing
653 * *_VIP VIP:Video Input Processor
654 * *_VOP* VOP:Visual Output Processor
662 reg = <RK3288_PD_VIO>;
663 clocks = <&cru ACLK_IEP>,
677 <&cru PCLK_EDP_CTRL>,
678 <&cru PCLK_HDMI_CTRL>,
679 <&cru PCLK_LVDS_PHY>,
680 <&cru PCLK_MIPI_CSI>,
681 <&cru PCLK_MIPI_DSI0>,
682 <&cru PCLK_MIPI_DSI1>,
691 * Note: The following 3 are HEVC(H.265) clocks,
692 * and on the ACLK_HEVC_NIU (NOC).
695 reg = <RK3288_PD_HEVC>;
696 clocks = <&cru ACLK_HEVC>,
697 <&cru SCLK_HEVC_CABAC>,
698 <&cru SCLK_HEVC_CORE>;
702 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
703 * (video endecoder & decoder) clocks that on the
704 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
707 reg = <RK3288_PD_VIDEO>;
708 clocks = <&cru ACLK_VCODEC>,
713 * Note: ACLK_GPU is the GPU clock,
714 * and on the ACLK_GPU_NIU (NOC).
717 reg = <RK3288_PD_GPU>;
718 clocks = <&cru ACLK_GPU>;
723 sgrf: syscon@ff740000 {
724 compatible = "rockchip,rk3288-sgrf", "syscon";
725 reg = <0xff740000 0x1000>;
728 cru: clock-controller@ff760000 {
729 compatible = "rockchip,rk3288-cru";
730 reg = <0xff760000 0x1000>;
731 rockchip,grf = <&grf>;
734 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
735 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
736 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
737 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
739 assigned-clock-rates = <594000000>, <400000000>,
740 <500000000>, <300000000>,
741 <150000000>, <75000000>,
742 <300000000>, <150000000>,
746 grf: syscon@ff770000 {
747 compatible = "rockchip,rk3288-grf", "syscon";
748 reg = <0xff770000 0x1000>;
751 wdt: watchdog@ff800000 {
752 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
753 reg = <0xff800000 0x100>;
754 clocks = <&cru PCLK_WDT>;
755 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
759 spdif: sound@ff88b0000 {
760 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
761 reg = <0xff8b0000 0x10000>;
762 #sound-dai-cells = <0>;
763 clock-names = "hclk", "mclk";
764 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
765 dmas = <&dmac_bus_s 3>;
767 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
768 pinctrl-names = "default";
769 pinctrl-0 = <&spdif_tx>;
770 rockchip,grf = <&grf>;
775 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
776 reg = <0xff890000 0x10000>;
777 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
778 #address-cells = <1>;
780 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
781 dma-names = "tx", "rx";
782 clock-names = "i2s_hclk", "i2s_clk";
783 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&i2s0_bus>;
790 compatible = "rockchip,rk3288-vop";
791 reg = <0xff930000 0x19c>;
792 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
794 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
795 power-domains = <&power RK3288_PD_VIO>;
796 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
797 reset-names = "axi", "ahb", "dclk";
798 iommus = <&vopb_mmu>;
802 #address-cells = <1>;
805 vopb_out_hdmi: endpoint@0 {
807 remote-endpoint = <&hdmi_in_vopb>;
809 vopb_out_mipi: endpoint@2 {
811 remote-endpoint = <&mipi_in_vopb>;
816 vopb_mmu: iommu@ff930300 {
817 compatible = "rockchip,iommu";
818 reg = <0xff930300 0x100>;
819 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
820 interrupt-names = "vopb_mmu";
821 power-domains = <&power RK3288_PD_VIO>;
827 compatible = "rockchip,rk3288-vop";
828 reg = <0xff940000 0x19c>;
829 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
831 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
832 power-domains = <&power RK3288_PD_VIO>;
833 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
834 reset-names = "axi", "ahb", "dclk";
835 iommus = <&vopl_mmu>;
839 #address-cells = <1>;
842 vopl_out_hdmi: endpoint@0 {
844 remote-endpoint = <&hdmi_in_vopl>;
846 vopl_out_mipi: endpoint@2 {
848 remote-endpoint = <&mipi_in_vopl>;
853 vopl_mmu: iommu@ff940300 {
854 compatible = "rockchip,iommu";
855 reg = <0xff940300 0x100>;
856 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
857 interrupt-names = "vopl_mmu";
858 power-domains = <&power RK3288_PD_VIO>;
863 mipi_dsi: mipi@ff960000 {
864 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
865 reg = <0xff960000 0x4000>;
866 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
868 clock-names = "ref", "pclk";
869 rockchip,grf = <&grf>;
870 #address-cells = <1>;
875 #address-cells = <1>;
880 #address-cells = <1>;
882 mipi_in_vopb: endpoint@0 {
884 remote-endpoint = <&vopb_out_mipi>;
886 mipi_in_vopl: endpoint@1 {
888 remote-endpoint = <&vopl_out_mipi>;
894 hdmi: hdmi@ff980000 {
895 compatible = "rockchip,rk3288-dw-hdmi";
896 reg = <0xff980000 0x20000>;
898 rockchip,grf = <&grf>;
899 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
901 clock-names = "iahb", "isfr";
902 power-domains = <&power RK3288_PD_VIO>;
907 #address-cells = <1>;
909 hdmi_in_vopb: endpoint@0 {
911 remote-endpoint = <&vopb_out_hdmi>;
913 hdmi_in_vopl: endpoint@1 {
915 remote-endpoint = <&vopl_out_hdmi>;
921 gic: interrupt-controller@ffc01000 {
922 compatible = "arm,gic-400";
923 interrupt-controller;
924 #interrupt-cells = <3>;
925 #address-cells = <0>;
927 reg = <0xffc01000 0x1000>,
931 interrupts = <GIC_PPI 9 0xf04>;
935 compatible = "rockchip,rk3288-usb-phy";
936 rockchip,grf = <&grf>;
937 #address-cells = <1>;
944 clocks = <&cru SCLK_OTGPHY0>;
945 clock-names = "phyclk";
951 clocks = <&cru SCLK_OTGPHY1>;
952 clock-names = "phyclk";
958 clocks = <&cru SCLK_OTGPHY2>;
959 clock-names = "phyclk";
964 compatible = "rockchip,rk3288-pinctrl";
965 rockchip,grf = <&grf>;
966 rockchip,pmu = <&pmu>;
967 #address-cells = <1>;
971 gpio0: gpio0@ff750000 {
972 compatible = "rockchip,gpio-bank";
973 reg = <0xff750000 0x100>;
974 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&cru PCLK_GPIO0>;
980 interrupt-controller;
981 #interrupt-cells = <2>;
984 gpio1: gpio1@ff780000 {
985 compatible = "rockchip,gpio-bank";
986 reg = <0xff780000 0x100>;
987 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&cru PCLK_GPIO1>;
993 interrupt-controller;
994 #interrupt-cells = <2>;
997 gpio2: gpio2@ff790000 {
998 compatible = "rockchip,gpio-bank";
999 reg = <0xff790000 0x100>;
1000 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&cru PCLK_GPIO2>;
1006 interrupt-controller;
1007 #interrupt-cells = <2>;
1010 gpio3: gpio3@ff7a0000 {
1011 compatible = "rockchip,gpio-bank";
1012 reg = <0xff7a0000 0x100>;
1013 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&cru PCLK_GPIO3>;
1019 interrupt-controller;
1020 #interrupt-cells = <2>;
1023 gpio4: gpio4@ff7b0000 {
1024 compatible = "rockchip,gpio-bank";
1025 reg = <0xff7b0000 0x100>;
1026 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&cru PCLK_GPIO4>;
1032 interrupt-controller;
1033 #interrupt-cells = <2>;
1036 gpio5: gpio5@ff7c0000 {
1037 compatible = "rockchip,gpio-bank";
1038 reg = <0xff7c0000 0x100>;
1039 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1040 clocks = <&cru PCLK_GPIO5>;
1045 interrupt-controller;
1046 #interrupt-cells = <2>;
1049 gpio6: gpio6@ff7d0000 {
1050 compatible = "rockchip,gpio-bank";
1051 reg = <0xff7d0000 0x100>;
1052 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&cru PCLK_GPIO6>;
1058 interrupt-controller;
1059 #interrupt-cells = <2>;
1062 gpio7: gpio7@ff7e0000 {
1063 compatible = "rockchip,gpio-bank";
1064 reg = <0xff7e0000 0x100>;
1065 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&cru PCLK_GPIO7>;
1071 interrupt-controller;
1072 #interrupt-cells = <2>;
1075 gpio8: gpio8@ff7f0000 {
1076 compatible = "rockchip,gpio-bank";
1077 reg = <0xff7f0000 0x100>;
1078 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1079 clocks = <&cru PCLK_GPIO8>;
1084 interrupt-controller;
1085 #interrupt-cells = <2>;
1089 hdmi_ddc: hdmi-ddc {
1090 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1091 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1095 pcfg_pull_up: pcfg-pull-up {
1099 pcfg_pull_down: pcfg-pull-down {
1103 pcfg_pull_none: pcfg-pull-none {
1107 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1109 drive-strength = <12>;
1113 global_pwroff: global-pwroff {
1114 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1117 ddrio_pwroff: ddrio-pwroff {
1118 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1121 ddr0_retention: ddr0-retention {
1122 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1125 ddr1_retention: ddr1-retention {
1126 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1131 i2c0_xfer: i2c0-xfer {
1132 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1133 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1138 i2c1_xfer: i2c1-xfer {
1139 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1140 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1145 i2c2_xfer: i2c2-xfer {
1146 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1147 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1152 i2c3_xfer: i2c3-xfer {
1153 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1154 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1159 i2c4_xfer: i2c4-xfer {
1160 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1161 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1166 i2c5_xfer: i2c5-xfer {
1167 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1168 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1173 i2s0_bus: i2s0-bus {
1174 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1175 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1176 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1177 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1178 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1179 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1184 sdmmc_clk: sdmmc-clk {
1185 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1188 sdmmc_cmd: sdmmc-cmd {
1189 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1192 sdmmc_cd: sdmcc-cd {
1193 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1196 sdmmc_bus1: sdmmc-bus1 {
1197 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1200 sdmmc_bus4: sdmmc-bus4 {
1201 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1202 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1203 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1204 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1209 sdio0_bus1: sdio0-bus1 {
1210 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1213 sdio0_bus4: sdio0-bus4 {
1214 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1215 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1216 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1217 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1220 sdio0_cmd: sdio0-cmd {
1221 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1224 sdio0_clk: sdio0-clk {
1225 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1228 sdio0_cd: sdio0-cd {
1229 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1232 sdio0_wp: sdio0-wp {
1233 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1236 sdio0_pwr: sdio0-pwr {
1237 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1240 sdio0_bkpwr: sdio0-bkpwr {
1241 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1244 sdio0_int: sdio0-int {
1245 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1250 sdio1_bus1: sdio1-bus1 {
1251 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1254 sdio1_bus4: sdio1-bus4 {
1255 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1256 <3 25 4 &pcfg_pull_up>,
1257 <3 26 4 &pcfg_pull_up>,
1258 <3 27 4 &pcfg_pull_up>;
1261 sdio1_cd: sdio1-cd {
1262 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1265 sdio1_wp: sdio1-wp {
1266 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1269 sdio1_bkpwr: sdio1-bkpwr {
1270 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1273 sdio1_int: sdio1-int {
1274 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1277 sdio1_cmd: sdio1-cmd {
1278 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1281 sdio1_clk: sdio1-clk {
1282 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1285 sdio1_pwr: sdio1-pwr {
1286 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1291 emmc_clk: emmc-clk {
1292 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1295 emmc_cmd: emmc-cmd {
1296 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1299 emmc_pwr: emmc-pwr {
1300 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1303 emmc_bus1: emmc-bus1 {
1304 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1307 emmc_bus4: emmc-bus4 {
1308 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1309 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1310 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1311 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1314 emmc_bus8: emmc-bus8 {
1315 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1316 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1317 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1318 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1319 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1320 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1321 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1322 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1327 spi0_clk: spi0-clk {
1328 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1330 spi0_cs0: spi0-cs0 {
1331 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1334 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1337 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1339 spi0_cs1: spi0-cs1 {
1340 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1344 spi1_clk: spi1-clk {
1345 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1347 spi1_cs0: spi1-cs0 {
1348 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1351 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1354 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1359 spi2_cs1: spi2-cs1 {
1360 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1362 spi2_clk: spi2-clk {
1363 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1365 spi2_cs0: spi2-cs0 {
1366 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1369 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1372 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1377 uart0_xfer: uart0-xfer {
1378 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1379 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1382 uart0_cts: uart0-cts {
1383 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1386 uart0_rts: uart0-rts {
1387 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1392 uart1_xfer: uart1-xfer {
1393 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1394 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1397 uart1_cts: uart1-cts {
1398 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1401 uart1_rts: uart1-rts {
1402 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1407 uart2_xfer: uart2-xfer {
1408 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1409 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1411 /* no rts / cts for uart2 */
1415 uart3_xfer: uart3-xfer {
1416 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1417 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1420 uart3_cts: uart3-cts {
1421 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1424 uart3_rts: uart3-rts {
1425 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1430 uart4_xfer: uart4-xfer {
1431 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1432 <5 13 3 &pcfg_pull_none>;
1435 uart4_cts: uart4-cts {
1436 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1439 uart4_rts: uart4-rts {
1440 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1445 otp_gpio: otp-gpio {
1446 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1450 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1455 pwm0_pin: pwm0-pin {
1456 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1461 pwm1_pin: pwm1-pin {
1462 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1467 pwm2_pin: pwm2-pin {
1468 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1473 pwm3_pin: pwm3-pin {
1474 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1479 rgmii_pins: rgmii-pins {
1480 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1481 <3 31 3 &pcfg_pull_none>,
1482 <3 26 3 &pcfg_pull_none>,
1483 <3 27 3 &pcfg_pull_none>,
1484 <3 28 3 &pcfg_pull_none_12ma>,
1485 <3 29 3 &pcfg_pull_none_12ma>,
1486 <3 24 3 &pcfg_pull_none_12ma>,
1487 <3 25 3 &pcfg_pull_none_12ma>,
1488 <4 0 3 &pcfg_pull_none>,
1489 <4 5 3 &pcfg_pull_none>,
1490 <4 6 3 &pcfg_pull_none>,
1491 <4 9 3 &pcfg_pull_none_12ma>,
1492 <4 4 3 &pcfg_pull_none_12ma>,
1493 <4 1 3 &pcfg_pull_none>,
1494 <4 3 3 &pcfg_pull_none>;
1497 rmii_pins: rmii-pins {
1498 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1499 <3 31 3 &pcfg_pull_none>,
1500 <3 28 3 &pcfg_pull_none>,
1501 <3 29 3 &pcfg_pull_none>,
1502 <4 0 3 &pcfg_pull_none>,
1503 <4 5 3 &pcfg_pull_none>,
1504 <4 4 3 &pcfg_pull_none>,
1505 <4 1 3 &pcfg_pull_none>,
1506 <4 2 3 &pcfg_pull_none>,
1507 <4 3 3 &pcfg_pull_none>;
1512 spdif_tx: spdif-tx {
1513 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;