1 #include <dt-bindings/clock/rk_system_status.h>
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include <dt-bindings/rkfb/rk_fb.h>
4 #include <dt-bindings/rkmipi/mipi_dsi.h>
5 #include <dt-bindings/suspend/rockchip-pm.h>
6 #include <dt-bindings/sensor-dev.h>
8 #include "skeleton.dtsi"
9 #include "rk3288-pinctrl.dtsi"
10 #include "rk3288-clocks.dtsi"
13 compatible = "rockchip,rk3288";
14 rockchip,sram = <&sram>;
15 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a15";
47 compatible = "arm,cortex-a15";
52 compatible = "arm,cortex-a15";
57 compatible = "arm,cortex-a15";
62 gic: interrupt-controller@ffc01000 {
63 compatible = "arm,cortex-a15-gic";
65 #interrupt-cells = <3>;
67 reg = <0xffc01000 0x1000>,
72 compatible = "arm,cortex-a12-pmu";
73 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
79 cpu_axi_bus: cpu_axi_bus {
80 compatible = "rockchip,cpu_axi_bus";
91 reg = <0xffa80000 0x20>;
94 reg = <0xffa80080 0x20>;
97 reg = <0xffa80100 0x20>;
101 reg = <0xffa90000 0x20>;
104 reg = <0xffa90080 0x20>;
107 reg = <0xffa90100 0x20>;
110 reg = <0xffa90180 0x20>;
113 reg = <0xffa90200 0x20>;
117 reg = <0xffaa0000 0x20>;
120 reg = <0xffaa0080 0x20>;
124 reg = <0xffab0000 0x20>;
128 reg = <0xffad0000 0x20>;
129 rockchip,priority = <2 2>;
132 reg = <0xffad0100 0x20>;
135 reg = <0xffad0180 0x20>;
138 reg = <0xffad0400 0x20>;
139 rockchip,priority = <2 2>;
142 reg = <0xffad0480 0x20>;
145 reg = <0xffad0500 0x20>;
148 reg = <0xffad0800 0x20>;
151 reg = <0xffad0880 0x20>;
154 reg = <0xffad0900 0x20>;
158 reg = <0xffae0000 0x20>;
162 reg = <0xffaf0000 0x20>;
165 reg = <0xffaf0080 0x20>;
170 #address-cells = <1>;
175 reg = <0xffac0000 0x40>;
176 rockchip,read-latency = <0x34>;
179 reg = <0xffac0080 0x40>;
180 rockchip,read-latency = <0x34>;
185 sram: sram@ff710000 {
186 compatible = "mmio-sram";
187 reg = <0xff710000 0x8000>; /* 32k */
192 compatible = "arm,armv7-timer";
193 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
194 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
195 clock-frequency = <24000000>;
199 compatible = "rockchip,timer";
200 reg = <0xff810000 0x20>;
201 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
202 rockchip,broadcast = <1>;
205 watchdog: wdt@2004c000 {
206 compatible = "rockchip,watch dog";
207 reg = <0xff800000 0x100>;
208 clocks = <&pclk_pd_alive>;
209 clock-names = "pclk_wdt";
210 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
212 rockchip,timeout = <60>;
213 rockchip,atboot = <1>;
214 rockchip,debug = <0>;
219 #address-cells = <1>;
221 compatible = "arm,amba-bus";
222 interrupt-parent = <&gic>;
225 pdma0: pdma@ffb20000 {
226 compatible = "arm,pl330", "arm,primecell";
227 reg = <0xffb20000 0x4000>;
228 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
233 pdma1: pdma@ff250000 {
234 compatible = "arm,pl330", "arm,primecell";
235 reg = <0xff250000 0x4000>;
236 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
242 nandc0: nandc@0xff400000 {
243 compatible = "rockchip,rk-nandc";
244 reg = <0xff400000 0x4000>;
245 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
248 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
251 nandc1: nandc@0xff410000 {
252 compatible = "rockchip,rk-nandc";
253 reg = <0xff410000 0x4000>;
254 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
257 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
260 nandc0reg: nandc0@0xff400000 {
261 compatible = "rockchip,rk-nandc";
262 reg = <0xff400000 0x4000>;
265 emmc: rksdmmc@ff0f0000 {
266 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
267 reg = <0xff0f0000 0x4000>;
268 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
269 #address-cells = <1>;
271 //pinctrl-names = "default",,"suspend";
272 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
273 clocks = <&clk_emmc>, <&clk_gates8 6>;
274 clock-names = "clk_mmc", "hclk_mmc";
276 fifo-depth = <0x100>;
280 sdmmc: rksdmmc@ff0c0000 {
281 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
282 reg = <0xff0c0000 0x4000>;
283 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>;
286 pinctrl-names = "default", "idle";
287 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
288 pinctrl-1 = <&sdmmc0_gpio>;
289 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
290 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
291 clock-names = "clk_mmc", "hclk_mmc";
293 fifo-depth = <0x100>;
297 sdio: rksdmmc@ff0d0000 {
298 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
299 reg = <0xff0d0000 0x4000>;
300 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
301 #address-cells = <1>;
303 pinctrl-names = "default","idle";
304 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
305 &sdio0_intn &sdio0_bus4>;
306 pinctrl-1 = <&sdio0_gpio>;
307 clocks = <&clk_sdio0>, <&clk_gates8 4>;
308 clock-names = "clk_mmc", "hclk_mmc";
310 fifo-depth = <0x100>;
314 sdio1: rksdmmc@ff0e0000 {
315 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
316 reg = <0xff0e0000 0x4000>;
317 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>;
320 //pinctrl-names = "default","suspend";
321 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
322 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
323 clocks = <&clk_sdio1>, <&clk_gates8 5>;
324 clock-names = "clk_mmc", "hclk_mmc";
326 fifo-depth = <0x100>;
332 compatible = "rockchip,rockchip-spi";
333 reg = <0xff110000 0x1000>;
334 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
335 #address-cells = <1>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
339 rockchip,spi-src-clk = <0>;
341 clocks =<&clk_spi0>, <&clk_gates6 4>;
342 clock-names = "spi","pclk_spi0";
343 //dmas = <&pdma1 11>, <&pdma1 12>;
345 //dma-names = "tx", "rx";
350 compatible = "rockchip,rockchip-spi";
351 reg = <0xff120000 0x1000>;
352 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
357 rockchip,spi-src-clk = <1>;
359 clocks = <&clk_spi1>, <&clk_gates6 5>;
360 clock-names = "spi","pclk_spi1";
361 //dmas = <&pdma1 13>, <&pdma1 14>;
363 //dma-names = "tx", "rx";
368 compatible = "rockchip,rockchip-spi";
369 reg = <0xff130000 0x1000>;
370 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
371 #address-cells = <1>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
375 rockchip,spi-src-clk = <2>;
377 clocks = <&clk_spi2>, <&clk_gates6 6>;
378 clock-names = "spi","pclk_spi2";
379 //dmas = <&pdma1 15>, <&pdma1 16>;
381 //dma-names = "tx", "rx";
385 uart_bt: serial@ff180000 {
386 compatible = "rockchip,serial";
387 reg = <0xff180000 0x100>;
388 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
389 clock-frequency = <24000000>;
390 clocks = <&clk_uart0>, <&clk_gates6 8>;
391 clock-names = "sclk_uart", "pclk_uart";
394 dmas = <&pdma1 1>, <&pdma1 2>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
401 uart_bb: serial@ff190000 {
402 compatible = "rockchip,serial";
403 reg = <0xff190000 0x100>;
404 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
405 clock-frequency = <24000000>;
406 clocks = <&clk_uart1>, <&clk_gates6 9>;
407 clock-names = "sclk_uart", "pclk_uart";
410 dmas = <&pdma1 3>, <&pdma1 4>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
417 uart_dbg: serial@ff690000 {
418 compatible = "rockchip,serial";
419 reg = <0xff690000 0x100>;
420 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
421 clock-frequency = <24000000>;
422 clocks = <&clk_uart2>, <&clk_gates11 9>;
423 clock-names = "sclk_uart", "pclk_uart";
426 dmas = <&pdma0 4>, <&pdma0 5>;
428 pinctrl-names = "default";
429 pinctrl-0 = <&uart2_xfer>;
433 uart_gps: serial@ff1b0000 {
434 compatible = "rockchip,serial";
435 reg = <0xff1b0000 0x100>;
436 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
437 clock-frequency = <24000000>;
438 clocks = <&clk_uart3>, <&clk_gates6 11>;
439 clock-names = "sclk_uart", "pclk_uart";
440 current-speed = <115200>;
443 dmas = <&pdma1 7>, <&pdma1 8>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
450 uart_exp: serial@ff1c0000 {
451 compatible = "rockchip,serial";
452 reg = <0xff1c0000 0x100>;
453 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
454 clock-frequency = <24000000>;
455 clocks = <&clk_uart4>, <&clk_gates6 12>;
456 clock-names = "sclk_uart", "pclk_uart";
459 dmas = <&pdma1 9>, <&pdma1 10>;
461 pinctrl-names = "default";
462 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
467 compatible = "rockchip,fiq-debugger";
468 rockchip,serial-id = <2>;
469 rockchip,signal-irq = <106>;
470 rockchip,wake-irq = <0>;
475 compatible = "rockchip,clocks-init";
476 rockchip,clocks-init-parent =
477 <&clk_core &clk_apll>, <&aclk_bus_src &clk_gpll>,
478 <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
479 <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
480 <&usbphy_480m &otgphy2_480m>;
481 rockchip,clocks-init-rate =
482 <&clk_core 792000000>, <&clk_gpll 297000000>,
483 /*<&clk_cpll 47000000>,*/ <&clk_npll 1250000000>,
484 <&aclk_bus_src 300000000>, <&aclk_bus 300000000>,
485 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
486 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
487 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
488 <&clk_gpu 200000000>, <&aclk_vio0 300000000>,
489 <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
490 <&pclk_pd_alive 100000000>, <&pclk_pd_pmu 100000000>,
491 <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
492 <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
493 <&aclk_rga 300000000>, <&clk_rga 300000000>,
494 <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
495 <&clk_edp 200000000>, <&clk_isp 200000000>,
496 <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
497 <&clk_tspout 80000000>, <&clk_mac 125000000>;
498 rockchip,clocks-uboot-has-init =
503 compatible = "rockchip,clocks-enable";
506 <&clk_gates0 2>, <&clk_core0>,
507 <&clk_core1>, <&clk_core2>,
508 <&clk_core3>, <&clk_l2ram>,
509 <&aclk_core_m0>, <&aclk_core_mp>,
510 <&atclk_core>, <&pclk_dbg_src>,
511 <&clk_gates12 9>, <&clk_gates12 10>,
515 <&aclk_bus>, <&clk_gates0 3>,
516 <&hclk_bus>, <&pclk_bus>,
517 <&clk_gates13 8>, <&clk_crypto>,
521 <&clk_gates1 0>, <&clk_gates1 1>,
522 <&clk_gates1 2>, <&clk_gates1 3>,
523 <&clk_gates1 4>, <&clk_gates1 5>,
525 <&pclk_pd_alive>, <&pclk_pd_pmu>,
528 <&aclk_peri>, <&hclk_peri>,
532 /*<&clk_gates4 14>,*/
535 <&clk_gates10 5>,/*aclk_intmem0*/
536 <&clk_gates10 6>,/*aclk_intmem1*/
537 <&clk_gates10 7>,/*aclk_intmem2*/
538 <&clk_gates10 12>,/*aclk_dma1*/
539 <&clk_gates10 13>,/*aclk_strc_sys*/
540 <&clk_gates10 4>,/*aclk_intmem*/
541 <&clk_gates11 6>,/*aclk_crypto*/
542 <&clk_gates11 8>,/*aclk_ccp*/
545 <&clk_gates11 7>,/*hclk_crypto*/
546 <&clk_gates10 9>,/*hclk_rom*/
549 <&clk_gates10 1>,/*pclk_timer*/
550 <&clk_gates10 9>,/*rom*/
551 <&clk_gates10 13>,/*aclk strc*/
553 <&clk_gates12 8>,/*aclk strc*/
556 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
557 <&clk_gates6 3>,/*aclk_dmac2*/
558 <&clk_gates7 11>,/*aclk_peri_niu*/
559 <&clk_gates8 12>,/*aclk_peri_mmu*/
562 <&clk_gates6 0>,/*hclk_peri_matrix*/
563 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
564 <&clk_gates7 12>,/*hclk_emem_peri*/
565 <&clk_gates7 13>,/*hclk_mem_peri*/
568 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
571 <&clk_gates14 11>,/*pclk_grf*/
572 <&clk_gates14 12>,/*pclk_alive_niu*/
575 <&clk_gates17 0>,/*pclk_pmu*/
576 <&clk_gates17 1>,/*pclk_intmem1*/
577 <&clk_gates17 2>,/*pclk_pmu_niu*/
578 <&clk_gates17 3>,/*pclk_sgrf*/
581 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
582 <&clk_gates15 10>,/*hclk_vio_niu*/
583 <&clk_gates16 10>,/*hclk_vio2_h2p*/
584 <&clk_gates16 11>,/*pclk_vio2_h2p*/
587 <&clk_gates15 11>,/*aclk_vio0_niu*/
590 <&clk_gates15 12>,/*aclk_vio1_niu*/
593 //<&clk_gates5 12>,/*hdmi_hdcp_clk*/
596 <&clk_gates11 9>,/*pclk_uart2*/
603 compatible = "rockchip,rk30-i2c";
604 reg = <0xff650000 0x1000>;
605 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
606 #address-cells = <1>;
608 pinctrl-names = "default", "gpio";
609 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
610 pinctrl-1 = <&i2c0_gpio>;
611 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
612 clocks = <&clk_gates10 2>;
613 rockchip,check-idle = <1>;
618 compatible = "rockchip,rk30-i2c";
619 reg = <0xff140000 0x1000>;
620 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
621 #address-cells = <1>;
623 pinctrl-names = "default", "gpio";
624 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
625 pinctrl-1 = <&i2c1_gpio>;
626 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
627 clocks = <&clk_gates10 3>;
628 rockchip,check-idle = <1>;
633 compatible = "rockchip,rk30-i2c";
634 reg = <0xff660000 0x1000>;
635 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
636 #address-cells = <1>;
638 pinctrl-names = "default", "gpio";
639 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
640 pinctrl-1 = <&i2c2_gpio>;
641 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
642 clocks = <&clk_gates6 13>;
643 rockchip,check-idle = <1>;
648 compatible = "rockchip,rk30-i2c";
649 reg = <0xff150000 0x1000>;
650 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
651 #address-cells = <1>;
653 pinctrl-names = "default", "gpio";
654 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
655 pinctrl-1 = <&i2c3_gpio>;
656 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
657 clocks = <&clk_gates6 14>;
658 rockchip,check-idle = <1>;
663 compatible = "rockchip,rk30-i2c";
664 reg = <0xff160000 0x1000>;
665 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
666 #address-cells = <1>;
668 pinctrl-names = "default", "gpio";
669 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
670 pinctrl-1 = <&i2c4_gpio>;
671 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
672 clocks = <&clk_gates6 15>;
673 rockchip,check-idle = <1>;
678 compatible = "rockchip,rk30-i2c";
679 reg = <0xff170000 0x1000>;
680 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
681 #address-cells = <1>;
683 pinctrl-names = "default", "gpio";
684 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
685 pinctrl-1 = <&i2c5_gpio>;
686 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
687 clocks = <&clk_gates7 0>;
688 rockchip,check-idle = <1>;
693 compatible = "rockchip,rk-fb";
694 rockchip,disp-mode = <DUAL>;
697 rk_screen: rk_screen{
698 compatible = "rockchip,screen";
701 dsihost0: mipi@ff960000{
702 compatible = "rockchip,rk32-dsi";
704 reg = <0xff960000 0x4000>;
705 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
707 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
711 dsihost1: mipi@ff964000{
712 compatible = "rockchip,rk32-dsi";
714 reg = <0xff964000 0x4000>;
715 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
717 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
721 lvds: lvds@ff96c000 {
722 compatible = "rockchip,rk32-lvds";
723 reg = <0xff96c000 0x4000>;
724 clocks = <&clk_gates16 7>;
725 clock-names = "pclk_lvds";
729 compatible = "rockchip,rk32-edp";
730 reg = <0xff970000 0x4000>;
731 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
733 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
736 hdmi: hdmi@ff980000 {
737 compatible = "rockchip,rk3288-hdmi";
738 reg = <0xff980000 0x20000>;
739 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
740 pinctrl-names = "default", "sleep";
741 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
742 pinctrl-1 = <&i2c5_gpio>;
743 clocks = <&clk_gates16 9>, <&clk_gates5 12>;
744 clock-names = "pclk_hdmi", "hdcp_clk_hdmi";
748 lcdc1: lcdc@ff940000 {
749 compatible = "rockchip,rk3288-lcdc";
750 rockchip,prop = <PRMRY>;
751 rochchip,pwr18 = <0>;
752 rockchip,iommu-enabled = <1>;
753 reg = <0xff940000 0x10000>;
754 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
755 pinctrl-names = "default", "gpio";
756 pinctrl-0 = <&lcdc0_lcdc>;
757 pinctrl-1 = <&lcdc0_gpio>;
759 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
760 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
763 lcdc0: lcdc@ff930000 {
764 compatible = "rockchip,rk3288-lcdc";
765 rockchip,prop = <EXTEND>;
766 rockchip,pwr18 = <0>;
767 rockchip,iommu-enabled = <1>;
768 reg = <0xff930000 0x10000>;
769 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
770 //pinctrl-names = "default", "gpio";
771 //pinctrl-0 = <&lcdc0_lcdc>;
772 //pinctrl-1 = <&lcdc0_gpio>;
774 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
775 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
779 compatible = "rockchip,saradc";
780 reg = <0xff100000 0x100>;
781 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
782 #io-channel-cells = <1>;
784 rockchip,adc-vref = <1800>;
785 clock-frequency = <1000000>;
786 clocks = <&clk_saradc>, <&clk_gates7 1>;
787 clock-names = "saradc", "pclk_saradc";
792 compatible = "rockchip,rga";
793 reg = <0xff920000 0x1000>;
794 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
796 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
799 i2s: rockchip-i2s@0xff890000 {
800 compatible = "rockchip-i2s";
801 reg = <0xff890000 0x10000>;
803 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
804 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
805 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
806 dmas = <&pdma0 0>, <&pdma0 1>;
808 dma-names = "tx", "rx";
809 pinctrl-names = "default", "sleep";
810 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
811 pinctrl-1 = <&i2s_gpio>;
814 spdif: rockchip-spdif@0xff8b0000 {
815 compatible = "rockchip-spdif";
816 reg = <0xff8b0000 0x10000>; //8channel
817 //reg = <ff880000 0x10000>;//2channel
818 clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
819 clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
820 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
822 //dmas = <&pdma0 2>; //2channel
825 pinctrl-names = "default";
826 pinctrl-0 = <&spdif_tx>;
829 vop1pwm: pwm@ff9401a0 {
830 compatible = "rockchip,vop-pwm";
831 reg = <0xff9401a0 0x10>;
833 pinctrl-names = "default";
834 pinctrl-0 = <&vop1_pwm_pin>;
835 clocks = <&clk_gates13 11>;
836 clock-names = "pclk_pwm";
840 vop0pwm: pwm@ff9301a0 {
841 compatible = "rockchip,vop-pwm";
842 reg = <0xff9301a0 0x10>;
844 pinctrl-names = "default";
845 pinctrl-0 = <&vop0_pwm_pin>;
846 clocks = <&clk_gates13 10>;
847 clock-names = "pclk_pwm";
852 compatible = "rockchip,rk-pwm";
853 reg = <0xff680000 0x10>;
855 pinctrl-names = "default";
856 pinctrl-0 = <&pwm0_pin>;
857 clocks = <&clk_gates11 11>;
858 clock-names = "pclk_pwm";
863 compatible = "rockchip,rk-pwm";
864 reg = <0xff680010 0x10>;
866 pinctrl-names = "default";
867 pinctrl-0 = <&pwm1_pin>;
868 clocks = <&clk_gates11 11>;
869 clock-names = "pclk_pwm";
874 compatible = "rockchip,rk-pwm";
875 reg = <0xff680020 0x10>;
877 pinctrl-names = "default";
878 pinctrl-0 = <&pwm2_pin>;
879 clocks = <&clk_gates11 11>;
880 clock-names = "pclk_pwm";
885 compatible = "rockchip,rk-pwm";
886 reg = <0xff680030 0x10>;
888 pinctrl-names = "default";
889 pinctrl-0 = <&pwm3_pin>;
890 clocks = <&clk_gates11 11>;
891 clock-names = "pclk_pwm";
896 temp-limit-enable = <1>;
900 regulator_name = "vdd_arm";
901 suspend_volt = <1000>; //mV
903 clk_core_dvfs_table: clk_core {
912 normal-temp-limit = <
913 /*delta-temp delta-freq*/
919 performance-temp-limit = <
929 regulator_name = "vdd_logic";
930 suspend_volt = <1000>; //mV
932 clk_ddr_dvfs_table: clk_ddr {
944 aclk_vio1_dvfs_table: aclk_vio1 {
956 regulator_name = "vdd_gpu";
957 suspend_volt = <1000>; //mV
959 clk_gpu_dvfs_table: clk_gpu {
973 compatible = "rockchip,ion";
974 #address-cells = <1>;
977 rockchip,ion-heap@1 { /* CMA HEAP */
978 compatible = "rockchip,ion-reserve";
979 rockchip,ion_heap = <1>;
980 reg = <0x00000000 0x20000000>; /* 512MB */
982 rockchip,ion-heap@3 { /* VMALLOC HEAP */
983 rockchip,ion_heap = <3>;
987 vpu: vpu_service@ff9a0000 {
988 compatible = "vpu_service";
989 reg = <0xff9a0000 0x800>;
990 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
991 interrupt-names = "irq_enc", "irq_dec";
992 clocks = <&clk_vdpu>, <&hclk_vdpu>;
993 clock-names = "aclk_vcodec", "hclk_vcodec";
994 name = "vpu_service";
995 //status = "disabled";
998 hevc: hevc_service@ff9c0000 {
999 compatible = "rockchip,hevc_service";
1000 reg = <0xff9c0000 0x800>;
1001 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1002 interrupt-names = "irq_dec";
1003 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1004 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1005 name = "hevc_service";
1006 //status = "disabled";
1010 compatible = "rockchip,iep";
1011 reg = <0xff900000 0x800>;
1012 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1014 clock-names = "aclk_iep", "hclk_iep";
1018 dwc_control_usb: dwc-control-usb@ff770284 {
1019 compatible = "rockchip,rk3288-dwc-control-usb";
1020 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1021 <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1022 <0xff770320 0x14>, <0xff770334 0x14>,
1023 <0xff770348 0x10>, <0xff770358 0x08>,
1025 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1026 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1027 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1028 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1030 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1031 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1033 interrupt-names = "otg_id", "otg_bvalid",
1034 "otg_linestate", "host0_linestate",
1036 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1037 <&otgphy1_480m>, <&otgphy2_480m>;
1038 clock-names = "hclk_usb_peri", "usbphy_480m",
1039 "usbphy1_480m", "usbphy2_480m";
1042 compatible = "synopsys,phy";
1043 /* offset bit mask */
1044 rk_usb,bvalid = <0x288 14 1>;
1045 rk_usb,iddig = <0x288 17 1>;
1046 rk_usb,dcdenb = <0x328 14 1>;
1047 rk_usb,vdatsrcenb = <0x328 7 1>;
1048 rk_usb,vdatdetenb = <0x328 6 1>;
1049 rk_usb,chrgsel = <0x328 5 1>;
1050 rk_usb,chgdet = <0x2cc 23 1>;
1051 rk_usb,fsvminus = <0x2cc 25 1>;
1052 rk_usb,fsvplus = <0x2cc 24 1>;
1056 usb0: usb@ff580000 {
1057 compatible = "rockchip,rk3288_usb20_otg";
1058 reg = <0xff580000 0x40000>;
1059 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1061 clock-names = "clk_usbphy0", "hclk_usb0";
1062 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1063 rockchip,usb-mode = <0>;
1066 usb1: usb@ff540000 {
1067 compatible = "rockchip,rk3288_usb20_host";
1068 reg = <0xff540000 0x40000>;
1069 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1072 clock-names = "clk_usbphy1", "hclk_usb1",
1076 usb2: usb@ff500000 {
1077 compatible = "rockchip,rk3288_rk_ehci_host";
1078 reg = <0xff500000 0x20000>;
1079 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1081 clock-names = "clk_usbphy2", "hclk_usb2";
1084 usb3: usb@ff520000 {
1085 compatible = "rockchip,rk3288_rk_ohci_host";
1086 reg = <0xff520000 0x20000>;
1087 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1089 clock-names = "clk_usbphy3", "hclk_usb3";
1092 hsic: hsic@ff5c0000 {
1093 compatible = "rockchip,rk3288_rk_hsic_host";
1094 reg = <0xff5c0000 0x40000>;
1095 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1097 <&hsicphy_12m>, <&usbphy_480m>,
1098 <&otgphy1_480m>, <&otgphy2_480m>;
1099 clock-names = "hsicphy_480m", "hclk_hsic",
1100 "hsicphy_12m", "usbphy_480m",
1101 "hsic_usbphy1", "hsic_usbphy2";
1104 gmac: eth@ff290000 {
1105 compatible = "rockchip,gmac";
1106 reg = <0xff290000 0x10000>;
1107 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1108 interrupt-names = "macirq";
1109 clocks = <&clk_mac>, <&clk_gates5 0>,
1110 <&clk_gates5 1>, <&clk_gates5 2>,
1111 <&clk_gates5 3>, <&clk_gates8 0>,
1113 clock-names = "clk_mac", "mac_clk_rx",
1114 "mac_clk_tx", "clk_mac_ref",
1115 "clk_mac_refout", "aclk_mac",
1117 //phy-mode = "rmii";
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1124 compatible = "arm,malit764",
1128 reg = <0xffa30000 0x10000>;
1129 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1130 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1131 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1132 interrupt-names = "JOB", "MMU", "GPU";
1137 compatible = "iommu,iep_mmu";
1138 reg = <0xff900800 0x100>;
1139 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1140 interrupt-names = "iep_mmu";
1145 compatible = "iommu,vip_mmu";
1146 reg = <0xff950800 0x100>;
1147 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1148 interrupt-names = "vip_mmu";
1153 compatible = "iommu,vopb_mmu";
1154 reg = <0xff930300 0x100>;
1155 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1156 interrupt-names = "vopb_mmu";
1161 compatible = "iommu,vopl_mmu";
1162 reg = <0xff940300 0x100>;
1163 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1164 interrupt-names = "vopl_mmu";
1169 compatible = "iommu,hevc_mmu";
1170 reg = <0xff9c0440 0x100>,
1172 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1173 interrupt-names = "hevc_mmu";
1178 compatible = "iommu,vpu_mmu";
1179 reg = <0xff9a0800 0x100>;
1180 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1181 interrupt-names = "vpu_mmu";
1185 dbgname = "isp_mmu";
1186 compatible = "iommu,isp_mmu";
1187 reg = <0xff914000 0x100>,
1189 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1190 interrupt-names = "isp_mmu";
1194 rockchip,ctrbits = <
1199 // |RKPM_CTR_SYSCLK_DIV
1200 // |RKPM_CTR_IDLEAUTO_MD
1201 // |RKPM_CTR_ARMOFF_LPMD
1202 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1205 rockchip,pmic-gpios = <
1206 RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
1207 RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
1212 compatible = "rockchip,isp";
1213 reg = <0xff910000 0x10000>;
1214 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
1216 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
1217 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1218 pinctrl-0 = <&isp_mipi>;
1219 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1220 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1221 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1222 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1223 pinctrl-5 = <&isp_mipi>;
1224 pinctrl-6 = <&isp_mipi &isp_prelight>;
1225 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1226 pinctrl-8 = <&isp_flash_trigger>;
1227 rockchip,isp,mipiphy = <2>;
1228 rockchip,isp,cifphy = <1>;
1229 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1230 rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
1234 tsadc: tsadc@ff280000 {
1235 compatible = "rockchip,tsadc";
1236 reg = <0xff280000 0x100>;
1237 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1238 #io-channel-cells = <1>;
1240 clock-frequency = <50000>;
1241 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1242 clock-names = "tsadc", "pclk_tsadc";
1246 lcdc_vdd_domain: lcdc-vdd-domain {
1247 compatible = "rockchip,io_vol_domain";
1248 pinctrl-names = "default", "1.8V", "3.3V";
1249 pinctrl-0 = <&lcdc_vcc>;
1250 pinctrl-1 = <&lcdc_vcc_18>;
1251 pinctrl-2 = <&lcdc_vcc_33>;
1254 dpio_vdd_domain: dpio-vdd-domain {
1255 compatible = "rockchip,io_vol_domain";
1256 pinctrl-names = "default", "1.8V", "3.3V";
1257 pinctrl-0 = <&dvp_vcc>;
1258 pinctrl-1 = <&dvp_vcc_18>;
1259 pinctrl-2 = <&dvp_vcc_33>;
1262 flash0_vdd_domain: flash0-vdd-domain {
1263 compatible = "rockchip,io_vol_domain";
1264 pinctrl-names = "default", "1.8V", "3.3V";
1265 pinctrl-0 = <&flash0_vcc>;
1266 pinctrl-1 = <&flash0_vcc_18>;
1267 pinctrl-2 = <&flash0_vcc_33>;
1270 flash1_vdd_domain: flash1-vdd-domain {
1271 compatible = "rockchip,io_vol_domain";
1272 pinctrl-names = "default", "1.8V", "3.3V";
1273 pinctrl-0 = <&flash1_vcc>;
1274 pinctrl-1 = <&flash1_vcc_18>;
1275 pinctrl-2 = <&flash1_vcc_33>;
1278 apio3_vdd_domain: apio3-vdd-domain {
1279 compatible = "rockchip,io_vol_domain";
1280 pinctrl-names = "default", "1.8V", "3.3V";
1281 pinctrl-0 = <&wifi_vcc>;
1282 pinctrl-1 = <&wifi_vcc_18>;
1283 pinctrl-2 = <&wifi_vcc_33>;
1286 apio5_vdd_domain: apio5-vdd-domain {
1287 compatible = "rockchip,io_vol_domain";
1288 pinctrl-names = "default", "1.8V", "3.3V";
1289 pinctrl-0 = <&bb_vcc>;
1290 pinctrl-1 = <&bb_vcc_18>;
1291 pinctrl-2 = <&bb_vcc_33>;
1294 apio4_vdd_domain: apio4-vdd-domain {
1295 compatible = "rockchip,io_vol_domain";
1296 pinctrl-names = "default", "1.8V", "3.3V";
1297 pinctrl-0 = <&audio_vcc>;
1298 pinctrl-1 = <&audio_vcc_18>;
1299 pinctrl-2 = <&audio_vcc_33>;
1302 apio1_vdd_domain: apio0-vdd-domain {
1303 compatible = "rockchip,io_vol_domain";
1304 pinctrl-names = "default", "1.8V", "3.3V";
1305 pinctrl-0 = <&gpio30_vcc>;
1306 pinctrl-1 = <&gpio30_vcc_18>;
1307 pinctrl-2 = <&gpio30_vcc_33>;
1310 apio2_vdd_domain: apio2-vdd-domain {
1311 compatible = "rockchip,io_vol_domain";
1312 pinctrl-names = "default", "1.8V", "3.3V";
1313 pinctrl-0 = <&gpio1830_vcc>;
1314 pinctrl-1 = <&gpio1830_vcc_18>;
1315 pinctrl-2 = <&gpio1830_vcc_33>;
1318 sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1319 compatible = "rockchip,io_vol_domain";
1320 pinctrl-names = "default", "1.8V", "3.3V";
1321 pinctrl-0 = <&sdcard_vcc>;
1322 pinctrl-1 = <&sdcard_vcc_18>;
1323 pinctrl-2 = <&sdcard_vcc_33>;