2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include "skeleton.dtsi"
51 compatible = "rockchip,rk3288";
53 interrupt-parent = <&gic>;
77 compatible = "arm,cortex-a12-pmu";
78 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
82 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 enable-method = "rockchip,rk3066-smp";
89 rockchip,pmu = <&pmu>;
93 compatible = "arm,cortex-a12";
95 resets = <&cru SRST_CORE0>;
111 #cooling-cells = <2>; /* min followed by max */
112 clock-latency = <40000>;
113 clocks = <&cru ARMCLK>;
117 compatible = "arm,cortex-a12";
119 resets = <&cru SRST_CORE1>;
123 compatible = "arm,cortex-a12";
125 resets = <&cru SRST_CORE2>;
129 compatible = "arm,cortex-a12";
131 resets = <&cru SRST_CORE3>;
136 compatible = "arm,amba-bus";
137 #address-cells = <1>;
141 dmac_peri: dma-controller@ff250000 {
142 compatible = "arm,pl330", "arm,primecell";
143 reg = <0xff250000 0x4000>;
144 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
147 arm,pl330-broken-no-flushp;
148 peripherals-req-type-burst;
149 clocks = <&cru ACLK_DMAC2>;
150 clock-names = "apb_pclk";
153 dmac_bus_ns: dma-controller@ff600000 {
154 compatible = "arm,pl330", "arm,primecell";
155 reg = <0xff600000 0x4000>;
156 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
159 arm,pl330-broken-no-flushp;
160 peripherals-req-type-burst;
161 clocks = <&cru ACLK_DMAC1>;
162 clock-names = "apb_pclk";
166 dmac_bus_s: dma-controller@ffb20000 {
167 compatible = "arm,pl330", "arm,primecell";
168 reg = <0xffb20000 0x4000>;
169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
172 arm,pl330-broken-no-flushp;
173 peripherals-req-type-burst;
174 clocks = <&cru ACLK_DMAC1>;
175 clock-names = "apb_pclk";
180 #address-cells = <1>;
185 * The rk3288 cannot use the memory area above 0xfe000000
186 * for dma operations for some reason. While there is
187 * probably a better solution available somewhere, we
188 * haven't found it yet and while devices with 2GB of ram
189 * are not affected, this issue prevents 4GB from booting.
190 * So to make these devices at least bootable, block
191 * this area for the time being until the real solution
194 dma-unusable@fe000000 {
195 reg = <0xfe000000 0x1000000>;
200 compatible = "fixed-clock";
201 clock-frequency = <24000000>;
202 clock-output-names = "xin24m";
207 compatible = "rockchip,rk3288-dp-phy";
208 clocks = <&cru SCLK_EDP_24M>;
210 rockchip,grf = <&grf>;
216 compatible = "arm,armv7-timer";
217 arm,cpu-registers-not-fw-configured;
218 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
220 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
221 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
222 clock-frequency = <24000000>;
225 timer: timer@ff810000 {
226 compatible = "rockchip,rk3288-timer";
227 reg = <0xff810000 0x20>;
228 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&xin24m>, <&cru PCLK_TIMER>;
230 clock-names = "timer", "pclk";
234 compatible = "rockchip,display-subsystem";
235 ports = <&vopl_out>, <&vopb_out>;
238 sdmmc: dwmmc@ff0c0000 {
239 compatible = "rockchip,rk3288-dw-mshc";
240 clock-freq-min-max = <400000 150000000>;
241 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
242 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
243 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
244 fifo-depth = <0x100>;
245 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
246 reg = <0xff0c0000 0x4000>;
250 sdio0: dwmmc@ff0d0000 {
251 compatible = "rockchip,rk3288-dw-mshc";
252 clock-freq-min-max = <400000 150000000>;
253 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
254 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
256 fifo-depth = <0x100>;
257 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
258 reg = <0xff0d0000 0x4000>;
262 sdio1: dwmmc@ff0e0000 {
263 compatible = "rockchip,rk3288-dw-mshc";
264 clock-freq-min-max = <400000 150000000>;
265 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
266 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
267 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
268 fifo-depth = <0x100>;
269 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
270 reg = <0xff0e0000 0x4000>;
274 emmc: dwmmc@ff0f0000 {
275 compatible = "rockchip,rk3288-dw-mshc";
276 clock-freq-min-max = <400000 150000000>;
277 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
278 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
279 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
280 fifo-depth = <0x100>;
281 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
282 reg = <0xff0f0000 0x4000>;
286 saradc: saradc@ff100000 {
287 compatible = "rockchip,saradc";
288 reg = <0xff100000 0x100>;
289 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
290 #io-channel-cells = <1>;
291 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
292 clock-names = "saradc", "apb_pclk";
297 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
298 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
299 clock-names = "spiclk", "apb_pclk";
300 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
301 dma-names = "tx", "rx";
302 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
305 reg = <0xff110000 0x1000>;
306 #address-cells = <1>;
312 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
313 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
314 clock-names = "spiclk", "apb_pclk";
315 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
316 dma-names = "tx", "rx";
317 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
320 reg = <0xff120000 0x1000>;
321 #address-cells = <1>;
327 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
328 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
329 clock-names = "spiclk", "apb_pclk";
330 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
331 dma-names = "tx", "rx";
332 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
335 reg = <0xff130000 0x1000>;
336 #address-cells = <1>;
342 compatible = "rockchip,rk3288-i2c";
343 reg = <0xff140000 0x1000>;
344 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
345 #address-cells = <1>;
348 clocks = <&cru PCLK_I2C1>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&i2c1_xfer>;
355 compatible = "rockchip,rk3288-i2c";
356 reg = <0xff150000 0x1000>;
357 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
358 #address-cells = <1>;
361 clocks = <&cru PCLK_I2C3>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&i2c3_xfer>;
368 compatible = "rockchip,rk3288-i2c";
369 reg = <0xff160000 0x1000>;
370 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
371 #address-cells = <1>;
374 clocks = <&cru PCLK_I2C4>;
375 pinctrl-names = "default";
376 pinctrl-0 = <&i2c4_xfer>;
381 compatible = "rockchip,rk3288-i2c";
382 reg = <0xff170000 0x1000>;
383 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
384 #address-cells = <1>;
387 clocks = <&cru PCLK_I2C5>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&i2c5_xfer>;
393 uart0: serial@ff180000 {
394 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
395 reg = <0xff180000 0x100>;
396 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
400 clock-names = "baudclk", "apb_pclk";
401 pinctrl-names = "default";
402 pinctrl-0 = <&uart0_xfer>;
406 uart1: serial@ff190000 {
407 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
408 reg = <0xff190000 0x100>;
409 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
413 clock-names = "baudclk", "apb_pclk";
414 pinctrl-names = "default";
415 pinctrl-0 = <&uart1_xfer>;
419 uart2: serial@ff690000 {
420 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
421 reg = <0xff690000 0x100>;
422 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
426 clock-names = "baudclk", "apb_pclk";
427 pinctrl-names = "default";
428 pinctrl-0 = <&uart2_xfer>;
432 uart3: serial@ff1b0000 {
433 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
434 reg = <0xff1b0000 0x100>;
435 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
439 clock-names = "baudclk", "apb_pclk";
440 pinctrl-names = "default";
441 pinctrl-0 = <&uart3_xfer>;
445 uart4: serial@ff1c0000 {
446 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
447 reg = <0xff1c0000 0x100>;
448 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
452 clock-names = "baudclk", "apb_pclk";
453 pinctrl-names = "default";
454 pinctrl-0 = <&uart4_xfer>;
459 #include "rk3288-thermal.dtsi"
462 tsadc: tsadc@ff280000 {
463 compatible = "rockchip,rk3288-tsadc";
464 reg = <0xff280000 0x100>;
465 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
467 clock-names = "tsadc", "apb_pclk";
468 resets = <&cru SRST_TSADC>;
469 reset-names = "tsadc-apb";
470 pinctrl-names = "init", "default", "sleep";
471 pinctrl-0 = <&otp_gpio>;
472 pinctrl-1 = <&otp_out>;
473 pinctrl-2 = <&otp_gpio>;
474 #thermal-sensor-cells = <1>;
475 rockchip,hw-tshut-temp = <95000>;
479 gmac: ethernet@ff290000 {
480 compatible = "rockchip,rk3288-gmac";
481 reg = <0xff290000 0x10000>;
482 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
483 interrupt-names = "macirq";
484 rockchip,grf = <&grf>;
485 clocks = <&cru SCLK_MAC>,
486 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
487 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
488 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
489 clock-names = "stmmaceth",
490 "mac_clk_rx", "mac_clk_tx",
491 "clk_mac_ref", "clk_mac_refout",
492 "aclk_mac", "pclk_mac";
493 resets = <&cru SRST_MAC>;
494 reset-names = "stmmaceth";
498 usb_host0_ehci: usb@ff500000 {
499 compatible = "generic-ehci";
500 reg = <0xff500000 0x100>;
501 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru HCLK_USBHOST0>;
503 clock-names = "usbhost";
509 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
511 usb_host1: usb@ff540000 {
512 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
514 reg = <0xff540000 0x40000>;
515 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&cru HCLK_USBHOST1>;
520 phy-names = "usb2-phy";
524 usb_otg: usb@ff580000 {
525 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
527 reg = <0xff580000 0x40000>;
528 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&cru HCLK_OTG0>;
532 g-np-tx-fifo-size = <16>;
533 g-rx-fifo-size = <275>;
534 g-tx-fifo-size = <256 128 128 64 64 32>;
537 phy-names = "usb2-phy";
541 usb_hsic: usb@ff5c0000 {
542 compatible = "generic-ehci";
543 reg = <0xff5c0000 0x100>;
544 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&cru HCLK_HSIC>;
546 clock-names = "usbhost";
551 compatible = "rockchip,rk3288-i2c";
552 reg = <0xff650000 0x1000>;
553 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <1>;
557 clocks = <&cru PCLK_I2C0>;
558 pinctrl-names = "default";
559 pinctrl-0 = <&i2c0_xfer>;
564 compatible = "rockchip,rk3288-i2c";
565 reg = <0xff660000 0x1000>;
566 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
567 #address-cells = <1>;
570 clocks = <&cru PCLK_I2C2>;
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c2_xfer>;
577 compatible = "rockchip,rk3288-pwm";
578 reg = <0xff680000 0x10>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&pwm0_pin>;
582 clocks = <&cru PCLK_PWM>;
588 compatible = "rockchip,rk3288-pwm";
589 reg = <0xff680010 0x10>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&pwm1_pin>;
593 clocks = <&cru PCLK_PWM>;
599 compatible = "rockchip,rk3288-pwm";
600 reg = <0xff680020 0x10>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&pwm2_pin>;
604 clocks = <&cru PCLK_PWM>;
610 compatible = "rockchip,rk3288-pwm";
611 reg = <0xff680030 0x10>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&pwm3_pin>;
615 clocks = <&cru PCLK_PWM>;
620 bus_intmem@ff700000 {
621 compatible = "mmio-sram";
622 reg = <0xff700000 0x18000>;
623 #address-cells = <1>;
625 ranges = <0 0xff700000 0x18000>;
627 compatible = "rockchip,rk3066-smp-sram";
633 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
634 reg = <0xff720000 0x1000>;
637 pmu: power-management@ff730000 {
638 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
639 reg = <0xff730000 0x100>;
641 power: power-controller {
642 compatible = "rockchip,rk3288-power-controller";
643 #power-domain-cells = <1>;
644 #address-cells = <1>;
648 * Note: Although SCLK_* are the working clocks
649 * of device without including on the NOC, needed for
652 * The clocks on the which NOC:
653 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
654 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
655 * ACLK_RGA is on ACLK_RGA_NIU.
656 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
658 * Which clock are device clocks:
660 * *_IEP IEP:Image Enhancement Processor
661 * *_ISP ISP:Image Signal Processing
662 * *_VIP VIP:Video Input Processor
663 * *_VOP* VOP:Visual Output Processor
671 reg = <RK3288_PD_VIO>;
672 clocks = <&cru ACLK_IEP>,
686 <&cru PCLK_EDP_CTRL>,
687 <&cru PCLK_HDMI_CTRL>,
688 <&cru PCLK_LVDS_PHY>,
689 <&cru PCLK_MIPI_CSI>,
690 <&cru PCLK_MIPI_DSI0>,
691 <&cru PCLK_MIPI_DSI1>,
700 * Note: The following 3 are HEVC(H.265) clocks,
701 * and on the ACLK_HEVC_NIU (NOC).
704 reg = <RK3288_PD_HEVC>;
705 clocks = <&cru ACLK_HEVC>,
706 <&cru SCLK_HEVC_CABAC>,
707 <&cru SCLK_HEVC_CORE>;
711 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
712 * (video endecoder & decoder) clocks that on the
713 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
716 reg = <RK3288_PD_VIDEO>;
717 clocks = <&cru ACLK_VCODEC>,
722 * Note: ACLK_GPU is the GPU clock,
723 * and on the ACLK_GPU_NIU (NOC).
726 reg = <RK3288_PD_GPU>;
727 clocks = <&cru ACLK_GPU>;
732 sgrf: syscon@ff740000 {
733 compatible = "rockchip,rk3288-sgrf", "syscon";
734 reg = <0xff740000 0x1000>;
737 cru: clock-controller@ff760000 {
738 compatible = "rockchip,rk3288-cru";
739 reg = <0xff760000 0x1000>;
740 rockchip,grf = <&grf>;
743 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
744 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
745 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
746 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
748 assigned-clock-rates = <594000000>, <400000000>,
749 <500000000>, <300000000>,
750 <150000000>, <75000000>,
751 <300000000>, <150000000>,
755 grf: syscon@ff770000 {
756 compatible = "rockchip,rk3288-grf", "syscon";
757 reg = <0xff770000 0x1000>;
760 wdt: watchdog@ff800000 {
761 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
762 reg = <0xff800000 0x100>;
763 clocks = <&cru PCLK_WDT>;
764 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
768 spdif: sound@ff88b0000 {
769 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
770 reg = <0xff8b0000 0x10000>;
771 #sound-dai-cells = <0>;
772 clock-names = "hclk", "mclk";
773 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
774 dmas = <&dmac_bus_s 3>;
776 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
777 pinctrl-names = "default";
778 pinctrl-0 = <&spdif_tx>;
779 rockchip,grf = <&grf>;
784 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
785 reg = <0xff890000 0x10000>;
786 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
787 #address-cells = <1>;
789 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
790 dma-names = "tx", "rx";
791 clock-names = "i2s_hclk", "i2s_clk";
792 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
793 pinctrl-names = "default";
794 pinctrl-0 = <&i2s0_bus>;
799 compatible = "rockchip,rk3288-vop";
800 reg = <0xff930000 0x19c>;
801 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
803 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
804 power-domains = <&power RK3288_PD_VIO>;
805 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
806 reset-names = "axi", "ahb", "dclk";
807 iommus = <&vopb_mmu>;
811 #address-cells = <1>;
814 vopb_out_hdmi: endpoint@0 {
816 remote-endpoint = <&hdmi_in_vopb>;
819 vopb_out_edp: endpoint@1 {
821 remote-endpoint = <&edp_in_vopb>;
824 vopb_out_mipi: endpoint@2 {
826 remote-endpoint = <&mipi_in_vopb>;
831 vopb_mmu: iommu@ff930300 {
832 compatible = "rockchip,iommu";
833 reg = <0xff930300 0x100>;
834 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-names = "vopb_mmu";
836 power-domains = <&power RK3288_PD_VIO>;
842 compatible = "rockchip,rk3288-vop";
843 reg = <0xff940000 0x19c>;
844 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
846 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
847 power-domains = <&power RK3288_PD_VIO>;
848 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
849 reset-names = "axi", "ahb", "dclk";
850 iommus = <&vopl_mmu>;
854 #address-cells = <1>;
857 vopl_out_hdmi: endpoint@0 {
859 remote-endpoint = <&hdmi_in_vopl>;
862 vopl_out_edp: endpoint@1 {
864 remote-endpoint = <&edp_in_vopl>;
867 vopl_out_mipi: endpoint@2 {
869 remote-endpoint = <&mipi_in_vopl>;
874 vopl_mmu: iommu@ff940300 {
875 compatible = "rockchip,iommu";
876 reg = <0xff940300 0x100>;
877 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
878 interrupt-names = "vopl_mmu";
879 power-domains = <&power RK3288_PD_VIO>;
884 mipi_dsi: mipi@ff960000 {
885 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
886 reg = <0xff960000 0x4000>;
887 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
889 clock-names = "ref", "pclk";
890 rockchip,grf = <&grf>;
891 #address-cells = <1>;
896 #address-cells = <1>;
901 #address-cells = <1>;
903 mipi_in_vopb: endpoint@0 {
905 remote-endpoint = <&vopb_out_mipi>;
907 mipi_in_vopl: endpoint@1 {
909 remote-endpoint = <&vopl_out_mipi>;
916 compatible = "rockchip,rk3288-dp";
917 reg = <0xff970000 0x4000>;
918 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
919 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
920 clock-names = "dp", "pclk";
923 resets = <&cru SRST_EDP>;
925 rockchip,grf = <&grf>;
929 #address-cells = <1>;
933 #address-cells = <1>;
935 edp_in_vopb: endpoint@0 {
937 remote-endpoint = <&vopb_out_edp>;
939 edp_in_vopl: endpoint@1 {
941 remote-endpoint = <&vopl_out_edp>;
947 hdmi: hdmi@ff980000 {
948 compatible = "rockchip,rk3288-dw-hdmi";
949 reg = <0xff980000 0x20000>;
951 rockchip,grf = <&grf>;
952 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
954 clock-names = "iahb", "isfr";
955 power-domains = <&power RK3288_PD_VIO>;
960 #address-cells = <1>;
962 hdmi_in_vopb: endpoint@0 {
964 remote-endpoint = <&vopb_out_hdmi>;
966 hdmi_in_vopl: endpoint@1 {
968 remote-endpoint = <&vopl_out_hdmi>;
974 gic: interrupt-controller@ffc01000 {
975 compatible = "arm,gic-400";
976 interrupt-controller;
977 #interrupt-cells = <3>;
978 #address-cells = <0>;
980 reg = <0xffc01000 0x1000>,
984 interrupts = <GIC_PPI 9 0xf04>;
988 compatible = "rockchip,rk3288-usb-phy";
989 rockchip,grf = <&grf>;
990 #address-cells = <1>;
997 clocks = <&cru SCLK_OTGPHY0>;
998 clock-names = "phyclk";
1004 clocks = <&cru SCLK_OTGPHY1>;
1005 clock-names = "phyclk";
1011 clocks = <&cru SCLK_OTGPHY2>;
1012 clock-names = "phyclk";
1017 compatible = "rockchip,rk3288-pinctrl";
1018 rockchip,grf = <&grf>;
1019 rockchip,pmu = <&pmu>;
1020 #address-cells = <1>;
1024 gpio0: gpio0@ff750000 {
1025 compatible = "rockchip,gpio-bank";
1026 reg = <0xff750000 0x100>;
1027 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&cru PCLK_GPIO0>;
1033 interrupt-controller;
1034 #interrupt-cells = <2>;
1037 gpio1: gpio1@ff780000 {
1038 compatible = "rockchip,gpio-bank";
1039 reg = <0xff780000 0x100>;
1040 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&cru PCLK_GPIO1>;
1046 interrupt-controller;
1047 #interrupt-cells = <2>;
1050 gpio2: gpio2@ff790000 {
1051 compatible = "rockchip,gpio-bank";
1052 reg = <0xff790000 0x100>;
1053 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&cru PCLK_GPIO2>;
1059 interrupt-controller;
1060 #interrupt-cells = <2>;
1063 gpio3: gpio3@ff7a0000 {
1064 compatible = "rockchip,gpio-bank";
1065 reg = <0xff7a0000 0x100>;
1066 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&cru PCLK_GPIO3>;
1072 interrupt-controller;
1073 #interrupt-cells = <2>;
1076 gpio4: gpio4@ff7b0000 {
1077 compatible = "rockchip,gpio-bank";
1078 reg = <0xff7b0000 0x100>;
1079 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&cru PCLK_GPIO4>;
1085 interrupt-controller;
1086 #interrupt-cells = <2>;
1089 gpio5: gpio5@ff7c0000 {
1090 compatible = "rockchip,gpio-bank";
1091 reg = <0xff7c0000 0x100>;
1092 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&cru PCLK_GPIO5>;
1098 interrupt-controller;
1099 #interrupt-cells = <2>;
1102 gpio6: gpio6@ff7d0000 {
1103 compatible = "rockchip,gpio-bank";
1104 reg = <0xff7d0000 0x100>;
1105 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&cru PCLK_GPIO6>;
1111 interrupt-controller;
1112 #interrupt-cells = <2>;
1115 gpio7: gpio7@ff7e0000 {
1116 compatible = "rockchip,gpio-bank";
1117 reg = <0xff7e0000 0x100>;
1118 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&cru PCLK_GPIO7>;
1124 interrupt-controller;
1125 #interrupt-cells = <2>;
1128 gpio8: gpio8@ff7f0000 {
1129 compatible = "rockchip,gpio-bank";
1130 reg = <0xff7f0000 0x100>;
1131 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&cru PCLK_GPIO8>;
1137 interrupt-controller;
1138 #interrupt-cells = <2>;
1142 hdmi_ddc: hdmi-ddc {
1143 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1144 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1148 pcfg_pull_up: pcfg-pull-up {
1152 pcfg_pull_down: pcfg-pull-down {
1156 pcfg_pull_none: pcfg-pull-none {
1160 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1162 drive-strength = <12>;
1166 global_pwroff: global-pwroff {
1167 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1170 ddrio_pwroff: ddrio-pwroff {
1171 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1174 ddr0_retention: ddr0-retention {
1175 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1178 ddr1_retention: ddr1-retention {
1179 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1184 i2c0_xfer: i2c0-xfer {
1185 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1186 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1191 i2c1_xfer: i2c1-xfer {
1192 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1193 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1198 i2c2_xfer: i2c2-xfer {
1199 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1200 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1205 i2c3_xfer: i2c3-xfer {
1206 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1207 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1212 i2c4_xfer: i2c4-xfer {
1213 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1214 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1219 i2c5_xfer: i2c5-xfer {
1220 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1221 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1226 i2s0_bus: i2s0-bus {
1227 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1228 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1229 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1230 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1231 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1232 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1237 sdmmc_clk: sdmmc-clk {
1238 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1241 sdmmc_cmd: sdmmc-cmd {
1242 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1245 sdmmc_cd: sdmcc-cd {
1246 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1249 sdmmc_bus1: sdmmc-bus1 {
1250 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1253 sdmmc_bus4: sdmmc-bus4 {
1254 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1255 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1256 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1257 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1262 sdio0_bus1: sdio0-bus1 {
1263 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1266 sdio0_bus4: sdio0-bus4 {
1267 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1268 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1269 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1270 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1273 sdio0_cmd: sdio0-cmd {
1274 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1277 sdio0_clk: sdio0-clk {
1278 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1281 sdio0_cd: sdio0-cd {
1282 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1285 sdio0_wp: sdio0-wp {
1286 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1289 sdio0_pwr: sdio0-pwr {
1290 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1293 sdio0_bkpwr: sdio0-bkpwr {
1294 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1297 sdio0_int: sdio0-int {
1298 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1303 sdio1_bus1: sdio1-bus1 {
1304 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1307 sdio1_bus4: sdio1-bus4 {
1308 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1309 <3 25 4 &pcfg_pull_up>,
1310 <3 26 4 &pcfg_pull_up>,
1311 <3 27 4 &pcfg_pull_up>;
1314 sdio1_cd: sdio1-cd {
1315 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1318 sdio1_wp: sdio1-wp {
1319 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1322 sdio1_bkpwr: sdio1-bkpwr {
1323 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1326 sdio1_int: sdio1-int {
1327 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1330 sdio1_cmd: sdio1-cmd {
1331 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1334 sdio1_clk: sdio1-clk {
1335 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1338 sdio1_pwr: sdio1-pwr {
1339 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1344 emmc_clk: emmc-clk {
1345 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1348 emmc_cmd: emmc-cmd {
1349 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1352 emmc_pwr: emmc-pwr {
1353 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1356 emmc_bus1: emmc-bus1 {
1357 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1360 emmc_bus4: emmc-bus4 {
1361 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1362 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1363 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1364 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1367 emmc_bus8: emmc-bus8 {
1368 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1369 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1370 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1371 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1372 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1373 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1374 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1375 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1380 spi0_clk: spi0-clk {
1381 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1383 spi0_cs0: spi0-cs0 {
1384 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1387 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1390 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1392 spi0_cs1: spi0-cs1 {
1393 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1397 spi1_clk: spi1-clk {
1398 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1400 spi1_cs0: spi1-cs0 {
1401 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1404 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1407 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1412 spi2_cs1: spi2-cs1 {
1413 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1415 spi2_clk: spi2-clk {
1416 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1418 spi2_cs0: spi2-cs0 {
1419 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1422 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1425 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1430 uart0_xfer: uart0-xfer {
1431 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1432 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1435 uart0_cts: uart0-cts {
1436 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1439 uart0_rts: uart0-rts {
1440 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1445 uart1_xfer: uart1-xfer {
1446 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1447 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1450 uart1_cts: uart1-cts {
1451 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1454 uart1_rts: uart1-rts {
1455 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1460 uart2_xfer: uart2-xfer {
1461 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1462 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1464 /* no rts / cts for uart2 */
1468 uart3_xfer: uart3-xfer {
1469 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1470 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1473 uart3_cts: uart3-cts {
1474 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1477 uart3_rts: uart3-rts {
1478 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1483 uart4_xfer: uart4-xfer {
1484 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1485 <5 13 3 &pcfg_pull_none>;
1488 uart4_cts: uart4-cts {
1489 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1492 uart4_rts: uart4-rts {
1493 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1498 otp_gpio: otp-gpio {
1499 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1503 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1508 pwm0_pin: pwm0-pin {
1509 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1514 pwm1_pin: pwm1-pin {
1515 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1520 pwm2_pin: pwm2-pin {
1521 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1526 pwm3_pin: pwm3-pin {
1527 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1532 rgmii_pins: rgmii-pins {
1533 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1534 <3 31 3 &pcfg_pull_none>,
1535 <3 26 3 &pcfg_pull_none>,
1536 <3 27 3 &pcfg_pull_none>,
1537 <3 28 3 &pcfg_pull_none_12ma>,
1538 <3 29 3 &pcfg_pull_none_12ma>,
1539 <3 24 3 &pcfg_pull_none_12ma>,
1540 <3 25 3 &pcfg_pull_none_12ma>,
1541 <4 0 3 &pcfg_pull_none>,
1542 <4 5 3 &pcfg_pull_none>,
1543 <4 6 3 &pcfg_pull_none>,
1544 <4 9 3 &pcfg_pull_none_12ma>,
1545 <4 4 3 &pcfg_pull_none_12ma>,
1546 <4 1 3 &pcfg_pull_none>,
1547 <4 3 3 &pcfg_pull_none>;
1550 rmii_pins: rmii-pins {
1551 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1552 <3 31 3 &pcfg_pull_none>,
1553 <3 28 3 &pcfg_pull_none>,
1554 <3 29 3 &pcfg_pull_none>,
1555 <4 0 3 &pcfg_pull_none>,
1556 <4 5 3 &pcfg_pull_none>,
1557 <4 4 3 &pcfg_pull_none>,
1558 <4 1 3 &pcfg_pull_none>,
1559 <4 2 3 &pcfg_pull_none>,
1560 <4 3 3 &pcfg_pull_none>;
1565 spdif_tx: spdif-tx {
1566 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;