1 #include <dt-bindings/clock/rk_system_status.h>
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include <dt-bindings/rkfb/rk_fb.h>
4 #include <dt-bindings/rkmipi/mipi_dsi.h>
5 #include <dt-bindings/suspend/rockchip-pm.h>
6 #include <dt-bindings/sensor-dev.h>
8 #include "skeleton.dtsi"
9 #include "rk3288-pinctrl.dtsi"
10 #include "rk3288-clocks.dtsi"
13 compatible = "rockchip,rk3288";
14 rockchip,sram = <&sram>;
15 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a15";
47 compatible = "arm,cortex-a15";
52 compatible = "arm,cortex-a15";
57 compatible = "arm,cortex-a15";
62 gic: interrupt-controller@ffc01000 {
63 compatible = "arm,cortex-a15-gic";
65 #interrupt-cells = <3>;
67 reg = <0xffc01000 0x1000>,
72 compatible = "arm,cortex-a12-pmu";
73 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
79 cpu_axi_bus: cpu_axi_bus {
80 compatible = "rockchip,cpu_axi_bus";
91 reg = <0xffa80000 0x20>;
94 reg = <0xffa80080 0x20>;
97 reg = <0xffa80100 0x20>;
101 reg = <0xffa90000 0x20>;
104 reg = <0xffa90080 0x20>;
107 reg = <0xffa90100 0x20>;
110 reg = <0xffa90180 0x20>;
113 reg = <0xffa90200 0x20>;
117 reg = <0xffaa0000 0x20>;
120 reg = <0xffaa0080 0x20>;
124 reg = <0xffab0000 0x20>;
128 reg = <0xffad0000 0x20>;
129 rockchip,priority = <2 2>;
132 reg = <0xffad0100 0x20>;
135 reg = <0xffad0180 0x20>;
138 reg = <0xffad0400 0x20>;
139 rockchip,priority = <2 2>;
142 reg = <0xffad0480 0x20>;
145 reg = <0xffad0500 0x20>;
148 reg = <0xffad0800 0x20>;
151 reg = <0xffad0880 0x20>;
154 reg = <0xffad0900 0x20>;
158 reg = <0xffae0000 0x20>;
162 reg = <0xffaf0000 0x20>;
165 reg = <0xffaf0080 0x20>;
170 #address-cells = <1>;
175 reg = <0xffac0000 0x40>;
176 rockchip,read-latency = <0x34>;
179 reg = <0xffac0080 0x40>;
180 rockchip,read-latency = <0x34>;
185 sram: sram@ff710000 {
186 compatible = "mmio-sram";
187 reg = <0xff710000 0x8000>; /* 32k */
192 compatible = "arm,armv7-timer";
193 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
194 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
195 clock-frequency = <24000000>;
199 compatible = "rockchip,timer";
200 reg = <0xff810000 0x20>;
201 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
202 rockchip,broadcast = <1>;
205 watchdog: wdt@2004c000 {
206 compatible = "rockchip,watch dog";
207 reg = <0xff800000 0x100>;
208 clocks = <&pclk_pd_alive>;
209 clock-names = "pclk_wdt";
210 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
212 rockchip,timeout = <60>;
213 rockchip,atboot = <1>;
214 rockchip,debug = <0>;
219 #address-cells = <1>;
221 compatible = "arm,amba-bus";
222 interrupt-parent = <&gic>;
225 pdma0: pdma@ffb20000 {
226 compatible = "arm,pl330", "arm,primecell";
227 reg = <0xffb20000 0x4000>;
228 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
233 pdma1: pdma@ff250000 {
234 compatible = "arm,pl330", "arm,primecell";
235 reg = <0xff250000 0x4000>;
236 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
242 reset: reset@ff7601b8{
243 compatible = "rockchip,reset";
244 reg = <0xff7601b8 0x30>;
245 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
249 nandc0: nandc@0xff400000 {
250 compatible = "rockchip,rk-nandc";
251 reg = <0xff400000 0x4000>;
252 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
255 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
258 nandc1: nandc@0xff410000 {
259 compatible = "rockchip,rk-nandc";
260 reg = <0xff410000 0x4000>;
261 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
264 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
267 nandc0reg: nandc0@0xff400000 {
268 compatible = "rockchip,rk-nandc";
269 reg = <0xff400000 0x4000>;
272 emmc: rksdmmc@ff0f0000 {
273 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
274 reg = <0xff0f0000 0x4000>;
275 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
276 #address-cells = <1>;
278 //pinctrl-names = "default",,"suspend";
279 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
280 clocks = <&clk_emmc>, <&clk_gates8 6>;
281 clock-names = "clk_mmc", "hclk_mmc";
283 fifo-depth = <0x100>;
287 sdmmc: rksdmmc@ff0c0000 {
288 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
289 reg = <0xff0c0000 0x4000>;
290 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
291 #address-cells = <1>;
293 pinctrl-names = "default", "idle";
294 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
295 pinctrl-1 = <&sdmmc0_gpio>;
296 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
297 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
298 clock-names = "clk_mmc", "hclk_mmc";
300 fifo-depth = <0x100>;
304 sdio: rksdmmc@ff0d0000 {
305 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
306 reg = <0xff0d0000 0x4000>;
307 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
308 #address-cells = <1>;
310 pinctrl-names = "default","idle";
311 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
312 &sdio0_intn &sdio0_bus4>;
313 pinctrl-1 = <&sdio0_gpio>;
314 clocks = <&clk_sdio0>, <&clk_gates8 4>;
315 clock-names = "clk_mmc", "hclk_mmc";
317 fifo-depth = <0x100>;
321 sdio1: rksdmmc@ff0e0000 {
322 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
323 reg = <0xff0e0000 0x4000>;
324 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>;
327 //pinctrl-names = "default","suspend";
328 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
329 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
330 clocks = <&clk_sdio1>, <&clk_gates8 5>;
331 clock-names = "clk_mmc", "hclk_mmc";
333 fifo-depth = <0x100>;
339 compatible = "rockchip,rockchip-spi";
340 reg = <0xff110000 0x1000>;
341 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
346 rockchip,spi-src-clk = <0>;
348 clocks =<&clk_spi0>, <&clk_gates6 4>;
349 clock-names = "spi","pclk_spi0";
350 //dmas = <&pdma1 11>, <&pdma1 12>;
352 //dma-names = "tx", "rx";
357 compatible = "rockchip,rockchip-spi";
358 reg = <0xff120000 0x1000>;
359 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
360 #address-cells = <1>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
364 rockchip,spi-src-clk = <1>;
366 clocks = <&clk_spi1>, <&clk_gates6 5>;
367 clock-names = "spi","pclk_spi1";
368 //dmas = <&pdma1 13>, <&pdma1 14>;
370 //dma-names = "tx", "rx";
375 compatible = "rockchip,rockchip-spi";
376 reg = <0xff130000 0x1000>;
377 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
382 rockchip,spi-src-clk = <2>;
384 clocks = <&clk_spi2>, <&clk_gates6 6>;
385 clock-names = "spi","pclk_spi2";
386 //dmas = <&pdma1 15>, <&pdma1 16>;
388 //dma-names = "tx", "rx";
392 uart_bt: serial@ff180000 {
393 compatible = "rockchip,serial";
394 reg = <0xff180000 0x100>;
395 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
396 clock-frequency = <24000000>;
397 clocks = <&clk_uart0>, <&clk_gates6 8>;
398 clock-names = "sclk_uart", "pclk_uart";
401 dmas = <&pdma1 1>, <&pdma1 2>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
408 uart_bb: serial@ff190000 {
409 compatible = "rockchip,serial";
410 reg = <0xff190000 0x100>;
411 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
412 clock-frequency = <24000000>;
413 clocks = <&clk_uart1>, <&clk_gates6 9>;
414 clock-names = "sclk_uart", "pclk_uart";
417 dmas = <&pdma1 3>, <&pdma1 4>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
424 uart_dbg: serial@ff690000 {
425 compatible = "rockchip,serial";
426 reg = <0xff690000 0x100>;
427 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
428 clock-frequency = <24000000>;
429 clocks = <&clk_uart2>, <&clk_gates11 9>;
430 clock-names = "sclk_uart", "pclk_uart";
433 dmas = <&pdma0 4>, <&pdma0 5>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&uart2_xfer>;
440 uart_gps: serial@ff1b0000 {
441 compatible = "rockchip,serial";
442 reg = <0xff1b0000 0x100>;
443 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
444 clock-frequency = <24000000>;
445 clocks = <&clk_uart3>, <&clk_gates6 11>;
446 clock-names = "sclk_uart", "pclk_uart";
447 current-speed = <115200>;
450 dmas = <&pdma1 7>, <&pdma1 8>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
457 uart_exp: serial@ff1c0000 {
458 compatible = "rockchip,serial";
459 reg = <0xff1c0000 0x100>;
460 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
461 clock-frequency = <24000000>;
462 clocks = <&clk_uart4>, <&clk_gates6 12>;
463 clock-names = "sclk_uart", "pclk_uart";
466 dmas = <&pdma1 9>, <&pdma1 10>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
474 compatible = "rockchip,fiq-debugger";
475 rockchip,serial-id = <2>;
476 rockchip,signal-irq = <106>;
477 rockchip,wake-irq = <0>;
481 rockchip_clocks_init: clocks-init{
482 compatible = "rockchip,clocks-init";
483 rockchip,clocks-init-parent =
484 <&clk_core &clk_apll>, <&aclk_bus_src &clk_gpll>,
485 <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
486 <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
487 <&usbphy_480m &otgphy2_480m>;
488 rockchip,clocks-init-rate =
489 <&clk_core 792000000>, <&clk_gpll 297000000>,
490 /*<&clk_cpll 47000000>,*/ <&clk_npll 1250000000>,
491 <&aclk_bus_src 300000000>, <&aclk_bus 300000000>,
492 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
493 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
494 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
495 <&clk_gpu 200000000>, <&aclk_vio0 300000000>,
496 <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
497 <&pclk_pd_alive 100000000>, <&pclk_pd_pmu 100000000>,
498 <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
499 <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
500 <&aclk_rga 300000000>, <&clk_rga 300000000>,
501 <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
502 <&clk_edp 200000000>, <&clk_isp 200000000>,
503 <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
504 <&clk_tspout 80000000>, <&clk_mac 125000000>;
505 rockchip,clocks-uboot-has-init =
510 compatible = "rockchip,clocks-enable";
513 <&clk_gates0 2>, <&clk_core0>,
514 <&clk_core1>, <&clk_core2>,
515 <&clk_core3>, <&clk_l2ram>,
516 <&aclk_core_m0>, <&aclk_core_mp>,
517 <&atclk_core>, <&pclk_dbg_src>,
518 <&clk_gates12 9>, <&clk_gates12 10>,
522 <&aclk_bus>, <&clk_gates0 3>,
523 <&hclk_bus>, <&pclk_bus>,
524 <&clk_gates13 8>, <&clk_crypto>,
528 <&clk_gates1 0>, <&clk_gates1 1>,
529 <&clk_gates1 2>, <&clk_gates1 3>,
530 <&clk_gates1 4>, <&clk_gates1 5>,
532 <&pclk_pd_alive>, <&pclk_pd_pmu>,
535 <&aclk_peri>, <&hclk_peri>,
539 /*<&clk_gates4 14>,*/
542 <&clk_gates10 5>,/*aclk_intmem0*/
543 <&clk_gates10 6>,/*aclk_intmem1*/
544 <&clk_gates10 7>,/*aclk_intmem2*/
545 <&clk_gates10 12>,/*aclk_dma1*/
546 <&clk_gates10 13>,/*aclk_strc_sys*/
547 <&clk_gates10 4>,/*aclk_intmem*/
548 <&clk_gates11 6>,/*aclk_crypto*/
549 <&clk_gates11 8>,/*aclk_ccp*/
552 <&clk_gates11 7>,/*hclk_crypto*/
553 <&clk_gates10 9>,/*hclk_rom*/
556 <&clk_gates10 1>,/*pclk_timer*/
557 <&clk_gates10 9>,/*rom*/
558 <&clk_gates10 13>,/*aclk strc*/
560 <&clk_gates12 8>,/*aclk strc*/
563 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
564 <&clk_gates6 3>,/*aclk_dmac2*/
565 <&clk_gates7 11>,/*aclk_peri_niu*/
566 <&clk_gates8 12>,/*aclk_peri_mmu*/
569 <&clk_gates6 0>,/*hclk_peri_matrix*/
570 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
571 <&clk_gates7 12>,/*hclk_emem_peri*/
572 <&clk_gates7 13>,/*hclk_mem_peri*/
575 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
578 <&clk_gates14 11>,/*pclk_grf*/
579 <&clk_gates14 12>,/*pclk_alive_niu*/
582 <&clk_gates17 0>,/*pclk_pmu*/
583 <&clk_gates17 1>,/*pclk_intmem1*/
584 <&clk_gates17 2>,/*pclk_pmu_niu*/
585 <&clk_gates17 3>,/*pclk_sgrf*/
588 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
589 <&clk_gates15 10>,/*hclk_vio_niu*/
590 <&clk_gates16 10>,/*hclk_vio2_h2p*/
591 <&clk_gates16 11>,/*pclk_vio2_h2p*/
594 <&clk_gates15 11>,/*aclk_vio0_niu*/
597 <&clk_gates15 12>,/*aclk_vio1_niu*/
600 //<&clk_gates5 12>,/*hdmi_hdcp_clk*/
603 <&clk_gates11 9>,/*pclk_uart2*/
610 compatible = "rockchip,rk30-i2c";
611 reg = <0xff650000 0x1000>;
612 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
613 #address-cells = <1>;
615 pinctrl-names = "default", "gpio";
616 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
617 pinctrl-1 = <&i2c0_gpio>;
618 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
619 clocks = <&clk_gates10 2>;
620 rockchip,check-idle = <1>;
625 compatible = "rockchip,rk30-i2c";
626 reg = <0xff140000 0x1000>;
627 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
628 #address-cells = <1>;
630 pinctrl-names = "default", "gpio";
631 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
632 pinctrl-1 = <&i2c1_gpio>;
633 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
634 clocks = <&clk_gates10 3>;
635 rockchip,check-idle = <1>;
640 compatible = "rockchip,rk30-i2c";
641 reg = <0xff660000 0x1000>;
642 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
643 #address-cells = <1>;
645 pinctrl-names = "default", "gpio";
646 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
647 pinctrl-1 = <&i2c2_gpio>;
648 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
649 clocks = <&clk_gates6 13>;
650 rockchip,check-idle = <1>;
655 compatible = "rockchip,rk30-i2c";
656 reg = <0xff150000 0x1000>;
657 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
658 #address-cells = <1>;
660 pinctrl-names = "default", "gpio";
661 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
662 pinctrl-1 = <&i2c3_gpio>;
663 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
664 clocks = <&clk_gates6 14>;
665 rockchip,check-idle = <1>;
670 compatible = "rockchip,rk30-i2c";
671 reg = <0xff160000 0x1000>;
672 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
673 #address-cells = <1>;
675 pinctrl-names = "default", "gpio";
676 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
677 pinctrl-1 = <&i2c4_gpio>;
678 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
679 clocks = <&clk_gates6 15>;
680 rockchip,check-idle = <1>;
685 compatible = "rockchip,rk30-i2c";
686 reg = <0xff170000 0x1000>;
687 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
688 #address-cells = <1>;
690 pinctrl-names = "default", "gpio";
691 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
692 pinctrl-1 = <&i2c5_gpio>;
693 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
694 clocks = <&clk_gates7 0>;
695 rockchip,check-idle = <1>;
700 compatible = "rockchip,rk-fb";
701 rockchip,disp-mode = <DUAL>;
704 rk_screen: rk_screen{
705 compatible = "rockchip,screen";
708 dsihost0: mipi@ff960000{
709 compatible = "rockchip,rk32-dsi";
711 reg = <0xff960000 0x4000>;
712 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
714 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
718 dsihost1: mipi@ff964000{
719 compatible = "rockchip,rk32-dsi";
721 reg = <0xff964000 0x4000>;
722 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
724 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
728 lvds: lvds@ff96c000 {
729 compatible = "rockchip,rk32-lvds";
730 reg = <0xff96c000 0x4000>;
731 clocks = <&clk_gates16 7>;
732 clock-names = "pclk_lvds";
736 compatible = "rockchip,rk32-edp";
737 reg = <0xff970000 0x4000>;
738 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
740 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
743 hdmi: hdmi@ff980000 {
744 compatible = "rockchip,rk3288-hdmi";
745 reg = <0xff980000 0x20000>;
746 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
747 pinctrl-names = "default", "sleep";
748 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
749 pinctrl-1 = <&i2c5_gpio>;
750 clocks = <&clk_gates16 9>, <&clk_gates5 12>;
751 clock-names = "pclk_hdmi", "hdcp_clk_hdmi";
755 lcdc0: lcdc@ff930000 {
756 compatible = "rockchip,rk3288-lcdc";
757 rockchip,prop = <PRMRY>;
758 rockchip,pwr18 = <0>;
759 rockchip,iommu-enabled = <1>;
760 reg = <0xff930000 0x10000>;
761 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
762 pinctrl-names = "default", "gpio";
763 pinctrl-0 = <&lcdc0_lcdc>;
764 pinctrl-1 = <&lcdc0_gpio>;
766 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
767 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
770 lcdc1: lcdc@ff940000 {
771 compatible = "rockchip,rk3288-lcdc";
772 rockchip,prop = <EXTEND>;
773 rochchip,pwr18 = <0>;
774 rockchip,iommu-enabled = <1>;
775 reg = <0xff940000 0x10000>;
776 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
779 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
783 compatible = "rockchip,saradc";
784 reg = <0xff100000 0x100>;
785 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
786 #io-channel-cells = <1>;
788 rockchip,adc-vref = <1800>;
789 clock-frequency = <1000000>;
790 clocks = <&clk_saradc>, <&clk_gates7 1>;
791 clock-names = "saradc", "pclk_saradc";
796 compatible = "rockchip,rga";
797 reg = <0xff920000 0x1000>;
798 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
800 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
803 i2s: rockchip-i2s@0xff890000 {
804 compatible = "rockchip-i2s";
805 reg = <0xff890000 0x10000>;
807 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
808 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
809 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
810 dmas = <&pdma0 0>, <&pdma0 1>;
812 dma-names = "tx", "rx";
813 pinctrl-names = "default", "sleep";
814 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
815 pinctrl-1 = <&i2s_gpio>;
818 spdif: rockchip-spdif@0xff8b0000 {
819 compatible = "rockchip-spdif";
820 reg = <0xff8b0000 0x10000>; //8channel
821 //reg = <ff880000 0x10000>;//2channel
822 clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
823 clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
824 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
826 //dmas = <&pdma0 2>; //2channel
829 pinctrl-names = "default";
830 pinctrl-0 = <&spdif_tx>;
833 vop1pwm: pwm@ff9401a0 {
834 compatible = "rockchip,vop-pwm";
835 reg = <0xff9401a0 0x10>;
837 pinctrl-names = "default";
838 pinctrl-0 = <&vop1_pwm_pin>;
839 clocks = <&clk_gates13 11>;
840 clock-names = "pclk_pwm";
844 vop0pwm: pwm@ff9301a0 {
845 compatible = "rockchip,vop-pwm";
846 reg = <0xff9301a0 0x10>;
848 pinctrl-names = "default";
849 pinctrl-0 = <&vop0_pwm_pin>;
850 clocks = <&clk_gates13 10>;
851 clock-names = "pclk_pwm";
856 compatible = "rockchip,rk-pwm";
857 reg = <0xff680000 0x10>;
859 pinctrl-names = "default";
860 pinctrl-0 = <&pwm0_pin>;
861 clocks = <&clk_gates11 11>;
862 clock-names = "pclk_pwm";
867 compatible = "rockchip,rk-pwm";
868 reg = <0xff680010 0x10>;
870 pinctrl-names = "default";
871 pinctrl-0 = <&pwm1_pin>;
872 clocks = <&clk_gates11 11>;
873 clock-names = "pclk_pwm";
878 compatible = "rockchip,rk-pwm";
879 reg = <0xff680020 0x10>;
881 pinctrl-names = "default";
882 pinctrl-0 = <&pwm2_pin>;
883 clocks = <&clk_gates11 11>;
884 clock-names = "pclk_pwm";
889 compatible = "rockchip,rk-pwm";
890 reg = <0xff680030 0x10>;
892 pinctrl-names = "default";
893 pinctrl-0 = <&pwm3_pin>;
894 clocks = <&clk_gates11 11>;
895 clock-names = "pclk_pwm";
900 temp-limit-enable = <1>;
904 regulator_name = "vdd_arm";
905 suspend_volt = <1000>; //mV
907 clk_core_dvfs_table: clk_core {
916 normal-temp-limit = <
917 /*delta-temp delta-freq*/
923 performance-temp-limit = <
939 regulator_name = "vdd_logic";
940 suspend_volt = <1000>; //mV
942 clk_ddr_dvfs_table: clk_ddr {
954 aclk_vio1_dvfs_table: aclk_vio1 {
966 regulator_name = "vdd_gpu";
967 suspend_volt = <1000>; //mV
969 clk_gpu_dvfs_table: clk_gpu {
989 compatible = "rockchip,ion";
990 #address-cells = <1>;
993 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
994 compatible = "rockchip,ion-reserve";
995 rockchip,ion_heap = <1>;
996 reg = <0x00000000 0x20000000>; /* 512MB */
998 rockchip,ion-heap@3 { /* VMALLOC HEAP */
999 rockchip,ion_heap = <3>;
1003 vpu: vpu_service@ff9a0000 {
1004 compatible = "vpu_service";
1005 reg = <0xff9a0000 0x800>;
1006 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1007 interrupt-names = "irq_enc", "irq_dec";
1008 clocks = <&clk_vdpu>, <&hclk_vdpu>;
1009 clock-names = "aclk_vcodec", "hclk_vcodec";
1010 name = "vpu_service";
1011 //status = "disabled";
1014 hevc: hevc_service@ff9c0000 {
1015 compatible = "rockchip,hevc_service";
1016 reg = <0xff9c0000 0x800>;
1017 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1018 interrupt-names = "irq_dec";
1019 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1020 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1021 name = "hevc_service";
1022 //status = "disabled";
1026 compatible = "rockchip,iep";
1027 reg = <0xff900000 0x800>;
1028 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1030 clock-names = "aclk_iep", "hclk_iep";
1034 dwc_control_usb: dwc-control-usb@ff770284 {
1035 compatible = "rockchip,rk3288-dwc-control-usb";
1036 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1037 <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1038 <0xff770320 0x14>, <0xff770334 0x14>,
1039 <0xff770348 0x10>, <0xff770358 0x08>,
1041 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1042 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1043 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1044 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1046 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1048 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1049 interrupt-names = "otg_id", "otg_bvalid",
1050 "otg_linestate", "host0_linestate",
1052 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1053 <&otgphy1_480m>, <&otgphy2_480m>;
1054 clock-names = "hclk_usb_peri", "usbphy_480m",
1055 "usbphy1_480m", "usbphy2_480m";
1058 compatible = "synopsys,phy";
1059 /* offset bit mask */
1060 rk_usb,bvalid = <0x288 14 1>;
1061 rk_usb,iddig = <0x288 17 1>;
1062 rk_usb,dcdenb = <0x328 14 1>;
1063 rk_usb,vdatsrcenb = <0x328 7 1>;
1064 rk_usb,vdatdetenb = <0x328 6 1>;
1065 rk_usb,chrgsel = <0x328 5 1>;
1066 rk_usb,chgdet = <0x2cc 23 1>;
1067 rk_usb,fsvminus = <0x2cc 25 1>;
1068 rk_usb,fsvplus = <0x2cc 24 1>;
1072 usb0: usb@ff580000 {
1073 compatible = "rockchip,rk3288_usb20_otg";
1074 reg = <0xff580000 0x40000>;
1075 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1077 clock-names = "clk_usbphy0", "hclk_usb0";
1078 resets = <&reset RK3288_SOFT_RST_USBOTG_H>, <&reset RK3288_SOFT_RST_USBOTGPHY>,
1079 <&reset RK3288_SOFT_RST_USBOTGC>;
1080 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1081 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1082 rockchip,usb-mode = <0>;
1085 usb1: usb@ff540000 {
1086 compatible = "rockchip,rk3288_usb20_host";
1087 reg = <0xff540000 0x40000>;
1088 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1089 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1091 clock-names = "clk_usbphy1", "hclk_usb1",
1093 resets = <&reset RK3288_SOFT_RST_USBHOST1_H>, <&reset RK3288_SOFT_RST_USBHOST1PHY>,
1094 <&reset RK3288_SOFT_RST_USBHOST1C>;
1095 reset-names = "host1_ahb", "host1_phy", "host1_controller";
1098 usb2: usb@ff500000 {
1099 compatible = "rockchip,rk3288_rk_ehci_host";
1100 reg = <0xff500000 0x20000>;
1101 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1102 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1103 clock-names = "clk_usbphy2", "hclk_usb2";
1104 resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1105 <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1106 reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1109 usb3: usb@ff520000 {
1110 compatible = "rockchip,rk3288_rk_ohci_host";
1111 reg = <0xff520000 0x20000>;
1112 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1113 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1114 clock-names = "clk_usbphy3", "hclk_usb3";
1117 hsic: hsic@ff5c0000 {
1118 compatible = "rockchip,rk3288_rk_hsic_host";
1119 reg = <0xff5c0000 0x40000>;
1120 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1122 <&hsicphy_12m>, <&usbphy_480m>,
1123 <&otgphy1_480m>, <&otgphy2_480m>;
1124 clock-names = "hsicphy_480m", "hclk_hsic",
1125 "hsicphy_12m", "usbphy_480m",
1126 "hsic_usbphy1", "hsic_usbphy2";
1127 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1128 <&reset RK3288_SOFT_RST_HSICPHY>;
1129 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1132 gmac: eth@ff290000 {
1133 compatible = "rockchip,gmac";
1134 reg = <0xff290000 0x10000>;
1135 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1136 interrupt-names = "macirq";
1137 clocks = <&clk_mac>, <&clk_gates5 0>,
1138 <&clk_gates5 1>, <&clk_gates5 2>,
1139 <&clk_gates5 3>, <&clk_gates8 0>,
1141 clock-names = "clk_mac", "mac_clk_rx",
1142 "mac_clk_tx", "clk_mac_ref",
1143 "clk_mac_refout", "aclk_mac",
1145 //phy-mode = "rmii";
1147 pinctrl-names = "default";
1148 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1152 compatible = "arm,malit764",
1156 reg = <0xffa30000 0x10000>;
1157 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1160 interrupt-names = "JOB", "MMU", "GPU";
1165 compatible = "iommu,iep_mmu";
1166 reg = <0xff900800 0x100>;
1167 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1168 interrupt-names = "iep_mmu";
1173 compatible = "iommu,vip_mmu";
1174 reg = <0xff950800 0x100>;
1175 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1176 interrupt-names = "vip_mmu";
1181 compatible = "iommu,vopb_mmu";
1182 reg = <0xff930300 0x100>;
1183 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1184 interrupt-names = "vopb_mmu";
1189 compatible = "iommu,vopl_mmu";
1190 reg = <0xff940300 0x100>;
1191 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1192 interrupt-names = "vopl_mmu";
1197 compatible = "iommu,hevc_mmu";
1198 reg = <0xff9c0440 0x100>,
1200 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1201 interrupt-names = "hevc_mmu";
1206 compatible = "iommu,vpu_mmu";
1207 reg = <0xff9a0800 0x100>;
1208 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1209 interrupt-names = "vpu_mmu";
1213 dbgname = "isp_mmu";
1214 compatible = "iommu,isp_mmu";
1215 reg = <0xff914000 0x100>,
1217 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1218 interrupt-names = "isp_mmu";
1222 rockchip,ctrbits = <
1228 // |RKPM_CTR_SYSCLK_DIV
1229 // |RKPM_CTR_IDLEAUTO_MD
1230 // |RKPM_CTR_ARMOFF_LPMD
1231 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1234 rockchip,pmic-suspend_gpios = <
1235 RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
1237 rockchip,pmic-resume_gpios = <
1238 RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
1244 compatible = "rockchip,isp";
1245 reg = <0xff910000 0x10000>;
1246 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1247 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
1248 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
1249 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1250 pinctrl-0 = <&isp_mipi>;
1251 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1252 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1253 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1254 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1255 pinctrl-5 = <&isp_mipi>;
1256 pinctrl-6 = <&isp_mipi &isp_prelight>;
1257 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1258 pinctrl-8 = <&isp_flash_trigger>;
1259 rockchip,isp,mipiphy = <2>;
1260 rockchip,isp,cifphy = <1>;
1261 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1262 rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
1266 tsadc: tsadc@ff280000 {
1267 compatible = "rockchip,tsadc";
1268 reg = <0xff280000 0x100>;
1269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1270 #io-channel-cells = <1>;
1272 clock-frequency = <10000>;
1273 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1274 clock-names = "tsadc", "pclk_tsadc";
1275 pinctrl-names = "default", "tsadc_int";
1276 pinctrl-0 = <&tsadc_gpio>;
1277 pinctrl-1 = <&tsadc_int>;
1278 tsadc-ht-temp = <120>;
1279 tsadc-ht-reset-cru = <1>;
1280 tsadc-ht-pull-gpio = <0>;
1284 lcdc_vdd_domain: lcdc-vdd-domain {
1285 compatible = "rockchip,io_vol_domain";
1286 pinctrl-names = "default", "1.8V", "3.3V";
1287 pinctrl-0 = <&lcdc_vcc>;
1288 pinctrl-1 = <&lcdc_vcc_18>;
1289 pinctrl-2 = <&lcdc_vcc_33>;
1292 dpio_vdd_domain: dpio-vdd-domain {
1293 compatible = "rockchip,io_vol_domain";
1294 pinctrl-names = "default", "1.8V", "3.3V";
1295 pinctrl-0 = <&dvp_vcc>;
1296 pinctrl-1 = <&dvp_vcc_18>;
1297 pinctrl-2 = <&dvp_vcc_33>;
1300 flash0_vdd_domain: flash0-vdd-domain {
1301 compatible = "rockchip,io_vol_domain";
1302 pinctrl-names = "default", "1.8V", "3.3V";
1303 pinctrl-0 = <&flash0_vcc>;
1304 pinctrl-1 = <&flash0_vcc_18>;
1305 pinctrl-2 = <&flash0_vcc_33>;
1308 flash1_vdd_domain: flash1-vdd-domain {
1309 compatible = "rockchip,io_vol_domain";
1310 pinctrl-names = "default", "1.8V", "3.3V";
1311 pinctrl-0 = <&flash1_vcc>;
1312 pinctrl-1 = <&flash1_vcc_18>;
1313 pinctrl-2 = <&flash1_vcc_33>;
1316 apio3_vdd_domain: apio3-vdd-domain {
1317 compatible = "rockchip,io_vol_domain";
1318 pinctrl-names = "default", "1.8V", "3.3V";
1319 pinctrl-0 = <&wifi_vcc>;
1320 pinctrl-1 = <&wifi_vcc_18>;
1321 pinctrl-2 = <&wifi_vcc_33>;
1324 apio5_vdd_domain: apio5-vdd-domain {
1325 compatible = "rockchip,io_vol_domain";
1326 pinctrl-names = "default", "1.8V", "3.3V";
1327 pinctrl-0 = <&bb_vcc>;
1328 pinctrl-1 = <&bb_vcc_18>;
1329 pinctrl-2 = <&bb_vcc_33>;
1332 apio4_vdd_domain: apio4-vdd-domain {
1333 compatible = "rockchip,io_vol_domain";
1334 pinctrl-names = "default", "1.8V", "3.3V";
1335 pinctrl-0 = <&audio_vcc>;
1336 pinctrl-1 = <&audio_vcc_18>;
1337 pinctrl-2 = <&audio_vcc_33>;
1340 apio1_vdd_domain: apio0-vdd-domain {
1341 compatible = "rockchip,io_vol_domain";
1342 pinctrl-names = "default", "1.8V", "3.3V";
1343 pinctrl-0 = <&gpio30_vcc>;
1344 pinctrl-1 = <&gpio30_vcc_18>;
1345 pinctrl-2 = <&gpio30_vcc_33>;
1348 apio2_vdd_domain: apio2-vdd-domain {
1349 compatible = "rockchip,io_vol_domain";
1350 pinctrl-names = "default", "1.8V", "3.3V";
1351 pinctrl-0 = <&gpio1830_vcc>;
1352 pinctrl-1 = <&gpio1830_vcc_18>;
1353 pinctrl-2 = <&gpio1830_vcc_33>;
1356 sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1357 compatible = "rockchip,io_vol_domain";
1358 pinctrl-names = "default", "1.8V", "3.3V";
1359 pinctrl-0 = <&sdcard_vcc>;
1360 pinctrl-1 = <&sdcard_vcc_18>;
1361 pinctrl-2 = <&sdcard_vcc_33>;