2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip_boot-mode.h>
49 #include "skeleton.dtsi"
52 compatible = "rockchip,rk3288";
54 interrupt-parent = <&gic>;
78 compatible = "arm,cortex-a12-pmu";
79 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
89 enable-method = "rockchip,rk3066-smp";
90 rockchip,pmu = <&pmu>;
94 compatible = "arm,cortex-a12";
96 resets = <&cru SRST_CORE0>;
112 #cooling-cells = <2>; /* min followed by max */
113 clock-latency = <40000>;
114 clocks = <&cru ARMCLK>;
118 compatible = "arm,cortex-a12";
120 resets = <&cru SRST_CORE1>;
124 compatible = "arm,cortex-a12";
126 resets = <&cru SRST_CORE2>;
130 compatible = "arm,cortex-a12";
132 resets = <&cru SRST_CORE3>;
137 compatible = "arm,amba-bus";
138 #address-cells = <1>;
142 dmac_peri: dma-controller@ff250000 {
143 compatible = "arm,pl330", "arm,primecell";
144 reg = <0xff250000 0x4000>;
145 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
148 arm,pl330-broken-no-flushp;
149 peripherals-req-type-burst;
150 clocks = <&cru ACLK_DMAC2>;
151 clock-names = "apb_pclk";
154 dmac_bus_ns: dma-controller@ff600000 {
155 compatible = "arm,pl330", "arm,primecell";
156 reg = <0xff600000 0x4000>;
157 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
160 arm,pl330-broken-no-flushp;
161 peripherals-req-type-burst;
162 clocks = <&cru ACLK_DMAC1>;
163 clock-names = "apb_pclk";
167 dmac_bus_s: dma-controller@ffb20000 {
168 compatible = "arm,pl330", "arm,primecell";
169 reg = <0xffb20000 0x4000>;
170 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
173 arm,pl330-broken-no-flushp;
174 peripherals-req-type-burst;
175 clocks = <&cru ACLK_DMAC1>;
176 clock-names = "apb_pclk";
181 #address-cells = <1>;
186 * The rk3288 cannot use the memory area above 0xfe000000
187 * for dma operations for some reason. While there is
188 * probably a better solution available somewhere, we
189 * haven't found it yet and while devices with 2GB of ram
190 * are not affected, this issue prevents 4GB from booting.
191 * So to make these devices at least bootable, block
192 * this area for the time being until the real solution
195 dma-unusable@fe000000 {
196 reg = <0xfe000000 0x1000000>;
201 compatible = "fixed-clock";
202 clock-frequency = <24000000>;
203 clock-output-names = "xin24m";
208 compatible = "arm,armv7-timer";
209 arm,cpu-registers-not-fw-configured;
210 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
211 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
214 clock-frequency = <24000000>;
217 timer: timer@ff810000 {
218 compatible = "rockchip,rk3288-timer";
219 reg = <0xff810000 0x20>;
220 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&xin24m>, <&cru PCLK_TIMER>;
222 clock-names = "timer", "pclk";
226 compatible = "rockchip,display-subsystem";
227 ports = <&vopl_out>, <&vopb_out>;
230 sdmmc: dwmmc@ff0c0000 {
231 compatible = "rockchip,rk3288-dw-mshc";
232 clock-freq-min-max = <400000 150000000>;
233 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
234 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
235 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
236 fifo-depth = <0x100>;
237 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
238 reg = <0xff0c0000 0x4000>;
242 sdio0: dwmmc@ff0d0000 {
243 compatible = "rockchip,rk3288-dw-mshc";
244 clock-freq-min-max = <400000 150000000>;
245 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
246 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
250 reg = <0xff0d0000 0x4000>;
254 sdio1: dwmmc@ff0e0000 {
255 compatible = "rockchip,rk3288-dw-mshc";
256 clock-freq-min-max = <400000 150000000>;
257 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
258 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
259 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
260 fifo-depth = <0x100>;
261 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
262 reg = <0xff0e0000 0x4000>;
266 emmc: dwmmc@ff0f0000 {
267 compatible = "rockchip,rk3288-dw-mshc";
268 clock-freq-min-max = <400000 150000000>;
269 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
270 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
271 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
272 fifo-depth = <0x100>;
273 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
274 reg = <0xff0f0000 0x4000>;
279 saradc: saradc@ff100000 {
280 compatible = "rockchip,saradc";
281 reg = <0xff100000 0x100>;
282 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
283 #io-channel-cells = <1>;
284 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
285 clock-names = "saradc", "apb_pclk";
286 resets = <&cru SRST_SARADC>;
287 reset-names = "saradc-apb";
292 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
293 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
294 clock-names = "spiclk", "apb_pclk";
295 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
296 dma-names = "tx", "rx";
297 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
300 reg = <0xff110000 0x1000>;
301 #address-cells = <1>;
307 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
308 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
309 clock-names = "spiclk", "apb_pclk";
310 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
311 dma-names = "tx", "rx";
312 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
315 reg = <0xff120000 0x1000>;
316 #address-cells = <1>;
322 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
323 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
324 clock-names = "spiclk", "apb_pclk";
325 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
326 dma-names = "tx", "rx";
327 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
330 reg = <0xff130000 0x1000>;
331 #address-cells = <1>;
337 compatible = "rockchip,rk3288-i2c";
338 reg = <0xff140000 0x1000>;
339 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
340 #address-cells = <1>;
343 clocks = <&cru PCLK_I2C1>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&i2c1_xfer>;
350 compatible = "rockchip,rk3288-i2c";
351 reg = <0xff150000 0x1000>;
352 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
356 clocks = <&cru PCLK_I2C3>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&i2c3_xfer>;
363 compatible = "rockchip,rk3288-i2c";
364 reg = <0xff160000 0x1000>;
365 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
366 #address-cells = <1>;
369 clocks = <&cru PCLK_I2C4>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&i2c4_xfer>;
376 compatible = "rockchip,rk3288-i2c";
377 reg = <0xff170000 0x1000>;
378 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
379 #address-cells = <1>;
382 clocks = <&cru PCLK_I2C5>;
383 pinctrl-names = "default";
384 pinctrl-0 = <&i2c5_xfer>;
388 uart0: serial@ff180000 {
389 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
390 reg = <0xff180000 0x100>;
391 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
395 clock-names = "baudclk", "apb_pclk";
396 pinctrl-names = "default";
397 pinctrl-0 = <&uart0_xfer>;
401 uart1: serial@ff190000 {
402 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
403 reg = <0xff190000 0x100>;
404 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
408 clock-names = "baudclk", "apb_pclk";
409 pinctrl-names = "default";
410 pinctrl-0 = <&uart1_xfer>;
414 uart2: serial@ff690000 {
415 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
416 reg = <0xff690000 0x100>;
417 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
421 clock-names = "baudclk", "apb_pclk";
422 pinctrl-names = "default";
423 pinctrl-0 = <&uart2_xfer>;
427 uart3: serial@ff1b0000 {
428 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
429 reg = <0xff1b0000 0x100>;
430 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
434 clock-names = "baudclk", "apb_pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&uart3_xfer>;
440 uart4: serial@ff1c0000 {
441 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
442 reg = <0xff1c0000 0x100>;
443 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
447 clock-names = "baudclk", "apb_pclk";
448 pinctrl-names = "default";
449 pinctrl-0 = <&uart4_xfer>;
454 reserve_thermal: reserve_thermal {
455 polling-delay-passive = <1000>; /* milliseconds */
456 polling-delay = <5000>; /* milliseconds */
458 thermal-sensors = <&tsadc 0>;
461 cpu_thermal: cpu_thermal {
462 polling-delay-passive = <100>; /* milliseconds */
463 polling-delay = <5000>; /* milliseconds */
465 thermal-sensors = <&tsadc 1>;
468 cpu_alert0: cpu_alert0 {
469 temperature = <70000>; /* millicelsius */
470 hysteresis = <2000>; /* millicelsius */
473 cpu_alert1: cpu_alert1 {
474 temperature = <75000>; /* millicelsius */
475 hysteresis = <2000>; /* millicelsius */
479 temperature = <90000>; /* millicelsius */
480 hysteresis = <2000>; /* millicelsius */
487 trip = <&cpu_alert0>;
489 <&cpu0 THERMAL_NO_LIMIT 6>;
492 trip = <&cpu_alert1>;
494 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
499 gpu_thermal: gpu_thermal {
500 polling-delay-passive = <100>; /* milliseconds */
501 polling-delay = <5000>; /* milliseconds */
503 thermal-sensors = <&tsadc 2>;
506 gpu_alert0: gpu_alert0 {
507 temperature = <70000>; /* millicelsius */
508 hysteresis = <2000>; /* millicelsius */
512 temperature = <90000>; /* millicelsius */
513 hysteresis = <2000>; /* millicelsius */
520 trip = <&gpu_alert0>;
522 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
528 tsadc: tsadc@ff280000 {
529 compatible = "rockchip,rk3288-tsadc";
530 reg = <0xff280000 0x100>;
531 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
533 clock-names = "tsadc", "apb_pclk";
534 resets = <&cru SRST_TSADC>;
535 reset-names = "tsadc-apb";
536 pinctrl-names = "init", "default", "sleep";
537 pinctrl-0 = <&otp_gpio>;
538 pinctrl-1 = <&otp_out>;
539 pinctrl-2 = <&otp_gpio>;
540 #thermal-sensor-cells = <1>;
541 rockchip,hw-tshut-temp = <95000>;
545 gmac: ethernet@ff290000 {
546 compatible = "rockchip,rk3288-gmac";
547 reg = <0xff290000 0x10000>;
548 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
550 interrupt-names = "macirq", "eth_wake_irq";
551 rockchip,grf = <&grf>;
552 clocks = <&cru SCLK_MAC>,
553 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
554 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
555 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
556 clock-names = "stmmaceth",
557 "mac_clk_rx", "mac_clk_tx",
558 "clk_mac_ref", "clk_mac_refout",
559 "aclk_mac", "pclk_mac";
560 resets = <&cru SRST_MAC>;
561 reset-names = "stmmaceth";
566 usb_host0_ehci: usb@ff500000 {
567 compatible = "generic-ehci";
568 reg = <0xff500000 0x100>;
569 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&cru HCLK_USBHOST0>;
571 clock-names = "usbhost";
577 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
579 usb_host1: usb@ff540000 {
580 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
582 reg = <0xff540000 0x40000>;
583 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cru HCLK_USBHOST1>;
588 phy-names = "usb2-phy";
592 usb_otg: usb@ff580000 {
593 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
595 reg = <0xff580000 0x40000>;
596 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&cru HCLK_OTG0>;
600 g-np-tx-fifo-size = <16>;
601 g-rx-fifo-size = <275>;
602 g-tx-fifo-size = <256 128 128 64 64 32>;
605 phy-names = "usb2-phy";
609 usb_hsic: usb@ff5c0000 {
610 compatible = "generic-ehci";
611 reg = <0xff5c0000 0x100>;
612 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&cru HCLK_HSIC>;
614 clock-names = "usbhost";
619 compatible = "rockchip,rk3288-i2c";
620 reg = <0xff650000 0x1000>;
621 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
622 #address-cells = <1>;
625 clocks = <&cru PCLK_I2C0>;
626 pinctrl-names = "default";
627 pinctrl-0 = <&i2c0_xfer>;
632 compatible = "rockchip,rk3288-i2c";
633 reg = <0xff660000 0x1000>;
634 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
635 #address-cells = <1>;
638 clocks = <&cru PCLK_I2C2>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&i2c2_xfer>;
645 compatible = "rockchip,rk3288-pwm";
646 reg = <0xff680000 0x10>;
648 pinctrl-names = "default";
649 pinctrl-0 = <&pwm0_pin>;
650 clocks = <&cru PCLK_PWM>;
656 compatible = "rockchip,rk3288-pwm";
657 reg = <0xff680010 0x10>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&pwm1_pin>;
661 clocks = <&cru PCLK_PWM>;
667 compatible = "rockchip,rk3288-pwm";
668 reg = <0xff680020 0x10>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&pwm2_pin>;
672 clocks = <&cru PCLK_PWM>;
678 compatible = "rockchip,rk3288-pwm";
679 reg = <0xff680030 0x10>;
681 pinctrl-names = "default";
682 pinctrl-0 = <&pwm3_pin>;
683 clocks = <&cru PCLK_PWM>;
688 bus_intmem@ff700000 {
689 compatible = "mmio-sram";
690 reg = <0xff700000 0x18000>;
691 #address-cells = <1>;
693 ranges = <0 0xff700000 0x18000>;
695 compatible = "rockchip,rk3066-smp-sram";
701 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
702 reg = <0xff720000 0x1000>;
705 qos_gpu_r: qos@ffaa0000 {
706 compatible = "syscon";
707 reg = <0xffaa0000 0x20>;
710 qos_gpu_w: qos@ffaa0080 {
711 compatible = "syscon";
712 reg = <0xffaa0080 0x20>;
715 qos_vio1_vop: qos@ffad0000 {
716 compatible = "syscon";
717 reg = <0xffad0000 0x20>;
720 qos_vio1_isp_w0: qos@ffad0100 {
721 compatible = "syscon";
722 reg = <0xffad0100 0x20>;
725 qos_vio1_isp_w1: qos@ffad0180 {
726 compatible = "syscon";
727 reg = <0xffad0180 0x20>;
730 qos_vio0_vop: qos@ffad0400 {
731 compatible = "syscon";
732 reg = <0xffad0400 0x20>;
735 qos_vio0_vip: qos@ffad0480 {
736 compatible = "syscon";
737 reg = <0xffad0480 0x20>;
740 qos_vio0_iep: qos@ffad0500 {
741 compatible = "syscon";
742 reg = <0xffad0500 0x20>;
745 qos_vio2_rga_r: qos@ffad0800 {
746 compatible = "syscon";
747 reg = <0xffad0800 0x20>;
750 qos_vio2_rga_w: qos@ffad0880 {
751 compatible = "syscon";
752 reg = <0xffad0880 0x20>;
755 qos_vio1_isp_r: qos@ffad0900 {
756 compatible = "syscon";
757 reg = <0xffad0900 0x20>;
760 qos_video: qos@ffae0000 {
761 compatible = "syscon";
762 reg = <0xffae0000 0x20>;
765 qos_hevc_r: qos@ffaf0000 {
766 compatible = "syscon";
767 reg = <0xffaf0000 0x20>;
770 qos_hevc_w: qos@ffaf0080 {
771 compatible = "syscon";
772 reg = <0xffaf0080 0x20>;
775 pmu: power-management@ff730000 {
776 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
777 reg = <0xff730000 0x100>;
779 power: power-controller {
780 compatible = "rockchip,rk3288-power-controller";
781 #power-domain-cells = <1>;
782 #address-cells = <1>;
786 * Note: Although SCLK_* are the working clocks
787 * of device without including on the NOC, needed for
790 * The clocks on the which NOC:
791 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
792 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
793 * ACLK_RGA is on ACLK_RGA_NIU.
794 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
796 * Which clock are device clocks:
798 * *_IEP IEP:Image Enhancement Processor
799 * *_ISP ISP:Image Signal Processing
800 * *_VIP VIP:Video Input Processor
801 * *_VOP* VOP:Visual Output Processor
808 pd_vio@RK3288_PD_VIO {
809 reg = <RK3288_PD_VIO>;
810 clocks = <&cru ACLK_IEP>,
824 <&cru PCLK_EDP_CTRL>,
825 <&cru PCLK_HDMI_CTRL>,
826 <&cru PCLK_LVDS_PHY>,
827 <&cru PCLK_MIPI_CSI>,
828 <&cru PCLK_MIPI_DSI0>,
829 <&cru PCLK_MIPI_DSI1>,
835 pm_qos = <&qos_vio0_iep>,
847 * Note: The following 3 are HEVC(H.265) clocks,
848 * and on the ACLK_HEVC_NIU (NOC).
850 pd_hevc@RK3288_PD_HEVC {
851 reg = <RK3288_PD_HEVC>;
852 clocks = <&cru ACLK_HEVC>,
853 <&cru SCLK_HEVC_CABAC>,
854 <&cru SCLK_HEVC_CORE>;
855 pm_qos = <&qos_hevc_r>,
860 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
861 * (video endecoder & decoder) clocks that on the
862 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
864 pd_video@RK3288_PD_VIDEO {
865 reg = <RK3288_PD_VIDEO>;
866 clocks = <&cru ACLK_VCODEC>,
868 pm_qos = <&qos_video>;
872 * Note: ACLK_GPU is the GPU clock,
873 * and on the ACLK_GPU_NIU (NOC).
875 pd_gpu@RK3288_PD_GPU {
876 reg = <RK3288_PD_GPU>;
877 clocks = <&cru ACLK_GPU>;
878 pm_qos = <&qos_gpu_r>,
884 compatible = "syscon-reboot-mode";
886 mode-normal = <BOOT_NORMAL>;
887 mode-recovery = <BOOT_RECOVERY>;
888 mode-bootloader = <BOOT_FASTBOOT>;
889 mode-loader = <BOOT_LOADER>;
890 mode-ums = <BOOT_UMS>;
894 sgrf: syscon@ff740000 {
895 compatible = "rockchip,rk3288-sgrf", "syscon";
896 reg = <0xff740000 0x1000>;
899 cru: clock-controller@ff760000 {
900 compatible = "rockchip,rk3288-cru";
901 reg = <0xff760000 0x1000>;
902 rockchip,grf = <&grf>;
905 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
906 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
907 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
908 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
909 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
911 assigned-clock-rates = <0>, <0>,
912 <594000000>, <400000000>,
913 <500000000>, <300000000>,
914 <150000000>, <75000000>,
915 <300000000>, <150000000>,
917 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
920 grf: syscon@ff770000 {
921 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
922 reg = <0xff770000 0x1000>;
925 compatible = "rockchip,rk3288-dp-phy";
926 clocks = <&cru SCLK_EDP_24M>;
932 io_domains: io-domains {
933 compatible = "rockchip,rk3288-io-voltage-domain";
938 compatible = "rockchip,rk3288-usb-phy";
939 #address-cells = <1>;
943 usbphy0: usb-phy@320 {
946 clocks = <&cru SCLK_OTGPHY0>;
947 clock-names = "phyclk";
949 resets = <&cru SRST_USBOTG_PHY>;
950 reset-names = "phy-reset";
953 usbphy1: usb-phy@334 {
956 clocks = <&cru SCLK_OTGPHY1>;
957 clock-names = "phyclk";
961 usbphy2: usb-phy@348 {
964 clocks = <&cru SCLK_OTGPHY2>;
965 clock-names = "phyclk";
967 resets = <&cru SRST_USBHOST1_PHY>;
968 reset-names = "phy-reset";
973 wdt: watchdog@ff800000 {
974 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
975 reg = <0xff800000 0x100>;
976 clocks = <&cru PCLK_WDT>;
977 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
981 spdif: sound@ff88b0000 {
982 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
983 reg = <0xff8b0000 0x10000>;
984 #sound-dai-cells = <0>;
985 clock-names = "hclk", "mclk";
986 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
987 dmas = <&dmac_bus_s 3>;
989 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
990 pinctrl-names = "default";
991 pinctrl-0 = <&spdif_tx>;
992 rockchip,grf = <&grf>;
997 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
998 reg = <0xff890000 0x10000>;
999 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1000 #address-cells = <1>;
1002 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1003 dma-names = "tx", "rx";
1004 clock-names = "i2s_hclk", "i2s_clk";
1005 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&i2s0_bus>;
1008 rockchip,playback-channels = <8>;
1009 rockchip,capture-channels = <2>;
1010 status = "disabled";
1013 vopb: vop@ff930000 {
1014 compatible = "rockchip,rk3288-vop";
1015 reg = <0xff930000 0x19c>;
1016 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1018 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1019 power-domains = <&power RK3288_PD_VIO>;
1020 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1021 reset-names = "axi", "ahb", "dclk";
1022 iommus = <&vopb_mmu>;
1023 status = "disabled";
1026 #address-cells = <1>;
1029 vopb_out_hdmi: endpoint@0 {
1031 remote-endpoint = <&hdmi_in_vopb>;
1034 vopb_out_edp: endpoint@1 {
1036 remote-endpoint = <&edp_in_vopb>;
1039 vopb_out_mipi: endpoint@2 {
1041 remote-endpoint = <&mipi_in_vopb>;
1044 vopb_out_lvds: endpoint@3 {
1046 remote-endpoint = <&lvds_in_vopb>;
1051 vopb_mmu: iommu@ff930300 {
1052 compatible = "rockchip,iommu";
1053 reg = <0xff930300 0x100>;
1054 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1055 interrupt-names = "vopb_mmu";
1056 power-domains = <&power RK3288_PD_VIO>;
1058 status = "disabled";
1061 vopl: vop@ff940000 {
1062 compatible = "rockchip,rk3288-vop";
1063 reg = <0xff940000 0x19c>;
1064 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1066 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1067 power-domains = <&power RK3288_PD_VIO>;
1068 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1069 reset-names = "axi", "ahb", "dclk";
1070 iommus = <&vopl_mmu>;
1071 status = "disabled";
1074 #address-cells = <1>;
1077 vopl_out_hdmi: endpoint@0 {
1079 remote-endpoint = <&hdmi_in_vopl>;
1082 vopl_out_edp: endpoint@1 {
1084 remote-endpoint = <&edp_in_vopl>;
1087 vopl_out_mipi: endpoint@2 {
1089 remote-endpoint = <&mipi_in_vopl>;
1092 vopl_out_lvds: endpoint@3 {
1094 remote-endpoint = <&lvds_in_vopl>;
1100 vopl_mmu: iommu@ff940300 {
1101 compatible = "rockchip,iommu";
1102 reg = <0xff940300 0x100>;
1103 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1104 interrupt-names = "vopl_mmu";
1105 power-domains = <&power RK3288_PD_VIO>;
1107 status = "disabled";
1110 mipi_dsi: mipi@ff960000 {
1111 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1112 reg = <0xff960000 0x4000>;
1113 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1115 clock-names = "ref", "pclk";
1116 power-domains = <&power RK3288_PD_VIO>;
1117 rockchip,grf = <&grf>;
1118 #address-cells = <1>;
1120 status = "disabled";
1124 #address-cells = <1>;
1126 mipi_in_vopb: endpoint@0 {
1128 remote-endpoint = <&vopb_out_mipi>;
1130 mipi_in_vopl: endpoint@1 {
1132 remote-endpoint = <&vopl_out_mipi>;
1139 compatible = "rockchip,rk3288-dp";
1140 reg = <0xff970000 0x4000>;
1141 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1143 clock-names = "dp", "pclk";
1146 resets = <&cru SRST_EDP>;
1148 rockchip,grf = <&grf>;
1149 status = "disabled";
1152 #address-cells = <1>;
1156 #address-cells = <1>;
1158 edp_in_vopb: endpoint@0 {
1160 remote-endpoint = <&vopb_out_edp>;
1162 edp_in_vopl: endpoint@1 {
1164 remote-endpoint = <&vopl_out_edp>;
1170 lvds: lvds@ff96c000 {
1171 compatible = "rockchip,rk3288-lvds";
1172 reg = <0xff96c000 0x4000>;
1173 clocks = <&cru PCLK_LVDS_PHY>;
1174 clock-names = "pclk_lvds";
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&lcdc0_ctl>;
1177 power-domains = <&power RK3288_PD_VIO>;
1178 rockchip,grf = <&grf>;
1179 status = "disabled";
1182 #address-cells = <1>;
1188 #address-cells = <1>;
1191 lvds_in_vopb: endpoint@0 {
1193 remote-endpoint = <&vopb_out_lvds>;
1195 lvds_in_vopl: endpoint@1 {
1197 remote-endpoint = <&vopl_out_lvds>;
1203 hdmi: hdmi@ff980000 {
1204 compatible = "rockchip,rk3288-dw-hdmi";
1205 reg = <0xff980000 0x20000>;
1207 rockchip,grf = <&grf>;
1208 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1209 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1210 clock-names = "iahb", "isfr";
1211 power-domains = <&power RK3288_PD_VIO>;
1212 status = "disabled";
1216 #address-cells = <1>;
1218 hdmi_in_vopb: endpoint@0 {
1220 remote-endpoint = <&vopb_out_hdmi>;
1222 hdmi_in_vopl: endpoint@1 {
1224 remote-endpoint = <&vopl_out_hdmi>;
1231 compatible = "arm,malit764",
1235 reg = <0xffa30000 0x10000>;
1236 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1239 interrupt-names = "JOB", "MMU", "GPU";
1240 clocks = <&cru ACLK_GPU>;
1241 clock-names = "clk_mali";
1242 operating-points = <
1245 /* 500000 1200000 - See crosbug.com/p/33857 */
1251 #cooling-cells = <2>; /* min followed by max */
1252 power-domains = <&power RK3288_PD_GPU>;
1253 status = "disabled";
1256 vpu: video-codec@ff9a0000 {
1257 compatible = "rockchip,rk3288-vpu";
1258 reg = <0xff9a0000 0x800>;
1259 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1261 interrupt-names = "vepu", "vdpu";
1262 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1263 clock-names = "aclk", "hclk";
1264 power-domains = <&power RK3288_PD_VIDEO>;
1265 iommus = <&vpu_mmu>;
1266 assigned-clocks = <&cru ACLK_VCODEC>;
1267 assigned-clock-rates = <400000000>;
1268 status = "disabled";
1271 vpu_service: vpu-service@ff9a0000 {
1272 compatible = "rockchip,vpu_service";
1273 reg = <0xff9a0000 0x800>;
1274 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1276 interrupt-names = "irq_enc", "irq_dec";
1277 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1278 clock-names = "aclk_vcodec", "hclk_vcodec";
1279 power-domains = <&power RK3288_PD_VIDEO>;
1280 rockchip,grf = <&grf>;
1281 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1282 reset-names = "video_a", "video_h";
1283 iommus = <&vpu_mmu>;
1284 iommu_enabled = <1>;
1286 status = "disabled";
1289 vpu_mmu: iommu@ff9a0800 {
1290 compatible = "rockchip,iommu";
1291 reg = <0xff9a0800 0x100>;
1292 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1293 interrupt-names = "vpu_mmu";
1294 power-domains = <&power RK3288_PD_VIDEO>;
1298 hevc_service: hevc-service@ff9c0000 {
1299 compatible = "rockchip,hevc_service";
1300 reg = <0xff9c0000 0x400>;
1301 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1302 interrupt-names = "irq_dec";
1303 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1304 <&cru SCLK_HEVC_CORE>,
1305 <&cru SCLK_HEVC_CABAC>;
1306 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1309 * The 4K hevc would also work well with 500/125/300/300,
1310 * no more err irq and reset request.
1312 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1313 <&cru SCLK_HEVC_CORE>,
1314 <&cru SCLK_HEVC_CABAC>;
1315 assigned-clock-rates = <400000000>, <100000000>,
1316 <300000000>, <300000000>;
1318 resets = <&cru SRST_HEVC>;
1319 reset-names = "video";
1320 power-domains = <&power RK3288_PD_HEVC>;
1321 rockchip,grf = <&grf>;
1323 iommus = <&hevc_mmu>;
1324 iommu_enabled = <1>;
1325 status = "disabled";
1328 hevc_mmu: iommu@ff9c0440 {
1329 compatible = "rockchip,iommu";
1330 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1331 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1332 interrupt-names = "hevc_mmu";
1333 power-domains = <&power RK3288_PD_HEVC>;
1337 gic: interrupt-controller@ffc01000 {
1338 compatible = "arm,gic-400";
1339 interrupt-controller;
1340 #interrupt-cells = <3>;
1341 #address-cells = <0>;
1343 reg = <0xffc01000 0x1000>,
1344 <0xffc02000 0x1000>,
1345 <0xffc04000 0x2000>,
1346 <0xffc06000 0x2000>;
1347 interrupts = <GIC_PPI 9 0xf04>;
1350 efuse: efuse@ffb40000 {
1351 compatible = "rockchip,rockchip-efuse";
1352 reg = <0xffb40000 0x20>;
1353 #address-cells = <1>;
1355 clocks = <&cru PCLK_EFUSE256>;
1356 clock-names = "pclk_efuse";
1358 cpu_leakage: cpu_leakage@17 {
1363 cif_isp0: cif_isp@ff910000 {
1364 compatible = "rockchip,rk3288-cif-isp";
1365 rockchip,grf = <&grf>;
1366 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1367 reg-names = "register", "csihost-register";
1368 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1369 <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1370 <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1371 <&cru SCLK_MIPIDSI_24M>;
1372 clock-names = "aclk_isp", "hclk_isp",
1373 "sclk_isp", "sclk_isp_jpe",
1374 "pclk_mipi_csi", "pclk_isp_in",
1376 resets = <&cru SRST_ISP>;
1377 reset-names = "rst_isp";
1378 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1379 interrupt-names = "cif_isp10_irq";
1380 status = "disabled";
1384 compatible = "rockchip,rk3288-pinctrl";
1385 rockchip,grf = <&grf>;
1386 rockchip,pmu = <&pmu>;
1387 #address-cells = <1>;
1391 gpio0: gpio0@ff750000 {
1392 compatible = "rockchip,gpio-bank";
1393 reg = <0xff750000 0x100>;
1394 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1395 clocks = <&cru PCLK_GPIO0>;
1400 interrupt-controller;
1401 #interrupt-cells = <2>;
1404 gpio1: gpio1@ff780000 {
1405 compatible = "rockchip,gpio-bank";
1406 reg = <0xff780000 0x100>;
1407 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1408 clocks = <&cru PCLK_GPIO1>;
1413 interrupt-controller;
1414 #interrupt-cells = <2>;
1417 gpio2: gpio2@ff790000 {
1418 compatible = "rockchip,gpio-bank";
1419 reg = <0xff790000 0x100>;
1420 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cru PCLK_GPIO2>;
1426 interrupt-controller;
1427 #interrupt-cells = <2>;
1430 gpio3: gpio3@ff7a0000 {
1431 compatible = "rockchip,gpio-bank";
1432 reg = <0xff7a0000 0x100>;
1433 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1434 clocks = <&cru PCLK_GPIO3>;
1439 interrupt-controller;
1440 #interrupt-cells = <2>;
1443 gpio4: gpio4@ff7b0000 {
1444 compatible = "rockchip,gpio-bank";
1445 reg = <0xff7b0000 0x100>;
1446 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1447 clocks = <&cru PCLK_GPIO4>;
1452 interrupt-controller;
1453 #interrupt-cells = <2>;
1456 gpio5: gpio5@ff7c0000 {
1457 compatible = "rockchip,gpio-bank";
1458 reg = <0xff7c0000 0x100>;
1459 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1460 clocks = <&cru PCLK_GPIO5>;
1465 interrupt-controller;
1466 #interrupt-cells = <2>;
1469 gpio6: gpio6@ff7d0000 {
1470 compatible = "rockchip,gpio-bank";
1471 reg = <0xff7d0000 0x100>;
1472 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1473 clocks = <&cru PCLK_GPIO6>;
1478 interrupt-controller;
1479 #interrupt-cells = <2>;
1482 gpio7: gpio7@ff7e0000 {
1483 compatible = "rockchip,gpio-bank";
1484 reg = <0xff7e0000 0x100>;
1485 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1486 clocks = <&cru PCLK_GPIO7>;
1491 interrupt-controller;
1492 #interrupt-cells = <2>;
1495 gpio8: gpio8@ff7f0000 {
1496 compatible = "rockchip,gpio-bank";
1497 reg = <0xff7f0000 0x100>;
1498 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1499 clocks = <&cru PCLK_GPIO8>;
1504 interrupt-controller;
1505 #interrupt-cells = <2>;
1509 hdmi_ddc: hdmi-ddc {
1510 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1511 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1515 pcfg_pull_up: pcfg-pull-up {
1519 pcfg_pull_down: pcfg-pull-down {
1523 pcfg_pull_none: pcfg-pull-none {
1527 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1529 drive-strength = <12>;
1533 global_pwroff: global-pwroff {
1534 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1537 ddrio_pwroff: ddrio-pwroff {
1538 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1541 ddr0_retention: ddr0-retention {
1542 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1545 ddr1_retention: ddr1-retention {
1546 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1552 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1557 i2c0_xfer: i2c0-xfer {
1558 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1559 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1564 i2c1_xfer: i2c1-xfer {
1565 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1566 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1571 i2c2_xfer: i2c2-xfer {
1572 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1573 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1578 i2c3_xfer: i2c3-xfer {
1579 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1580 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1585 i2c4_xfer: i2c4-xfer {
1586 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1587 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1592 i2c5_xfer: i2c5-xfer {
1593 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1594 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1599 i2s0_bus: i2s0-bus {
1600 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1601 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1602 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1603 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1604 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1605 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1610 lcdc0_ctl: lcdc0-ctl {
1611 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1612 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1613 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1614 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1619 sdmmc_clk: sdmmc-clk {
1620 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1623 sdmmc_cmd: sdmmc-cmd {
1624 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1627 sdmmc_cd: sdmcc-cd {
1628 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1631 sdmmc_bus1: sdmmc-bus1 {
1632 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1635 sdmmc_bus4: sdmmc-bus4 {
1636 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1637 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1638 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1639 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1644 sdio0_bus1: sdio0-bus1 {
1645 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1648 sdio0_bus4: sdio0-bus4 {
1649 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1650 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1651 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1652 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1655 sdio0_cmd: sdio0-cmd {
1656 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1659 sdio0_clk: sdio0-clk {
1660 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1663 sdio0_cd: sdio0-cd {
1664 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1667 sdio0_wp: sdio0-wp {
1668 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1671 sdio0_pwr: sdio0-pwr {
1672 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1675 sdio0_bkpwr: sdio0-bkpwr {
1676 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1679 sdio0_int: sdio0-int {
1680 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1685 sdio1_bus1: sdio1-bus1 {
1686 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1689 sdio1_bus4: sdio1-bus4 {
1690 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1691 <3 25 4 &pcfg_pull_up>,
1692 <3 26 4 &pcfg_pull_up>,
1693 <3 27 4 &pcfg_pull_up>;
1696 sdio1_cd: sdio1-cd {
1697 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1700 sdio1_wp: sdio1-wp {
1701 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1704 sdio1_bkpwr: sdio1-bkpwr {
1705 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1708 sdio1_int: sdio1-int {
1709 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1712 sdio1_cmd: sdio1-cmd {
1713 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1716 sdio1_clk: sdio1-clk {
1717 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1720 sdio1_pwr: sdio1-pwr {
1721 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1726 emmc_clk: emmc-clk {
1727 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1730 emmc_cmd: emmc-cmd {
1731 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1734 emmc_pwr: emmc-pwr {
1735 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1738 emmc_bus1: emmc-bus1 {
1739 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1742 emmc_bus4: emmc-bus4 {
1743 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1744 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1745 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1746 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1749 emmc_bus8: emmc-bus8 {
1750 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1751 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1752 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1753 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1754 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1755 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1756 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1757 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1762 spi0_clk: spi0-clk {
1763 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1765 spi0_cs0: spi0-cs0 {
1766 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1769 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1772 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1774 spi0_cs1: spi0-cs1 {
1775 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1779 spi1_clk: spi1-clk {
1780 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1782 spi1_cs0: spi1-cs0 {
1783 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1786 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1789 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1794 spi2_cs1: spi2-cs1 {
1795 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1797 spi2_clk: spi2-clk {
1798 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1800 spi2_cs0: spi2-cs0 {
1801 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1804 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1807 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1812 uart0_xfer: uart0-xfer {
1813 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1814 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1817 uart0_cts: uart0-cts {
1818 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1821 uart0_rts: uart0-rts {
1822 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1827 uart1_xfer: uart1-xfer {
1828 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1829 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1832 uart1_cts: uart1-cts {
1833 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1836 uart1_rts: uart1-rts {
1837 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1842 uart2_xfer: uart2-xfer {
1843 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1844 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1846 /* no rts / cts for uart2 */
1850 uart3_xfer: uart3-xfer {
1851 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1852 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1855 uart3_cts: uart3-cts {
1856 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1859 uart3_rts: uart3-rts {
1860 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1865 uart4_xfer: uart4-xfer {
1866 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1867 <5 13 3 &pcfg_pull_none>;
1870 uart4_cts: uart4-cts {
1871 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1874 uart4_rts: uart4-rts {
1875 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1880 otp_gpio: otp-gpio {
1881 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1885 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1890 pwm0_pin: pwm0-pin {
1891 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1896 pwm1_pin: pwm1-pin {
1897 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1902 pwm2_pin: pwm2-pin {
1903 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1908 pwm3_pin: pwm3-pin {
1909 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1914 rgmii_pins: rgmii-pins {
1915 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1916 <3 31 3 &pcfg_pull_none>,
1917 <3 26 3 &pcfg_pull_none>,
1918 <3 27 3 &pcfg_pull_none>,
1919 <3 28 3 &pcfg_pull_none_12ma>,
1920 <3 29 3 &pcfg_pull_none_12ma>,
1921 <3 24 3 &pcfg_pull_none_12ma>,
1922 <3 25 3 &pcfg_pull_none_12ma>,
1923 <4 0 3 &pcfg_pull_none>,
1924 <4 5 3 &pcfg_pull_none>,
1925 <4 6 3 &pcfg_pull_none>,
1926 <4 9 3 &pcfg_pull_none_12ma>,
1927 <4 4 3 &pcfg_pull_none_12ma>,
1928 <4 1 3 &pcfg_pull_none>,
1929 <4 3 3 &pcfg_pull_none>;
1932 rmii_pins: rmii-pins {
1933 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1934 <3 31 3 &pcfg_pull_none>,
1935 <3 28 3 &pcfg_pull_none>,
1936 <3 29 3 &pcfg_pull_none>,
1937 <4 0 3 &pcfg_pull_none>,
1938 <4 5 3 &pcfg_pull_none>,
1939 <4 4 3 &pcfg_pull_none>,
1940 <4 1 3 &pcfg_pull_none>,
1941 <4 2 3 &pcfg_pull_none>,
1942 <4 3 3 &pcfg_pull_none>;
1947 spdif_tx: spdif-tx {
1948 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1953 cif_dvp_d2d9: cif-dvp-d2d9 {
1954 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
1955 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1956 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1957 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1958 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1959 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1960 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1961 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1962 <2 8 RK_FUNC_1 &pcfg_pull_none>,
1963 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1964 <2 11 RK_FUNC_1 &pcfg_pull_none>;