1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/pinctrl/rockchip-rk3288.h>
7 pinctrl: pinctrl@ff770000 {
8 compatible = "rockchip,rk3288-pinctrl";
9 reg = <0xff770000 0x140>,
12 reg-names = "base", "pull", "drv";
17 gpio0: gpio0@ff750000 {
18 compatible = "rockchip,rk3288-gpio-bank0";
19 reg = <0xff750000 0x100>,
23 reg-names = "base", "mux_bank0", "pull_bank0", "drv_bank0";
24 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
25 clocks = <&clk_gates17 4>;
31 #interrupt-cells = <2>;
34 gpio1: gpio1@ff780000 {
35 compatible = "rockchip,gpio-bank";
36 reg = <0xff780000 0x100>;
37 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&clk_gates14 1>;
44 #interrupt-cells = <2>;
47 gpio2: gpio2@ff790000 {
48 compatible = "rockchip,gpio-bank";
49 reg = <0xff790000 0x100>;
50 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
51 clocks = <&clk_gates14 2>;
57 #interrupt-cells = <2>;
60 gpio3: gpio3@ff7a0000 {
61 compatible = "rockchip,gpio-bank";
62 reg = <0xff7a0000 0x100>;
63 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
64 clocks = <&clk_gates14 3>;
70 #interrupt-cells = <2>;
73 gpio4: gpio4@ff7b0000 {
74 compatible = "rockchip,gpio-bank";
75 reg = <0xff7b0000 0x100>;
76 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&clk_gates14 4>;
83 #interrupt-cells = <2>;
86 gpio5: gpio5@ff7c0000 {
87 compatible = "rockchip,gpio-bank";
88 reg = <0xff7c0000 0x100>;
89 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&clk_gates14 5>;
96 #interrupt-cells = <2>;
99 gpio6: gpio6@ff7d0000 {
100 compatible = "rockchip,gpio-bank";
101 reg = <0xff7d0000 0x100>;
102 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&clk_gates14 6>;
108 interrupt-controller;
109 #interrupt-cells = <2>;
112 gpio7: gpio7@ff7e0000 {
113 compatible = "rockchip,gpio-bank";
114 reg = <0xff7e0000 0x100>;
115 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&clk_gates14 7>;
121 interrupt-controller;
122 #interrupt-cells = <2>;
125 gpio8: gpio8@ff7f0000 {
126 compatible = "rockchip,gpio-bank";
127 reg = <0xff7f0000 0x100>;
128 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&clk_gates14 8>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
138 gpio15: gpio15@ff7f2000 {
139 compatible = "rockchip,gpio-bank";
140 reg = <0xff7f2000 0x100>;
141 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;//127 = 160-32-1
142 clocks = <&clk_gates14 8>;
147 interrupt-controller;
148 #interrupt-cells = <2>;
151 pcfg_pull_up: pcfg_pull_up {
155 pcfg_pull_down: pcfg_pull_down {
159 pcfg_pull_none: pcfg_pull_none {
164 uart0_xfer: uart0-xfer {
165 rockchip,pins = <UART0BT_SIN>,
167 rockchip,pull = <VALUE_PULL_DISABLE>;
168 rockchip,drive = <VALUE_DRV_DEFAULT>;
169 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
172 uart0_cts: uart0-cts {
173 rockchip,pins = <UART0BT_CTSN>;
174 rockchip,pull = <VALUE_PULL_DISABLE>;
175 rockchip,drive = <VALUE_DRV_DEFAULT>;
176 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
179 uart0_rts: uart0-rts {
180 rockchip,pins = <UART0BT_RTSN>;
181 rockchip,pull = <VALUE_PULL_DISABLE>;
182 rockchip,drive = <VALUE_DRV_DEFAULT>;
183 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
186 uart0_rts_gpio: uart0-rts-gpio {
187 rockchip,pins = <FUNC_TO_GPIO(UART0BT_RTSN)>;
188 rockchip,drive = <VALUE_DRV_DEFAULT>;
193 uart1_xfer: uart1-xfer {
194 rockchip,pins = <UART1BB_SIN>,
196 rockchip,pull = <VALUE_PULL_DISABLE>;
197 rockchip,drive = <VALUE_DRV_DEFAULT>;
198 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
201 uart1_cts: uart1-cts {
202 rockchip,pins = <UART1BB_CTSN>;
203 rockchip,pull = <VALUE_PULL_DISABLE>;
204 rockchip,drive = <VALUE_DRV_DEFAULT>;
205 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
208 uart1_rts: uart1-rts {
209 rockchip,pins = <UART1BB_RTSN>;
210 rockchip,pull = <VALUE_PULL_DISABLE>;
211 rockchip,drive = <VALUE_DRV_DEFAULT>;
212 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
215 uart1_rts_gpio: uart1-rts-gpio {
216 rockchip,pins = <FUNC_TO_GPIO(UART1BB_RTSN)>;
217 rockchip,drive = <VALUE_DRV_DEFAULT>;
222 uart2_xfer: uart2-xfer {
223 rockchip,pins = <UART2DBG_SIN>,
225 rockchip,pull = <VALUE_PULL_DISABLE>;
226 rockchip,drive = <VALUE_DRV_DEFAULT>;
227 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
229 /* no rts / cts for uart2 */
233 uart3_xfer: uart3-xfer {
234 rockchip,pins = <UART3GPS_SIN>,
236 rockchip,pull = <VALUE_PULL_DISABLE>;
237 rockchip,drive = <VALUE_DRV_DEFAULT>;
238 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
241 uart3_cts: uart3-cts {
242 rockchip,pins = <UART3GPS_CTSN>;
243 rockchip,pull = <VALUE_PULL_DISABLE>;
244 rockchip,drive = <VALUE_DRV_DEFAULT>;
245 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
248 uart3_rts: uart3-rts {
249 rockchip,pins = <UART3GPS_RTSN>;
250 rockchip,pull = <VALUE_PULL_DISABLE>;
251 rockchip,drive = <VALUE_DRV_DEFAULT>;
252 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
257 uart4_xfer: uart4-xfer {
258 rockchip,pins = <UART4EXP_SIN>,
260 rockchip,pull = <VALUE_PULL_DISABLE>;
261 rockchip,drive = <VALUE_DRV_DEFAULT>;
262 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
265 uart4_cts: uart4-cts {
266 rockchip,pins = <UART4EXP_CTSN>;
267 rockchip,pull = <VALUE_PULL_DISABLE>;
268 rockchip,drive = <VALUE_DRV_DEFAULT>;
269 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
272 uart4_rts: uart4-rts {
273 rockchip,pins = <UART4EXP_RTSN>;
274 rockchip,pull = <VALUE_PULL_DISABLE>;
275 rockchip,drive = <VALUE_DRV_DEFAULT>;
276 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
282 rockchip,pins = <I2C0PMU_SDA>;
283 rockchip,pull = <VALUE_PULL_DISABLE>;
284 rockchip,drive = <VALUE_DRV_DEFAULT>;
285 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
289 rockchip,pins = <I2C0PMU_SCL>;
290 rockchip,pull = <VALUE_PULL_DISABLE>;
291 rockchip,drive = <VALUE_DRV_DEFAULT>;
292 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
295 i2c0_gpio: i2c0-gpio {
296 rockchip,pins = <FUNC_TO_GPIO(I2C0PMU_SDA)>, <FUNC_TO_GPIO(I2C0PMU_SCL)>;
297 rockchip,drive = <VALUE_DRV_DEFAULT>;
303 rockchip,pins = <I2C1SENSOR_SDA>;
304 rockchip,pull = <VALUE_PULL_DISABLE>;
305 rockchip,drive = <VALUE_DRV_DEFAULT>;
306 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
310 rockchip,pins = <I2C1SENSOR_SCL>;
311 rockchip,pull = <VALUE_PULL_DISABLE>;
312 rockchip,drive = <VALUE_DRV_DEFAULT>;
313 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
316 i2c1_gpio: i2c1-gpio {
317 rockchip,pins = <FUNC_TO_GPIO(I2C1SENSOR_SDA)>, <FUNC_TO_GPIO(I2C1SENSOR_SCL)>;
318 rockchip,drive = <VALUE_DRV_DEFAULT>;
324 rockchip,pins = <I2C2AUDIO_SDA>;
325 rockchip,pull = <VALUE_PULL_DISABLE>;
326 rockchip,drive = <VALUE_DRV_DEFAULT>;
327 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
331 rockchip,pins = <I2C2AUDIO_SCL>;
332 rockchip,pull = <VALUE_PULL_DISABLE>;
333 rockchip,drive = <VALUE_DRV_DEFAULT>;
334 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
337 i2c2_gpio: i2c2-gpio {
338 rockchip,pins = <FUNC_TO_GPIO(I2C2AUDIO_SDA)>, <FUNC_TO_GPIO(I2C2AUDIO_SCL)>;
339 rockchip,drive = <VALUE_DRV_DEFAULT>;
345 rockchip,pins = <I2C3CAM_SDA>;
346 rockchip,pull = <VALUE_PULL_DISABLE>;
347 rockchip,drive = <VALUE_DRV_DEFAULT>;
348 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
352 rockchip,pins = <I2C3CAM_SCL>;
353 rockchip,pull = <VALUE_PULL_DISABLE>;
354 rockchip,drive = <VALUE_DRV_DEFAULT>;
355 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
358 i2c3_gpio: i2c3-gpio {
359 rockchip,pins = <FUNC_TO_GPIO(I2C3CAM_SDA)>, <FUNC_TO_GPIO(I2C3CAM_SCL)>;
360 rockchip,drive = <VALUE_DRV_DEFAULT>;
366 rockchip,pins = <I2C4TP_SDA>;
367 rockchip,pull = <VALUE_PULL_DISABLE>;
368 rockchip,drive = <VALUE_DRV_DEFAULT>;
369 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
373 rockchip,pins = <I2C4TP_SCL>;
374 rockchip,pull = <VALUE_PULL_DISABLE>;
375 rockchip,drive = <VALUE_DRV_DEFAULT>;
376 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
379 i2c4_gpio: i2c4-gpio {
380 rockchip,pins = <FUNC_TO_GPIO(I2C4TP_SDA)>, <FUNC_TO_GPIO(I2C4TP_SCL)>;
381 rockchip,drive = <VALUE_DRV_DEFAULT>;
387 rockchip,pins = <EDPHDMII2C_SDA>;
388 rockchip,pull = <VALUE_PULL_DISABLE>;
389 rockchip,drive = <VALUE_DRV_DEFAULT>;
390 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
394 rockchip,pins = <EDPHDMII2C_SCL>;
395 rockchip,pull = <VALUE_PULL_DISABLE>;
396 rockchip,drive = <VALUE_DRV_DEFAULT>;
397 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
400 i2c5_gpio: i2c5-gpio {
401 rockchip,pins = <FUNC_TO_GPIO(EDPHDMII2C_SDA)>, <FUNC_TO_GPIO(EDPHDMII2C_SCL)>;
402 rockchip,drive = <VALUE_DRV_DEFAULT>;
408 rockchip,pins = <SPI0_TXD>;
409 rockchip,pull = <VALUE_PULL_DISABLE>;
410 rockchip,drive = <VALUE_DRV_DEFAULT>;
411 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
415 rockchip,pins = <SPI0_RXD>;
416 rockchip,pull = <VALUE_PULL_DISABLE>;
417 rockchip,drive = <VALUE_DRV_DEFAULT>;
418 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
422 rockchip,pins = <SPI0_CLK>;
423 rockchip,pull = <VALUE_PULL_DISABLE>;
424 rockchip,drive = <VALUE_DRV_DEFAULT>;
425 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
429 rockchip,pins = <SPI0_CS0>;
430 rockchip,pull = <VALUE_PULL_DISABLE>;
431 rockchip,drive = <VALUE_DRV_DEFAULT>;
432 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
436 rockchip,pins = <SPI0_CS1>;
437 rockchip,pull = <VALUE_PULL_DISABLE>;
438 rockchip,drive = <VALUE_DRV_DEFAULT>;
439 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
446 rockchip,pins = <SPI1_TXD>;
447 rockchip,pull = <VALUE_PULL_DISABLE>;
448 rockchip,drive = <VALUE_DRV_DEFAULT>;
449 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
453 rockchip,pins = <SPI1_RXD>;
454 rockchip,pull = <VALUE_PULL_DISABLE>;
455 rockchip,drive = <VALUE_DRV_DEFAULT>;
456 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
460 rockchip,pins = <SPI1_CLK>;
461 rockchip,pull = <VALUE_PULL_DISABLE>;
462 rockchip,drive = <VALUE_DRV_DEFAULT>;
463 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
467 rockchip,pins = <SPI1_CS0>;
468 rockchip,pull = <VALUE_PULL_DISABLE>;
469 rockchip,drive = <VALUE_DRV_DEFAULT>;
470 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
477 rockchip,pins = <SPI2_TXD>;
478 rockchip,pull = <VALUE_PULL_DISABLE>;
479 rockchip,drive = <VALUE_DRV_DEFAULT>;
480 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
484 rockchip,pins = <SPI2_RXD>;
485 rockchip,pull = <VALUE_PULL_DISABLE>;
486 rockchip,drive = <VALUE_DRV_DEFAULT>;
487 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
491 rockchip,pins = <SPI2_CLK>;
492 rockchip,pull = <VALUE_PULL_DISABLE>;
493 rockchip,drive = <VALUE_DRV_DEFAULT>;
494 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
498 rockchip,pins = <SPI2_CS0>;
499 rockchip,pull = <VALUE_PULL_DISABLE>;
500 rockchip,drive = <VALUE_DRV_DEFAULT>;
501 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
505 rockchip,pins = <SPI2_CS1>;
506 rockchip,pull = <VALUE_PULL_DISABLE>;
507 rockchip,drive = <VALUE_DRV_DEFAULT>;
508 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
516 rockchip,pins = <I2S_CLK>;
517 rockchip,pull = <VALUE_PULL_DISABLE>;
518 rockchip,drive = <VALUE_DRV_DEFAULT>;
519 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
524 rockchip,pins = <I2S_SCLK>;
525 rockchip,pull = <VALUE_PULL_DISABLE>;
526 rockchip,drive = <VALUE_DRV_DEFAULT>;
527 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
531 i2s_lrckrx:i2s-lrckrx {
532 rockchip,pins = <I2S_LRCKRX>;
533 rockchip,pull = <VALUE_PULL_DISABLE>;
534 rockchip,drive = <VALUE_DRV_DEFAULT>;
535 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
539 i2s_lrcktx:i2s-lrcktx {
540 rockchip,pins = <I2S_LRCKTX>;
541 rockchip,pull = <VALUE_PULL_DISABLE>;
542 rockchip,drive = <VALUE_DRV_DEFAULT>;
543 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
548 rockchip,pins = <I2S_SDO0>;
549 rockchip,pull = <VALUE_PULL_DISABLE>;
550 rockchip,drive = <VALUE_DRV_DEFAULT>;
551 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
556 rockchip,pins = <I2S_SDO1>;
557 rockchip,pull = <VALUE_PULL_DISABLE>;
558 rockchip,drive = <VALUE_DRV_DEFAULT>;
559 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
564 rockchip,pins = <I2S_SDO2>;
565 rockchip,pull = <VALUE_PULL_DISABLE>;
566 rockchip,drive = <VALUE_DRV_DEFAULT>;
567 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
572 rockchip,pins = <I2S_SDO3>;
573 rockchip,pull = <VALUE_PULL_DISABLE>;
574 rockchip,drive = <VALUE_DRV_DEFAULT>;
575 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
580 rockchip,pins = <I2S_SDI>;
581 rockchip,pull = <VALUE_PULL_DISABLE>;
582 rockchip,drive = <VALUE_DRV_DEFAULT>;
583 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
588 rockchip,pins = <FUNC_TO_GPIO(I2S_CLK)>,
589 <FUNC_TO_GPIO(I2S_SCLK)>,
590 <FUNC_TO_GPIO(I2S_LRCKRX)>,
591 <FUNC_TO_GPIO(I2S_LRCKTX)>,
592 <FUNC_TO_GPIO(I2S_SDO0)>,
593 <FUNC_TO_GPIO(I2S_SDO1)>,
594 <FUNC_TO_GPIO(I2S_SDO2)>,
595 <FUNC_TO_GPIO(I2S_SDO3)>,
596 <FUNC_TO_GPIO(I2S_SDI)>;
598 rockchip,drive = <VALUE_DRV_DEFAULT>;
603 lcdc0_lcdc:lcdc0-lcdc {
607 <LCDC0_HSYNC_GPIO1D>,
608 <LCDC0_VSYNC_GPIO1D>;
609 rockchip,pull = <VALUE_PULL_DISABLE>;
610 rockchip,drive = <VALUE_DRV_DEFAULT>;
613 lcdc0_gpio:lcdc0-gpio {
615 <FUNC_TO_GPIO(LCDC0_DCLK_GPIO1D)>,
616 <FUNC_TO_GPIO(LCDC0_DEN_GPIO1D)>,
617 <FUNC_TO_GPIO(LCDC0_HSYNC_GPIO1D)>,
618 <FUNC_TO_GPIO(LCDC0_VSYNC_GPIO1D)>;
619 rockchip,pull = <VALUE_PULL_DISABLE>;
620 rockchip,drive = <VALUE_DRV_DEFAULT>;
628 rockchip,pins = <SPDIF_TX>;
629 rockchip,pull = <VALUE_PULL_DISABLE>;
630 rockchip,drive = <VALUE_DRV_DEFAULT>;
631 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
637 vop0_pwm_pin:vop0-pwm {
638 rockchip,pins = <VOP0_PWM>;
639 rockchip,pull = <VALUE_PULL_DISABLE>;
640 rockchip,drive = <VALUE_DRV_DEFAULT>;
641 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
645 vop1_pwm_pin:vop1-pwm {
646 rockchip,pins = <VOP1_PWM>;
647 rockchip,pull = <VALUE_PULL_DISABLE>;
648 rockchip,drive = <VALUE_DRV_DEFAULT>;
649 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
653 rockchip,pins = <PWM0>;
654 rockchip,pull = <VALUE_PULL_DISABLE>;
655 rockchip,drive = <VALUE_DRV_DEFAULT>;
656 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
662 rockchip,pins = <PWM1>;
663 rockchip,pull = <VALUE_PULL_DISABLE>;
664 rockchip,drive = <VALUE_DRV_DEFAULT>;
665 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
670 rockchip,pins = <PWM2>;
671 rockchip,pull = <VALUE_PULL_DISABLE>;
672 rockchip,drive = <VALUE_DRV_DEFAULT>;
673 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
678 rockchip,pins = <PWM3>;
679 rockchip,pull = <VALUE_PULL_DISABLE>;
680 rockchip,drive = <VALUE_DRV_DEFAULT>;
681 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
687 emmc0_clk: emmc0-clk {
688 rockchip,pins = <EMMC_CLKOUT>;
689 rockchip,pull = <VALUE_PULL_DISABLE>;
690 rockchip,drive = <VALUE_DRV_DEFAULT>;
691 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
694 emmc0_cmd: emmc0-cmd {
695 rockchip,pins = <EMMC_CMD>;
696 rockchip,pull = <VALUE_PULL_UP>;
697 rockchip,drive = <VALUE_DRV_DEFAULT>;
698 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
701 emmc0_rstnout: emmc0-rstnout {
702 rockchip,pins = <EMMC_RSTNOUT>;
703 rockchip,pull = <VALUE_PULL_UP>;
704 rockchip,drive = <VALUE_DRV_DEFAULT>;
705 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
709 emmc0_pwr: emmc0-pwr {
710 rockchip,pins = <EMMC_PWREN>;
711 rockchip,pull = <VALUE_PULL_DISABLE>;
712 rockchip,drive = <VALUE_DRV_DEFAULT>;
713 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
716 emmc0_bus1: emmc0-bus-width1 {
717 rockchip,pins = <EMMC_DATA0>;
718 rockchip,pull = <VALUE_PULL_UP>;
719 rockchip,drive = <VALUE_DRV_DEFAULT>;
720 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
723 emmc0_bus4: emmc0-bus-width4 {
724 rockchip,pins = <EMMC_DATA0>,
728 rockchip,pull = <VALUE_PULL_UP>;
729 rockchip,drive = <VALUE_DRV_DEFAULT>;
730 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
736 sdmmc0_clk: sdmmc0-clk {
737 rockchip,pins = <SDMMC0_CLKOUT>;
738 rockchip,pull = <VALUE_PULL_DISABLE>;
739 rockchip,drive = <VALUE_DRV_DEFAULT>;
740 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
743 sdmmc0_cmd: sdmmc0-cmd {
744 rockchip,pins = <SDMMC0_CMD>;
745 rockchip,pull = <VALUE_PULL_UP>;
746 rockchip,drive = <VALUE_DRV_DEFAULT>;
747 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
750 sdmmc0_dectn: sdmmc0-dectn{
751 rockchip,pins = <SDMMC0_DECTN>;
752 rockchip,pull = <VALUE_PULL_UP>;
753 rockchip,drive = <VALUE_DRV_DEFAULT>;
754 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
758 sdmmc0_bus1: sdmmc0-bus-width1 {
759 rockchip,pins = <SDMMC0_DATA0>;
760 rockchip,pull = <VALUE_PULL_UP>;
761 rockchip,drive = <VALUE_DRV_DEFAULT>;
762 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
765 sdmmc0_bus4: sdmmc0-bus-width4 {
766 rockchip,pins = <SDMMC0_DATA0>,
770 rockchip,pull = <VALUE_PULL_UP>;
771 rockchip,drive = <VALUE_DRV_DEFAULT>;
772 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
775 sdmmc0_gpio: sdmmc0_gpio{
784 rockchip,pull = <VALUE_PULL_UP>;
785 rockchip,drive = <VALUE_DRV_DEFAULT>;
786 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
793 sdio0_clk: sdio0_clk {
794 rockchip,pins = <SDIO0_CLKOUT>;
795 rockchip,pull = <VALUE_PULL_DISABLE>;
796 rockchip,drive = <VALUE_DRV_DEFAULT>;
797 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
800 sdio0_cmd: sdio0_cmd {
801 rockchip,pins = <SDIO0_CMD>;
802 rockchip,pull = <VALUE_PULL_UP>;
803 rockchip,drive = <VALUE_DRV_DEFAULT>;
804 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
807 sdio0_dectn: sdio0-dectn{
808 rockchip,pins = <SDIO0_DETECTN>;
809 rockchip,pull = <VALUE_PULL_UP>;
810 rockchip,drive = <VALUE_DRV_DEFAULT>;
811 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
814 sdio0_wrprt: sdio0_wrprt{
815 rockchip,pins = <SDIO0_WRPRT>;
816 rockchip,pull = <VALUE_PULL_UP>;
817 rockchip,drive = <VALUE_DRV_DEFAULT>;
818 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
821 sdio0_pwr: sdio0-pwren{
822 rockchip,pins = <SDIO0_PWREN>;
823 rockchip,pull = <VALUE_PULL_UP>;
824 rockchip,drive = <VALUE_DRV_DEFAULT>;
825 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
828 sdio0_bkpwr: sdio0-bkpwr{
829 rockchip,pins = <SDIO0_BKPWR>;
830 rockchip,pull = <VALUE_PULL_UP>;
831 rockchip,drive = <VALUE_DRV_DEFAULT>;
832 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
835 sdio0_intn: sdio0-intn{
836 rockchip,pins = <SDIO0_INTN>;
837 rockchip,pull = <VALUE_PULL_UP>;
838 rockchip,drive = <VALUE_DRV_DEFAULT>;
839 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
843 sdio0_bus1: sdio0-bus-width1 {
844 rockchip,pins = <SDIO0_DATA0>;
845 rockchip,pull = <VALUE_PULL_UP>;
846 rockchip,drive = <VALUE_DRV_DEFAULT>;
847 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
850 sdio0_bus4: sdio0-bus-width4 {
851 rockchip,pins = <SDIO0_DATA0>,
855 rockchip,pull = <VALUE_PULL_UP>;
856 rockchip,drive = <VALUE_DRV_DEFAULT>;
857 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
860 sdio0_gpio: sdio0-all-gpio{
873 rockchip,pull = <VALUE_PULL_UP>;
874 rockchip,drive = <VALUE_DRV_DEFAULT>;
875 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
881 rockchip,pins = <GPS_MAG>;
882 rockchip,pull = <VALUE_PULL_DISABLE>;
883 rockchip,drive = <VALUE_DRV_DEFAULT>;
884 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
889 rockchip,pins = <GPS_SIG>;
890 rockchip,pull = <VALUE_PULL_DISABLE>;
891 rockchip,drive = <VALUE_DRV_DEFAULT>;
892 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
897 gps_rfclk:gps-rfclk {
898 rockchip,pins = <GPS_RFCLK>;
899 rockchip,pull = <VALUE_PULL_DISABLE>;
900 rockchip,drive = <VALUE_DRV_DEFAULT>;
901 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
909 rockchip,pins = <MAC_CLK>;
910 rockchip,pull = <VALUE_PULL_DISABLE>;
911 rockchip,drive = <VALUE_DRV_DEFAULT>;
912 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
915 mac_txpins: mac-txpins {
916 rockchip,pins = <MAC_TXD0>, <MAC_TXD1>, <MAC_TXD2>, <MAC_TXD3>, <MAC_TXEN>, <MAC_TXCLK>;
917 rockchip,pull = <VALUE_PULL_DISABLE>;
918 rockchip,drive = <VALUE_DRV_DEFAULT>;
919 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
922 mac_rxpins: mac-rxpins {
923 rockchip,pins = <MAC_RXD0>, <MAC_RXD1>, <MAC_RXD2>, <MAC_RXD3>, <MAC_RXDV>, <MAC_RXER>, <MAC_RXCLK>, <MAC_COL>;
924 rockchip,pull = <VALUE_PULL_DISABLE>;
925 rockchip,drive = <VALUE_DRV_DEFAULT>;
926 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
930 rockchip,pins = <MAC_CRS>;
931 rockchip,pull = <VALUE_PULL_DISABLE>;
932 rockchip,drive = <VALUE_DRV_DEFAULT>;
933 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
936 mac_mdpins: mac-mdpins {
937 rockchip,pins = <MAC_MDIO>, <MAC_MDC>;
938 rockchip,pull = <VALUE_PULL_DISABLE>;
939 rockchip,drive = <VALUE_DRV_DEFAULT>;
940 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
944 gpio0_tsadc: gpio0-tsadc {
945 tsadc_int: tsadc-int {
946 rockchip,pins = <TSADC_INT>;
947 rockchip,pull = <VALUE_PULL_DISABLE>;
949 tsadc_gpio: tsadc-gpio {
950 rockchip,pins = <GPIO0_B2>;
951 rockchip,pull = <VALUE_PULL_DISABLE>;
961 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_LCDC_VCC>;
962 rockchip,voltage = <VALUE_VOL_DEFAULT>;
966 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_DVP_VCC>;
967 rockchip,voltage = <VALUE_VOL_DEFAULT>;
970 flash0_vcc:flash0-vcc {
971 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH0_VCC>;
972 rockchip,voltage = <VALUE_VOL_DEFAULT>;
975 flash1_vcc:flash1-vcc {
976 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH1_VCC>;
977 rockchip,voltage = <VALUE_VOL_DEFAULT>;
981 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_WIFI_VCC>;
982 rockchip,voltage = <VALUE_VOL_DEFAULT>;
986 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_BB_VCC>;
987 rockchip,voltage = <VALUE_VOL_DEFAULT>;
990 audio_vcc:audio-vcc {
991 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_AUDIO_VCC>;
992 rockchip,voltage = <VALUE_VOL_DEFAULT>;
995 sdcard_vcc:sdcard-vcc {
996 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_SDCARD_VCC>;
997 rockchip,voltage = <VALUE_VOL_DEFAULT>;
1000 gpio30_vcc:gpio30-vcc {
1001 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO30_VCC>;
1002 rockchip,voltage = <VALUE_VOL_DEFAULT>;
1005 gpio1830_vcc:gpio1830-vcc {
1006 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO1830_VCC>;
1007 rockchip,voltage = <VALUE_VOL_DEFAULT>;
1013 lcdc_vcc_18:lcdc-vcc-18 {
1014 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_LCDC_VCC>;
1015 rockchip,voltage = <VALUE_VOL_1V8>;
1018 dvp_vcc_18:dvp-vcc-18 {
1019 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_DVP_VCC>;
1020 rockchip,voltage = <VALUE_VOL_1V8>;
1023 flash0_vcc_18:flash0-vcc-18 {
1024 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH0_VCC>;
1025 rockchip,voltage = <VALUE_VOL_1V8>;
1028 flash1_vcc_18:flash1-vcc-18 {
1029 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH1_VCC>;
1030 rockchip,voltage = <VALUE_VOL_1V8>;
1033 wifi_vcc_18:wifi-vcc-18 {
1034 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_WIFI_VCC>;
1035 rockchip,voltage = <VALUE_VOL_1V8>;
1038 bb_vcc_18:bb-vcc-18 {
1039 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_BB_VCC>;
1040 rockchip,voltage = <VALUE_VOL_1V8>;
1043 audio_vcc_18:audio-vcc-18 {
1044 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_AUDIO_VCC>;
1045 rockchip,voltage = <VALUE_VOL_1V8>;
1048 sdcard_vcc_18:sdcard-vcc-18 {
1049 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_SDCARD_VCC>;
1050 rockchip,voltage = <VALUE_VOL_1V8>;
1053 gpio30_vcc_18:gpio30-vcc-18 {
1054 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO30_VCC>;
1055 rockchip,voltage = <VALUE_VOL_1V8>;
1058 gpio1830_vcc_18:gpio1830-vcc-18 {
1059 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO1830_VCC>;
1060 rockchip,voltage = <VALUE_VOL_1V8>;
1067 lcdc_vcc_33:lcdc-vcc-33 {
1068 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_LCDC_VCC>;
1069 rockchip,voltage = <VALUE_VOL_3V3>;
1072 dvp_vcc_33:dvp-vcc-33 {
1073 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_DVP_VCC>;
1074 rockchip,voltage = <VALUE_VOL_3V3>;
1077 flash0_vcc_33:flash0-vcc-33 {
1078 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH0_VCC>;
1079 rockchip,voltage = <VALUE_VOL_3V3>;
1082 flash1_vcc_33:flash1-vcc-33 {
1083 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_FLASH1_VCC>;
1084 rockchip,voltage = <VALUE_VOL_3V3>;
1087 wifi_vcc_33:wifi-vcc-33 {
1088 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_WIFI_VCC>;
1089 rockchip,voltage = <VALUE_VOL_3V3>;
1092 bb_vcc_33:bb-vcc-33 {
1093 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_BB_VCC>;
1094 rockchip,voltage = <VALUE_VOL_3V3>;
1097 audio_vcc_33:audio-vcc-33 {
1098 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_AUDIO_VCC>;
1099 rockchip,voltage = <VALUE_VOL_3V3>;
1102 sdcard_vcc_33:sdcard-vcc-33 {
1103 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_SDCARD_VCC>;
1104 rockchip,voltage = <VALUE_VOL_3V3>;
1107 gpio30_vcc_33:gpio30-vcc-33 {
1108 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO30_VCC>;
1109 rockchip,voltage = <VALUE_VOL_3V3>;
1112 gpio1830_vcc_33:gpio1830-vcc-33 {
1113 rockchip,pins = <RK32_VIRTUAL_PIN_FOR_GPIO1830_VCC>;
1114 rockchip,voltage = <VALUE_VOL_3V3>;
1123 rockchip,pins = <CIF_CLKOUT>;
1124 rockchip,pull = <VALUE_PULL_DISABLE>;
1125 rockchip,drive = <VALUE_DRV_DEFAULT>;
1126 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
1128 isp_dvp_d2d9:isp_dvp_d2d9 {
1129 rockchip,pins = <CIF_DATA2>,<CIF_DATA3>,
1130 <CIF_DATA4>,<CIF_DATA5>,
1131 <CIF_DATA6>,<CIF_DATA7>,
1132 <CIF_DATA8>,<CIF_DATA9>,
1133 <CIF_VSYNC>,<CIF_HREF>,
1134 <CIF_CLKIN>,<CIF_CLKOUT>;
1135 rockchip,pull = <VALUE_PULL_DISABLE>;
1136 rockchip,drive = <VALUE_DRV_DEFAULT>;
1137 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
1141 isp_dvp_d0d1:isp_d0d1 {
1142 rockchip,pins = <CIF_DATA0>,<CIF_DATA1>;
1143 rockchip,pull = <VALUE_PULL_DISABLE>;
1144 rockchip,drive = <VALUE_DRV_DEFAULT>;
1145 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
1148 isp_dvp_d10d11:isp_d10d11 {
1149 rockchip,pins = <CIF_DATA10>,<CIF_DATA11>;
1150 rockchip,pull = <VALUE_PULL_DISABLE>;
1151 rockchip,drive = <VALUE_DRV_DEFAULT>;
1152 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
1155 isp_dvp_d0d7:isp_d0d7 {
1156 rockchip,pins = <CIF_DATA0>,<CIF_DATA1>,
1157 <CIF_DATA2>,<CIF_DATA3>,
1158 <CIF_DATA4>,<CIF_DATA5>,
1159 <CIF_DATA6>,<CIF_DATA7>;
1160 rockchip,pull = <VALUE_PULL_DISABLE>;
1161 rockchip,drive = <VALUE_DRV_DEFAULT>;
1162 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
1165 isp_shutter:isp_shutter {
1166 rockchip,pins = <ISP_SHUTTEREN>,<ISP_SHUTTERTRIG>;
1167 rockchip,pull = <VALUE_PULL_DISABLE>;
1168 rockchip,drive = <VALUE_DRV_DEFAULT>;
1169 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
1172 isp_flash_trigger:isp_flash_trigger {
1173 rockchip,pins = <ISP_FLASHTRIGOUTSPI1_CS0>;
1174 rockchip,pull = <VALUE_PULL_DISABLE>;
1175 rockchip,drive = <VALUE_DRV_DEFAULT>;
1176 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
1179 isp_prelight:isp_prelight {
1180 rockchip,pins = <ISP_PRELIGHTTRIGSPI1_RXD>;
1181 rockchip,pull = <VALUE_PULL_DISABLE>;
1182 rockchip,drive = <VALUE_DRV_DEFAULT>;
1183 //rockchip,tristate = <VALUE_TRI_DEFAULT>;
1185 isp_flash_trigger_as_gpio:isp_flash_trigger_as_gpio {
1186 rockchip,pins = <FUNC_TO_GPIO(ISP_FLASHTRIGOUTSPI1_CS0)>;
1187 rockchip,pull = <VALUE_PULL_DISABLE>;
1188 rockchip,drive = <VALUE_DRV_DEFAULT>;
1189 //rockchip,tristate = <VALUE_TRI_DEFAULT>;