3 #include <dt-bindings/clock/ddr.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/rkfb/rk_fb.h>
6 #include <dt-bindings/suspend/rockchip-pm.h>
7 #include <dt-bindings/sensor-dev.h>
9 #include "skeleton.dtsi"
10 #include "rk3288-pinctrl.dtsi"
13 interrupt-parent = <&gic>;
33 compatible = "arm,cortex-a15";
38 compatible = "arm,cortex-a15";
43 compatible = "arm,cortex-a15";
48 compatible = "arm,cortex-a15";
53 gic: interrupt-controller@ffc01000 {
54 compatible = "arm,cortex-a15-gic";
56 #interrupt-cells = <3>;
58 reg = <0xffc01000 0x1000>,
63 compatible = "mmio-sram";
64 reg = <0xff710000 0x8000>; /* 32k */
69 compatible = "arm,armv7-timer";
70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
74 clock-frequency = <24000000>;
78 compatible = "rockchip,timer";
79 reg = <0xff810000 0x20>;
80 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
81 rockchip,broadcast = <1>;
85 compatible = "rockchip,timer";
86 reg = <0xff810020 0x20>;
87 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
88 rockchip,clocksource = <1>;
89 rockchip,count-up = <1>;
92 uart_dbg: serial@ff690000 {
93 compatible = "rockchip,serial";
94 reg = <0xff690000 0x100>;
95 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
96 clock-frequency = <24000000>;
103 compatible = "rockchip,fiq-debugger";
104 rockchip,serial-id = <2>;
105 rockchip,signal-irq = <106>;
106 rockchip,wake-irq = <0>;
111 compatible = "rockchip,rk30-i2c";
112 reg = <0xff650000 0x1000>;
113 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
114 #address-cells = <1>;
116 rockchip,check-idle = <0>;
121 compatible = "rockchip,rk30-i2c";
122 reg = <0xff140000 0x1000>;
123 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
124 #address-cells = <1>;
126 rockchip,check-idle = <0>;
131 compatible = "rockchip,rk30-i2c";
132 reg = <0xff660000 0x1000>;
133 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
134 #address-cells = <1>;
136 rockchip,check-idle = <0>;
141 compatible = "rockchip,rk30-i2c";
142 reg = <0xff150000 0x1000>;
143 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
144 #address-cells = <1>;
146 rockchip,check-idle = <0>;
151 compatible = "rockchip,rk30-i2c";
152 reg = <0xff160000 0x1000>;
153 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
154 #address-cells = <1>;
156 rockchip,check-idle = <0>;
161 compatible = "rockchip,rk30-i2c";
162 reg = <0xff170000 0x1000>;
163 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
164 #address-cells = <1>;
166 rockchip,check-idle = <0>;
170 lvds: lvds@ff96c000 {
171 compatible = "rockchip, rk32-lvds";
172 reg = <0xff960000 0x20000>;
176 compatible = "rockchip,rk32-edp";
177 reg = <0xff970000 0x4000>;
178 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
181 hdmi: hdmi@ff980000 {
182 compatible = "rockchip,rk3288-hdmi";
183 reg = <0xff980000 0x20000>;
184 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
185 rockchip,hdmi_lcdc_source = <1>;
186 pinctrl-names = "default", "gpio";
187 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
188 pinctrl-1 = <&i2c5_gpio>;
193 compatible = "rockchip,rk-fb";
194 rockchip,disp-mode = <DUAL>;
197 rk_screen: rk_screen{
198 compatible = "rockchip,screen";
201 lcdc1: lcdc@ff940000 {
202 compatible = "rockchip,rk3288-lcdc";
203 rockchip,prop = <PRMRY>;
204 rochchip,pwr18 = <0>;
205 reg = <0xff940000 0x10000>;
206 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
207 pinctrl-names = "default", "gpio";
208 pinctrl-0 = <&lcdc0_lcdc>;
209 pinctrl-1 = <&lcdc0_gpio>;
213 lcdc0: lcdc@ff930000 {
214 compatible = "rockchip,rk3288-lcdc";
215 rockchip,prop = <EXTEND>;
216 rockchip,pwr18 = <0>;
217 reg = <0xff930000 0x10000>;
218 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
219 //pinctrl-names = "default", "gpio";
220 //pinctrl-0 = <&lcdc0_lcdc>;
221 //pinctrl-1 = <&lcdc0_gpio>;
226 compatible = "rockchip,saradc";
227 reg = <0xff100000 0x100>;
228 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
229 #io-channel-cells = <1>;
231 rockchip,adc-vref = <1800>;
232 clock-frequency = <1000000>;
233 clock-names = "saradc", "pclk_saradc";
238 compatible = "rockchip,rga";
239 reg = <0xff920000 0x1000>;
240 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
241 clock-names = "hclk_rga", "aclk_rga";
244 i2s: rockchip-i2s@0xff890000 {
245 compatible = "rockchip-i2s";
246 reg = <0xff890000 0x10000>;
248 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
249 // dmas = <&pdma0 0>,
252 // dma-names = "tx", "rx";
255 spdif: rockchip-spdif@0xff8b0000 {
256 compatible = "rockchip-spdif";
257 reg = <0xff8b0000 0x10000>; //8channel
258 //reg = <ff880000 0x2000>;//2channel
259 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
260 // dmas = <&pdma0 8>;
265 compatible = "rockchip,ion";
266 #address-cells = <1>;
268 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
269 compatible = "rockchip,ion-heap";
270 rockchip,ion_heap = <4>;
271 reg = <0x00000000 0x04000000>; /* 64MB */
273 rockchip,ion-heap@0 { /* VMALLOC HEAP */
274 compatible = "rockchip,ion-heap";
275 rockchip,ion_heap = <0>;
280 compatible = "rockchip,rk_mmc";
281 reg = <0xff0c0000 0x4000>;
282 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
283 #address-cells = <1>;
285 clock-frequency = <50000000>;
286 clock-freq-min-max = <400000 50000000>;
290 card-detect-delay = <200>;
291 pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
292 fifo-depth = <0x100>;
293 emmc-compatible = <0>;
297 sdio0: mshc@ff0d0000 {
298 compatible = "rockchip,rk_mmc";
299 reg = <0xff0d0000 0x4000>;
300 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; /*irq=65*/
301 #address-cells = <1>;
303 clock-frequency = <50000000>;
304 clock-freq-min-max = <400000 50000000>;
307 fifo-depth = <0x100>;
308 emmc-compatible = <0>;
312 sdio1: mshc@ff0e0000 {
313 compatible = "rockchip,rk_mmc";
314 reg = <0xff0e0000 0x4000>;
315 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; /*irq=66*/
316 #address-cells = <1>;
318 clock-frequency = <50000000>;
319 clock-freq-min-max = <400000 50000000>;
322 fifo-depth = <0x100>;
323 emmc-compatible = <0>;
327 emmc: mshc@ff0f0000 {
328 compatible = "rockchip,rk_mmc";
329 reg = <0xff0f0000 0x4000>;
330 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; /*irq=67*/
331 #address-cells = <1>;
333 clock-frequency = <50000000>;
334 clock-freq-min-max = <400000 50000000>;
337 fifo-depth = <0x100>;
338 emmc-compatible = <1>;
342 vpu: vpu_service@ff9a0000 {
343 compatible = "vpu_service";
344 reg = <0xff9a0000 0x800>;
345 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
346 interrupt-names = "irq_enc", "irq_dec";
347 name = "vpu_service";
351 hevc: hevc_service@ff9c0000 {
352 compatible = "rockchip,hevc_service";
353 reg = <0xff9c0000 0x800>;
354 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
355 interrupt-names = "irq_dec";
356 name = "hevc_service";
361 compatible = "rockchip,iep";
362 reg = <0xff900000 0x800>;
363 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
367 dwc_control_usb: dwc-control-usb@ff770284 {
368 compatible = "rockchip,rk3288-dwc-control-usb";
369 reg = <0xff770284 0x04>, <0xff770288 0x04>,
370 <0xff7702cc 0x04>, <0xff7702d4 0x04>,
371 <0xff770320 0x14>, <0xff770334 0x14>,
372 <0xff770348 0x10>, <0xff770358 0x08>,
374 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
375 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
376 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
377 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
379 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
382 interrupt-names = "otg_id", "bvalid",
383 "otg_linestate", "host0_linestate",
385 /*gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,*//*HOST_VBUS_DRV*/
386 /* <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
387 /*clocks = <&clk_gates4 5>;*/
388 /*clock-names = "hclk_usb_peri";*/
392 compatible = "rockchip,rk3288_usb20_otg";
393 reg = <0xff580000 0x40000>;
394 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
398 compatible = "rockchip,rk3288_usb20_host";
399 reg = <0xff540000 0x40000>;
400 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
404 compatible = "rockchip,rk3288_rk_ohci_host";
405 reg = <0xff520000 0x20000>;
406 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
410 compatible = "rockchip,rk3288_rk_ehci_host";
411 reg = <0xff500000 0x20000>;
412 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
416 compatible = "rockchip,rk3288_rk_ehci1_host";
417 reg = <0xff5c0000 0x40000>;
418 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
422 compatible = "rockchip,gmac";
423 reg = <0xff290000 0x10000>;
424 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
425 interrupt-names = "macirq";
428 pinctrl-names = "default";
429 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
433 #include "lcd-td043mgeal.dtsi"
436 compatible = "rockchip,rk3288-fpga";
439 device_type = "memory";
440 reg = <0x00000000 0x10000000>;
444 bootargs = "androidboot.console=ttyFIQ0 initrd=0x02000000,0x00800000";
452 compatible = "rockchip-rt5631";
455 codec-name = "rt5631.0-001a";
456 cpu-dai-name = "rockchip-i2s.0";
459 //bitclock-inversion;
468 compatible = "rockchip-rk610";
471 codec-name = "rk610_codec.0-0060";
472 cpu-dai-name = "rockchip-i2s.0";
475 //bitclock-inversion;
484 compatible = "hdmi-spdif";
488 compatible = "hdmi-i2s";
492 compatible = "hdmi-spdif";
499 compatible = "rt5631";
504 compatible = "rk610_ctl";
506 rk610-reset-io = <&gpio3 GPIO_B2 GPIO_ACTIVE_HIGH>;
507 // clocks = <&clk_i2s>;
508 // clock-names = "i2s_clk";
511 rk610codec@60 {//RK610_CODEC addr from 0x60 to 0x80 (0x60~0x80)
512 compatible = "rk610_codec";
514 spk_ctl_io = <&gpio2 GPIO_D7 GPIO_ACTIVE_HIGH>;
516 pa_enable_time = <1000>;
520 compatible = "rockchip,ion";
521 #address-cells = <1>;
523 rockchip,ion-heap@1 { /* CMA HEAP */
524 compatible = "rockchip,ion-reserve";
526 memory-reservation = <0x00000000 0x04000000>; /* 64MB */
528 rockchip,ion-heap@3 { /* SYSTEM HEAP */
535 rockchip,disp-mode = <DUAL>;
539 display-timings = <&disp_timings>;
544 power_ctr: power_ctr {
545 rockchip,debug = <0>;
546 rockchip,mirror = <NO_MIRROR>;
548 rockchip,power_type = <GPIO>;
549 gpios = <&gpio7 GPIO_A3 GPIO_ACTIVE_HIGH>;
550 rockchip,delay = <10>;
555 rockchip,power_type = <REGULATOR>;
556 rockchip,delay = <10>;
560 rockchip,power_type = <GPIO>;
561 gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
562 rockchip,delay = <5>;
574 rockchips,hdmi_audio_source = <0>;