arch/arm/boot/dts/rk3288-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3288.h>
  15
  16 /{
  17         clocks {
  18                 compatible = "rockchip,rk-clocks";
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges = <0x0 0xFF760000 0x01b0>;
  22
  23                 xin24m: xin24m {
  24                         compatible = "fixed-clock";
  25                         #clock-cells = <0>;
  26                         clock-output-names = "xin24m";
  27                         clock-frequency = <24000000>;
  28                 };
  29
  30                 xin12m: xin12m {
  31                         compatible = "fixed-clock";
  32                         #clock-cells = <0>;
  33                         clocks = <&xin24m>;
  34                         clock-output-names = "xin12m";
  35                         clock-frequency = <12000000>;
  36                 };
  37
  38                 xin32k: xin32k {
  39                         compatible = "fixed-clock";
  40                         #clock-cells = <0>;
  41                         clock-output-names = "xin32k";
  42                         clock-frequency = <32000>;
  43                 };
  44
  45                 io_27m_in: io_27m_in {
  46                         compatible = "fixed-clock";
  47                         #clock-cells = <0>;
  48                         clock-output-names = "io_27m_in";
  49                         clock-frequency = <27000000>;
  50                 };
  51
  52                 dummy: dummy {
  53                         compatible = "fixed-clock";
  54                         #clock-cells = <0>;
  55                         clock-frequency = <0>;
  56                 };
  57
  58                 i2s_clkin: i2s_clkin {
  59                         compatible = "fixed-clock";
  60                         #clock-cells = <0>;
  61                         clock-output-names = "i2s_clkin";
  62                         clock-frequency = <0>;
  63                 };
  64
  65                 edp_24m_clkin: edp_24m_clkin {
  66                         compatible = "fixed-clock";
  67                         #clock-cells = <0>;
  68                         clock-output-names = "edp_24m_clkin";
  69                         clock-frequency = <0>;
  70                 };
  71
  72                 gmac_clkin: gmac_clkin {
  73                         compatible = "fixed-clock";
  74                         #clock-cells = <0>;
  75                         clock-output-names = "gmac_clkin";
  76                         clock-frequency = <0>;
  77                 };
  78
  79                 clk_hsadc_ext: clk_hsadc_ext {
  80                         compatible = "fixed-clock";
  81                         #clock-cells = <0>;
  82                         clock-output-names = "clk_hsadc_ext";
  83                         clock-frequency = <0>;
  84                 };
  85
  86                 jtag_clkin: jtag_clkin {
  87                         compatible = "fixed-clock";
  88                         #clock-cells = <0>;
  89                         clock-output-names = "jtag_clkin";
  90                         clock-frequency = <0>;
  91                 };
  92
  93                 pclkin_cif: pclkin_cif {
  94                         compatible = "fixed-clock";
  95                         #clock-cells = <0>;
  96                         clock-output-names = "pclkin_cif";
  97                         clock-frequency = <0>;
  98                 };
  99
 100                 pclkin_isp: pclkin_isp {
 101                         compatible = "fixed-clock";
 102                         #clock-cells = <0>;
 103                         clock-output-names = "pclkin_isp";
 104                         clock-frequency = <0>;
 105                 };
 106
 107                 clk_otgphy0_480m: clk_otgphy0_480m {
 108                         compatible = "fixed-factor-clock";
 109                         clocks = <&clk_gates13 4>;
 110                         clock-output-names = "clk_otgphy0_480m";
 111                         clock-div = <1>;
 112                         clock-mult = <20>;
 113                         #clock-cells = <0>;
 114                 };
 115
 116                 clk_otgphy1_480m: clk_otgphy1_480m {
 117                         compatible = "fixed-factor-clock";
 118                         clocks = <&clk_gates13 5>;
 119                         clock-output-names = "clk_otgphy1_480m";
 120                         clock-div = <1>;
 121                         clock-mult = <20>;
 122                         #clock-cells = <0>;
 123                 };
 124
 125                 clk_otgphy2_480m: clk_otgphy2_480m {
 126                         compatible = "fixed-factor-clock";
 127                         clocks = <&clk_gates13 6>;
 128                         clock-output-names = "clk_otgphy2_480m";
 129                         clock-div = <1>;
 130                         clock-mult = <20>;
 131                         #clock-cells = <0>;
 132                 };
 133
 134                 clk_hsadc_inv: clk_hsadc_inv {
 135                         compatible = "fixed-factor-clock";
 136                         clocks = <&clk_hsadc_out>;
 137                         clock-output-names = "clk_hsadc_inv";
 138                         clock-div = <1>;
 139                         clock-mult = <1>;
 140                         #clock-cells = <0>;
 141                 };
 142
 143                 pclkin_cif_inv: pclkin_cif_inv {
 144                         compatible = "fixed-factor-clock";
 145                         clocks = <&clk_gates16 0>;
 146                         clock-output-names = "pclkin_cif_inv";
 147                         clock-div = <1>;
 148                         clock-mult = <1>;
 149                         #clock-cells = <0>;
 150                 };
 151
 152                 pclkin_isp_inv: pclkin_isp_inv {
 153                         compatible = "fixed-factor-clock";
 154                         clocks = <&clk_gates16 3>;
 155                         clock-output-names = "pclkin_isp_inv";
 156                         clock-div = <1>;
 157                         clock-mult = <1>;
 158                         #clock-cells = <0>;
 159                 };
 160
 161                 hclk_vepu: hclk_vepu {
 162                         compatible = "fixed-factor-clock";
 163                         clocks = <&clk_vepu>;
 164                         clock-output-names = "hclk_vepu";
 165                         clock-div = <4>;
 166                         clock-mult = <1>;
 167                         #clock-cells = <0>;
 168                 };
 169
 170                 hclk_vdpu: hclk_vdpu {
 171                         compatible = "fixed-factor-clock";
 172                         clocks = <&clk_vdpu>;
 173                         clock-output-names = "hclk_vdpu";
 174                         clock-div = <4>;
 175                         clock-mult = <1>;
 176                         #clock-cells = <0>;
 177                 };
 178
 179                 clock_regs {
 180                         compatible = "rockchip,rk-clock-regs";
 181                         #address-cells = <1>;
 182                         #size-cells = <1>;
 183                         ranges;
 184
 185                         /* PLL control regs */
 186                         pll_cons {
 187                                 compatible = "rockchip,rk-pll-cons";
 188                                 #address-cells = <1>;
 189                                 #size-cells = <1>;
 190                                 ranges ;
 191
 192                                 clk_apll: pll-clk@0000 {
 193                                         compatible = "rockchip,rk3188-pll-clk";
 194                                         reg = <0x0000 0x10>;
 195                                         mode-reg = <0x0050 0>;
 196                                         status-reg = <0x0284 6>;
 197                                         clocks = <&xin24m>;
 198                                         clock-output-names = "clk_apll";
 199                                         rockchip,pll-type = <CLK_PLL_3288_APLL>;
 200                                         #clock-cells = <0>;
 201                                 };
 202
 203                                 clk_dpll: pll-clk@0010 {
 204                                         compatible = "rockchip,rk3188-pll-clk";
 205                                         reg = <0x0010 0x10>;
 206                                         mode-reg = <0x0050 4>;
 207                                         status-reg = <0x0284 5>;
 208                                         clocks = <&xin24m>;
 209                                         clock-output-names = "clk_dpll";
 210                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 211                                         #clock-cells = <0>;
 212                                 };
 213
 214                                 clk_cpll: pll-clk@0020 {
 215                                         compatible = "rockchip,rk3188-pll-clk";
 216                                         reg = <0x0020 0x10>;
 217                                         mode-reg = <0x0050 8>;
 218                                         status-reg = <0x0284 7>;
 219                                         clocks = <&xin24m>;
 220                                         clock-output-names = "clk_cpll";
 221                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 222                                         #clock-cells = <0>;
 223                                         #clock-init-cells = <1>;
 224                                 };
 225
 226                                 clk_gpll: pll-clk@0030 {
 227                                         compatible = "rockchip,rk3188-pll-clk";
 228                                         reg = <0x0030 0x10>;
 229                                         mode-reg = <0x0050 12>;
 230                                         status-reg = <0x0284 8>;
 231                                         clocks = <&xin24m>;
 232                                         clock-output-names = "clk_gpll";
 233                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 234                                         #clock-cells = <0>;
 235                                         #clock-init-cells = <1>;
 236                                 };
 237
 238                                 clk_npll: pll-clk@0040 {
 239                                         compatible = "rockchip,rk3188-pll-clk";
 240                                         reg = <0x0040 0x10>;
 241                                         mode-reg = <0x0050 14>;
 242                                         status-reg = <0x0284 9>;
 243                                         clocks = <&xin24m>;
 244                                         clock-output-names = "clk_npll";
 245                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 246                                         #clock-cells = <0>;
 247                                         #clock-init-cells = <1>;
 248                                 };
 249
 250                         };
 251
 252                         /* Select control regs */
 253                         clk_sel_cons {
 254                                 compatible = "rockchip,rk-sel-cons";
 255                                 #address-cells = <1>;
 256                                 #size-cells = <1>;
 257                                 ranges;
 258
 259                                 clk_sel_con0: sel-con@0060 {
 260                                         compatible = "rockchip,rk3188-selcon";
 261                                         reg = <0x0060 0x4>;
 262                                         #address-cells = <1>;
 263                                         #size-cells = <1>;
 264
 265                                         aclk_core_m0: aclk_core_m0_div {
 266                                                 compatible = "rockchip,rk3188-div-con";
 267                                                 rockchip,bits = <0 4>;
 268                                                 clocks = <&clk_core>;
 269                                                 clock-output-names = "aclk_core_m0";
 270                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 271                                                 #clock-cells = <0>;
 272                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 273                                         };
 274
 275                                         aclk_core_mp: aclk_core_mp_div {
 276                                                 compatible = "rockchip,rk3188-div-con";
 277                                                 rockchip,bits = <4 4>;
 278                                                 clocks = <&clk_core>;
 279                                                 clock-output-names = "aclk_core_mp";
 280                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 281                                                 #clock-cells = <0>;
 282                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 283                                         };
 284
 285                                         clk_core_div: clk_core_div {
 286                                                 compatible = "rockchip,rk3188-div-con";
 287                                                 rockchip,bits = <8 5>;
 288                                                 clocks = <&clk_core>;
 289                                                 clock-output-names = "clk_core";
 290                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 291                                                 #clock-cells = <0>;
 292                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 293                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 294                                                                         CLK_SET_RATE_NO_REPARENT)>;
 295                                         };
 296
 297                                         /* reg[14:13]: reserved */
 298
 299                                         clk_core: clk_core_mux {
 300                                                 compatible = "rockchip,rk3188-mux-con";
 301                                                 rockchip,bits = <15 1>;
 302                                                 clocks = <&clk_apll>, <&clk_gates0 2>;
 303                                                 clock-output-names = "clk_core";
 304                                                 #clock-cells = <0>;
 305                                                 #clock-init-cells = <1>;
 306                                         };
 307
 308                                 };
 309
 310                                 clk_sel_con1: sel-con@0064 {
 311                                         compatible = "rockchip,rk3188-selcon";
 312                                         reg = <0x0064 0x4>;
 313                                         #address-cells = <1>;
 314                                         #size-cells = <1>;
 315
 316                                         aclk_bus: aclk_bus_div {
 317                                                 compatible = "rockchip,rk3188-div-con";
 318                                                 rockchip,bits = <0 3>;
 319                                                 clocks = <&aclk_bus_src_div>;
 320                                                 clock-output-names = "aclk_bus";
 321                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 322                                                 #clock-cells = <0>;
 323                                                 #clock-init-cells = <1>;
 324                                         };
 325
 326                                         aclk_bus_src_div: aclk_bus_src_div {
 327                                                 compatible = "rockchip,rk3188-div-con";
 328                                                 rockchip,bits = <3 5>;
 329                                                 clocks = <&aclk_bus_src>;
 330                                                 clock-output-names = "aclk_bus_src";
 331                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 332                                                 #clock-cells = <0>;
 333                                                 rockchip,clkops-idx =
 334                                                         <CLKOPS_RATE_MUX_DIV>;
 335                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 336                                         };
 337
 338                                         hclk_bus: hclk_bus_div {
 339                                                 compatible = "rockchip,rk3188-div-con";
 340                                                 rockchip,bits = <8 2>;
 341                                                 clocks = <&aclk_bus>;
 342                                                 clock-output-names = "hclk_bus";
 343                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 344                                                 rockchip,div-relations =
 345                                                                 <0x0 1
 346                                                                  0x1 2
 347                                                                  0x3 4>;
 348                                                 #clock-cells = <0>;
 349                                                 #clock-init-cells = <1>;
 350                                         };
 351
 352                                         /* reg[11:10]: reserved */
 353
 354                                         pclk_bus: pclk_bus_div {
 355                                                 compatible = "rockchip,rk3188-div-con";
 356                                                 rockchip,bits = <12 3>;
 357                                                 clocks = <&aclk_bus>;
 358                                                 clock-output-names = "pclk_bus";
 359                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 360                                                 #clock-cells = <0>;
 361                                                 #clock-init-cells = <1>;
 362                                         };
 363
 364                                         aclk_bus_src: aclk_bus_src_mux {
 365                                                 compatible = "rockchip,rk3188-mux-con";
 366                                                 rockchip,bits = <15 1>;
 367                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 368                                                 /*clocks = <&clk_gates0 11>, <&clk_gates0 10>; FIXME*/
 369                                                 clock-output-names = "aclk_bus_src";
 370                                                 #clock-cells = <0>;
 371                                                 #clock-init-cells = <1>;
 372                                         };
 373
 374                                 };
 375
 376                                 clk_sel_con2: sel-con@0068 {
 377                                         compatible = "rockchip,rk3188-selcon";
 378                                         reg = <0x0068 0x4>;
 379                                         #address-cells = <1>;
 380                                         #size-cells = <1>;
 381
 382                                         clk_tsadc: clk_tsadc_div {
 383                                                 compatible = "rockchip,rk3188-div-con";
 384                                                 rockchip,bits = <0 6>;
 385                                                 clocks = <&xin32k>;
 386                                                 clock-output-names = "clk_tsadc";
 387                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 388                                                 #clock-cells = <0>;
 389                                         };
 390
 391                                         /* reg[7:6]: reserved */
 392
 393                                         testout_div: testout_div {
 394                                                 compatible = "rockchip,rk3188-div-con";
 395                                                 rockchip,bits = <8 5>;
 396                                                 clocks = <&dummy>;
 397                                                 clock-output-names = "testout_div";
 398                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 399                                                 #clock-cells = <0>;
 400                                         };
 401
 402                                         /* reg[15:13]: reserved */
 403                                 };
 404
 405                                 clk_sel_con3: sel-con@006c {
 406                                         compatible = "rockchip,rk3188-selcon";
 407                                         reg = <0x006c 0x4>;
 408                                         #address-cells = <1>;
 409                                         #size-cells = <1>;
 410
 411                                         clk_uart4_div: clk_uart4_div {
 412                                                 compatible = "rockchip,rk3188-div-con";
 413                                                 rockchip,bits = <0 7>;
 414                                                 clocks = <&uart_pll_mux>;
 415                                                 clock-output-names = "clk_uart4_div";
 416                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 417                                                 #clock-cells = <0>;
 418                                         };
 419
 420                                         /* reg[7]: reserved */
 421
 422                                         clk_uart4: uart4_mux {
 423                                                 compatible = "rockchip,rk3188-mux-con";
 424                                                 rockchip,bits = <8 2>;
 425                                                 clocks = <&clk_uart4_div>, <&uart4_frac>, <&xin24m>;
 426                                                 clock-output-names = "clk_uart4";
 427                                                 #clock-cells = <0>;
 428                                                 rockchip,clkops-idx =
 429                                                         <CLKOPS_RATE_UART>;
 430                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 431                                         };
 432
 433                                         /* reg[15:10]: reserved */
 434
 435                                 };
 436
 437                                 clk_sel_con4: sel-con@0070 {
 438                                         compatible = "rockchip,rk3188-selcon";
 439                                         reg = <0x0070 0x4>;
 440                                         #address-cells = <1>;
 441                                         #size-cells = <1>;
 442
 443                                         i2s0_pll_div: i2s0_pll_div {
 444                                                 compatible = "rockchip,rk3188-div-con";
 445                                                 rockchip,bits = <0 7>;
 446                                                 clocks = <&clk_i2s_pll>;
 447                                                 clock-output-names = "clk_i2s_pll";
 448                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 449                                                 #clock-cells = <0>;
 450                                                 rockchip,clkops-idx =
 451                                                         <CLKOPS_RATE_MUX_DIV>;
 452                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 453                                         };
 454
 455                                         /* reg[7]: reserved */
 456
 457                                         clk_i2s0: i2s0_mux {
 458                                                 compatible = "rockchip,rk3188-mux-con";
 459                                                 rockchip,bits = <8 2>;
 460                                                 clocks = <&clk_i2s_pll>, <&i2s0_frac>, <&i2s_clkin>, <&xin12m>;
 461                                                 clock-output-names = "clk_i2s0";
 462                                                 #clock-cells = <0>;
 463                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 464                                         };
 465
 466                                         /* reg[11:10]: reserved */
 467
 468                                         clk_i2s0_out: i2s0_outclk_mux {
 469                                                 compatible = "rockchip,rk3188-mux-con";
 470                                                 rockchip,bits = <12 1>;
 471                                                 clocks = <&clk_i2s0>, <&xin12m>;
 472                                                 clock-output-names = "clk_i2s0_out";
 473                                                 #clock-cells = <0>;
 474                                         };
 475
 476                                         /* reg[14:13]: reserved */
 477
 478                                         clk_i2s_pll: i2s_pll_mux {
 479                                                 compatible = "rockchip,rk3188-mux-con";
 480                                                 rockchip,bits = <15 1>;
 481                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 482                                                 clock-output-names = "clk_i2s_pll";
 483                                                 #clock-cells = <0>;
 484                                                 #clock-init-cells = <1>;
 485                                         };
 486                                 };
 487
 488                                 clk_sel_con5: sel-con@0074 {
 489                                         compatible = "rockchip,rk3188-selcon";
 490                                         reg = <0x0074 0x4>;
 491                                         #address-cells = <1>;
 492                                         #size-cells = <1>;
 493
 494                                         spdif_div: spdif_div {
 495                                                 compatible = "rockchip,rk3188-div-con";
 496                                                 rockchip,bits = <0 7>;
 497                                                 clocks = <&clk_spdif_pll>;
 498                                                 clock-output-names = "spdif_div";
 499                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 500                                                 #clock-cells = <0>;
 501                                         };
 502
 503                                         /* reg[7]: reserved */
 504
 505                                         clk_spdif: spdif_mux {
 506                                                 compatible = "rockchip,rk3188-mux-con";
 507                                                 rockchip,bits = <8 2>;
 508                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
 509                                                 clock-output-names = "clk_spdif";
 510                                                 #clock-cells = <0>;
 511                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 512                                         };
 513
 514                                         /* reg[14:10]: reserved */
 515
 516                                         clk_spdif_pll: spdif_pll_mux {
 517                                                 compatible = "rockchip,rk3188-mux-con";
 518                                                 rockchip,bits = <15 1>;
 519                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 520                                                 clock-output-names = "clk_spdif_pll";
 521                                                 #clock-cells = <0>;
 522                                         };
 523                                 };
 524
 525                                 clk_sel_con6: sel-con@0078 {
 526                                         compatible = "rockchip,rk3188-selcon";
 527                                         reg = <0x0078 0x4>;
 528                                         #address-cells = <1>;
 529                                         #size-cells = <1>;
 530
 531                                         clk_isp_div: clk_isp_div {
 532                                                 compatible = "rockchip,rk3188-div-con";
 533                                                 rockchip,bits = <0 6>;
 534                                                 clocks = <&clk_isp>;
 535                                                 clock-output-names = "clk_isp";
 536                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 537                                                 #clock-cells = <0>;
 538                                                 rockchip,clkops-idx =
 539                                                         <CLKOPS_RATE_MUX_DIV>;
 540                                         };
 541
 542                                         clk_isp: clk_isp_mux {
 543                                                 compatible = "rockchip,rk3188-mux-con";
 544                                                 rockchip,bits = <6 2>;
 545                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
 546                                                 clock-output-names = "clk_isp";
 547                                                 #clock-cells = <0>;
 548                                         };
 549
 550                                         clk_isp_jpe_div: clk_isp_jpe_div {
 551                                                 compatible = "rockchip,rk3188-div-con";
 552                                                 rockchip,bits = <8 6>;
 553                                                 clocks = <&clk_isp_jpe>;
 554                                                 clock-output-names = "clk_isp_jpe";
 555                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 556                                                 #clock-cells = <0>;
 557                                                 rockchip,clkops-idx =
 558                                                         <CLKOPS_RATE_MUX_DIV>;
 559                                         };
 560
 561                                         clk_isp_jpe: clk_isp_jpe_mux {
 562                                                 compatible = "rockchip,rk3188-mux-con";
 563                                                 rockchip,bits = <14 2>;
 564                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
 565                                                 clock-output-names = "clk_isp_jpe";
 566                                                 #clock-cells = <0>;
 567                                         };
 568                                 };
 569
 570                                 clk_sel_con7: sel-con@007c {
 571                                         compatible = "rockchip,rk3188-selcon";
 572                                         reg = <0x007c 0x4>;
 573                                         #address-cells = <1>;
 574                                         #size-cells = <1>;
 575
 576                                         uart4_frac: uart4_frac {
 577                                                 compatible = "rockchip,rk3188-frac-con";
 578                                                 clocks = <&clk_uart4_div>;
 579                                                 clock-output-names = "uart4_frac";
 580                                                 /* numerator    denominator */
 581                                                 rockchip,bits = <0 32>;
 582                                                 rockchip,clkops-idx =
 583                                                         <CLKOPS_RATE_FRAC>;
 584                                                 #clock-cells = <0>;
 585                                         };
 586                                 };
 587
 588                                 clk_sel_con8: sel-con@0080 {
 589                                         compatible = "rockchip,rk3188-selcon";
 590                                         reg = <0x0080 0x4>;
 591                                         #address-cells = <1>;
 592                                         #size-cells = <1>;
 593
 594                                         i2s0_frac: i2s0_frac {
 595                                                 compatible = "rockchip,rk3188-frac-con";
 596                                                 clocks = <&clk_i2s_pll>;
 597                                                 clock-output-names = "i2s0_frac";
 598                                                 /* numerator    denominator */
 599                                                 rockchip,bits = <0 32>;
 600                                                 rockchip,clkops-idx =
 601                                                         <CLKOPS_RATE_FRAC>;
 602                                                 #clock-cells = <0>;
 603                                         };
 604                                 };
 605
 606                                 clk_sel_con9: sel-con@0084 {
 607                                         compatible = "rockchip,rk3188-selcon";
 608                                         reg = <0x0084 0x4>;
 609                                         #address-cells = <1>;
 610                                         #size-cells = <1>;
 611
 612                                         spdif_frac: spdif_frac {
 613                                                 compatible = "rockchip,rk3188-frac-con";
 614                                                 clocks = <&spdif_div>;
 615                                                 clock-output-names = "spdif_frac";
 616                                                 /* numerator    denominator */
 617                                                 rockchip,bits = <0 32>;
 618                                                 rockchip,clkops-idx =
 619                                                         <CLKOPS_RATE_FRAC>;
 620                                                 #clock-cells = <0>;
 621                                         };
 622                                 };
 623
 624                                 clk_sel_con10: sel-con@0088 {
 625                                         compatible = "rockchip,rk3188-selcon";
 626                                         reg = <0x0088 0x4>;
 627                                         #address-cells = <1>;
 628                                         #size-cells = <1>;
 629
 630                                         aclk_peri_div: aclk_peri_div {
 631                                                 compatible = "rockchip,rk3188-div-con";
 632                                                 rockchip,bits = <0 5>;
 633                                                 clocks = <&aclk_peri>;
 634                                                 clock-output-names = "aclk_peri";
 635                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 636                                                 #clock-cells = <0>;
 637                                                 rockchip,clkops-idx =
 638                                                         <CLKOPS_RATE_MUX_DIV>;
 639                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 640                                         };
 641
 642                                         /* reg[7:5]: reserved */
 643
 644                                         hclk_peri: hclk_peri_div {
 645                                                 compatible = "rockchip,rk3188-div-con";
 646                                                 rockchip,bits = <8 2>;
 647                                                 clocks = <&aclk_peri>;
 648                                                 clock-output-names = "hclk_peri";
 649                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 650                                                 rockchip,div-relations =
 651                                                                 <0x0 1
 652                                                                  0x1 2
 653                                                                  0x2 4>;
 654                                                 #clock-cells = <0>;
 655                                                 #clock-init-cells = <1>;
 656                                         };
 657
 658                                         /* reg[11:10]: reserved */
 659
 660                                         pclk_peri: pclk_peri_div {
 661                                                 compatible = "rockchip,rk3188-div-con";
 662                                                 rockchip,bits = <12 2>;
 663                                                 clocks = <&aclk_peri>;
 664                                                 clock-output-names = "pclk_peri";
 665                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 666                                                 rockchip,div-relations =
 667                                                                 <0x0 1
 668                                                                  0x1 2
 669                                                                  0x2 4
 670                                                                  0x3 8>;
 671                                                 #clock-cells = <0>;
 672                                                 #clock-init-cells = <1>;
 673                                         };
 674
 675                                         /* reg[14]: reserved */
 676
 677                                         aclk_peri: aclk_peri_mux {
 678                                                 compatible = "rockchip,rk3188-mux-con";
 679                                                 rockchip,bits = <15 1>;
 680                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 681                                                 clock-output-names = "aclk_peri";
 682                                                 #clock-cells = <0>;
 683                                                 #clock-init-cells = <1>;
 684                                         };
 685                                 };
 686
 687                                 clk_sel_con11: sel-con@008c {
 688                                         compatible = "rockchip,rk3188-selcon";
 689                                         reg = <0x008c 0x4>;
 690                                         #address-cells = <1>;
 691                                         #size-cells = <1>;
 692
 693                                         clk_sdmmc0_div: clk_sdmmc0_div {
 694                                                 compatible = "rockchip,rk3188-div-con";
 695                                                 rockchip,bits = <0 6>;
 696                                                 clocks = <&clk_sdmmc0>;
 697                                                 clock-output-names = "clk_sdmmc0";
 698                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 699                                                 #clock-cells = <0>;
 700                                                 rockchip,clkops-idx =
 701                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 702                                         };
 703
 704                                         clk_sdmmc0: clk_sdmmc0_mux {
 705                                                 compatible = "rockchip,rk3188-mux-con";
 706                                                 rockchip,bits = <6 2>;
 707                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
 708                                                 clock-output-names = "clk_sdmmc0";
 709                                                 #clock-cells = <0>;
 710                                         };
 711
 712                                         hsicphy_12m_div: hsicphy_12m_div {
 713                                                 compatible = "rockchip,rk3188-div-con";
 714                                                 rockchip,bits = <8 6>;
 715                                                 clocks = <&hsicphy_480m>;
 716                                                 clock-output-names = "hsicphy_12m_div";
 717                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 718                                                 #clock-cells = <0>;
 719                                         };
 720
 721                                 };
 722
 723                                 clk_sel_con12: sel-con@0090 {
 724                                         compatible = "rockchip,rk3188-selcon";
 725                                         reg = <0x0090 0x4>;
 726                                         #address-cells = <1>;
 727                                         #size-cells = <1>;
 728
 729                                         clk_sdio0_div: clk_sdio0_div {
 730                                                 compatible = "rockchip,rk3188-div-con";
 731                                                 rockchip,bits = <0 6>;
 732                                                 clocks = <&clk_sdio0>;
 733                                                 clock-output-names = "clk_sdio0";
 734                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 735                                                 #clock-cells = <0>;
 736                                                 rockchip,clkops-idx =
 737                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 738                                         };
 739
 740                                         clk_sdio0: clk_sdio0_mux {
 741                                                 compatible = "rockchip,rk3188-mux-con";
 742                                                 rockchip,bits = <6 2>;
 743                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
 744                                                 clock-output-names = "clk_sdio0";
 745                                                 #clock-cells = <0>;
 746                                         };
 747
 748                                         clk_emmc_div: clk_emmc_div {
 749                                                 compatible = "rockchip,rk3188-div-con";
 750                                                 rockchip,bits = <8 6>;
 751                                                 clocks = <&clk_emmc>;
 752                                                 clock-output-names = "clk_emmc";
 753                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 754                                                 #clock-cells = <0>;
 755                                                 rockchip,clkops-idx =
 756                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 757                                         };
 758
 759                                         clk_emmc: clk_emmc_mux {
 760                                                 compatible = "rockchip,rk3188-mux-con";
 761                                                 rockchip,bits = <14 2>;
 762                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
 763                                                 clock-output-names = "clk_emmc";
 764                                                 #clock-cells = <0>;
 765                                         };
 766                                 };
 767
 768                                 clk_sel_con13: sel-con@0094 {
 769                                         compatible = "rockchip,rk3188-selcon";
 770                                         reg = <0x0094 0x4>;
 771                                         #address-cells = <1>;
 772                                         #size-cells = <1>;
 773
 774                                         clk_uart0_pll_div: clk_uart0_pll_div {
 775                                                 compatible = "rockchip,rk3188-div-con";
 776                                                 rockchip,bits = <0 7>;
 777                                                 clocks = <&clk_uart0_pll>;
 778                                                 clock-output-names = "clk_uart0_pll";
 779                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 780                                                 #clock-cells = <0>;
 781                                                 rockchip,clkops-idx =
 782                                                         <CLKOPS_RATE_MUX_DIV>;
 783                                         };
 784
 785                                         /* reg[7]: reserved */
 786
 787                                         clk_uart0: uart0_mux {
 788                                                 compatible = "rockchip,rk3188-mux-con";
 789                                                 rockchip,bits = <8 2>;
 790                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>;
 791                                                 clock-output-names = "clk_uart0";
 792                                                 #clock-cells = <0>;
 793                                                 rockchip,clkops-idx =
 794                                                         <CLKOPS_RATE_UART>;
 795                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 796                                         };
 797
 798                                         /* reg[10]: reserved */
 799
 800                                         usbphy_480m: usbphy_480m_mux {
 801                                                 compatible = "rockchip,rk3188-mux-con";
 802                                                 rockchip,bits = <11 2>;
 803                                                 clocks = <&clk_otgphy0_480m>, <&clk_otgphy1_480m>, <&clk_otgphy2_480m>;
 804                                                 clock-output-names = "usbphy_480m";
 805                                                 #clock-cells = <0>;
 806                                         };
 807
 808                                         clk_uart0_pll: clk_uart0_pll_mux {
 809                                                 compatible = "rockchip,rk3188-mux-con";
 810                                                 rockchip,bits = <13 2>;
 811                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 812                                                 clock-output-names = "clk_uart0_pll";
 813                                                 #clock-cells = <0>;
 814                                         };
 815
 816                                         uart_pll_mux: uart_pll_mux {
 817                                                 compatible = "rockchip,rk3188-mux-con";
 818                                                 rockchip,bits = <15 1>;
 819                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 820                                                 clock-output-names = "uart_pll_mux";
 821                                                 #clock-cells = <0>;
 822                                                 #clock-init-cells = <1>;
 823                                         };
 824                                 };
 825
 826                                 clk_sel_con14: sel-con@0098 {
 827                                         compatible = "rockchip,rk3188-selcon";
 828                                         reg = <0x0098 0x4>;
 829                                         #address-cells = <1>;
 830                                         #size-cells = <1>;
 831
 832                                         clk_uart1_div: clk_uart1_div {
 833                                                 compatible = "rockchip,rk3188-div-con";
 834                                                 rockchip,bits = <0 7>;
 835                                                 clocks = <&uart_pll_mux>;
 836                                                 clock-output-names = "clk_uart1_div";
 837                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 838                                                 #clock-cells = <0>;
 839                                         };
 840
 841                                         /* reg[7]: reserved */
 842
 843                                         clk_uart1: uart1_mux {
 844                                                 compatible = "rockchip,rk3188-mux-con";
 845                                                 rockchip,bits = <8 2>;
 846                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
 847                                                 clock-output-names = "clk_uart1";
 848                                                 #clock-cells = <0>;
 849                                                 rockchip,clkops-idx =
 850                                                         <CLKOPS_RATE_UART>;
 851                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 852                                         };
 853
 854                                         /* reg[15:10]: reserved */
 855                                 };
 856
 857                                 clk_sel_con15: sel-con@009c {
 858                                         compatible = "rockchip,rk3188-selcon";
 859                                         reg = <0x009c 0x4>;
 860                                         #address-cells = <1>;
 861                                         #size-cells = <1>;
 862
 863                                         clk_uart2_div: clk_uart2_div {
 864                                                 compatible = "rockchip,rk3188-div-con";
 865                                                 rockchip,bits = <0 7>;
 866                                                 clocks = <&uart_pll_mux>;
 867                                                 clock-output-names = "clk_uart2_div";
 868                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 869                                                 #clock-cells = <0>;
 870                                         };
 871
 872                                         /* reg[7]: reserved */
 873
 874                                         clk_uart2: uart2_mux {
 875                                                 compatible = "rockchip,rk3188-mux-con";
 876                                                 rockchip,bits = <8 2>;
 877                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
 878                                                 clock-output-names = "clk_uart2";
 879                                                 #clock-cells = <0>;
 880                                                 rockchip,clkops-idx =
 881                                                         <CLKOPS_RATE_UART>;
 882                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 883                                         };
 884
 885                                         /* reg[15:10]: reserved */
 886                                 };
 887
 888                                 clk_sel_con16: sel-con@00a0 {
 889                                         compatible = "rockchip,rk3188-selcon";
 890                                         reg = <0x00a0 0x4>;
 891                                         #address-cells = <1>;
 892                                         #size-cells = <1>;
 893
 894                                         clk_uart3_div: clk_uart3_div {
 895                                                 compatible = "rockchip,rk3188-div-con";
 896                                                 rockchip,bits = <0 7>;
 897                                                 clocks = <&uart_pll_mux>;
 898                                                 clock-output-names = "clk_uart3_div";
 899                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 900                                                 #clock-cells = <0>;
 901                                         };
 902
 903                                         /* reg[7]: reserved */
 904
 905                                         clk_uart3: uart3_mux {
 906                                                 compatible = "rockchip,rk3188-mux-con";
 907                                                 rockchip,bits = <8 2>;
 908                                                 clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>;
 909                                                 clock-output-names = "clk_uart3";
 910                                                 #clock-cells = <0>;
 911                                                 rockchip,clkops-idx =
 912                                                         <CLKOPS_RATE_UART>;
 913                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 914                                         };
 915
 916                                         /* reg[15:10]: reserved */
 917                                 };
 918
 919                                 clk_sel_con17: sel-con@00a4 {
 920                                         compatible = "rockchip,rk3188-selcon";
 921                                         reg = <0x00a4 0x4>;
 922                                         #address-cells = <1>;
 923                                         #size-cells = <1>;
 924
 925                                         uart0_frac: uart0_frac {
 926                                                 compatible = "rockchip,rk3188-frac-con";
 927                                                 clocks = <&clk_uart0_pll>;
 928                                                 clock-output-names = "uart0_frac";
 929                                                 /* numerator    denominator */
 930                                                 rockchip,bits = <0 32>;
 931                                                 rockchip,clkops-idx =
 932                                                         <CLKOPS_RATE_FRAC>;
 933                                                 #clock-cells = <0>;
 934                                         };
 935                                 };
 936
 937                                 clk_sel_con18: sel-con@00a8 {
 938                                         compatible = "rockchip,rk3188-selcon";
 939                                         reg = <0x00a8 0x4>;
 940                                         #address-cells = <1>;
 941                                         #size-cells = <1>;
 942
 943                                         uart1_frac: uart1_frac {
 944                                                 compatible = "rockchip,rk3188-frac-con";
 945                                                 clocks = <&clk_uart1_div>;
 946                                                 clock-output-names = "uart1_frac";
 947                                                 /* numerator    denominator */
 948                                                 rockchip,bits = <0 32>;
 949                                                 rockchip,clkops-idx =
 950                                                         <CLKOPS_RATE_FRAC>;
 951                                                 #clock-cells = <0>;
 952                                         };
 953                                 };
 954
 955                                 clk_sel_con19: sel-con@00ac {
 956                                         compatible = "rockchip,rk3188-selcon";
 957                                         reg = <0x00ac 0x4>;
 958                                         #address-cells = <1>;
 959                                         #size-cells = <1>;
 960
 961                                         uart2_frac: uart2_frac {
 962                                                 compatible = "rockchip,rk3188-frac-con";
 963                                                 clocks = <&clk_uart2_div>;
 964                                                 clock-output-names = "uart2_frac";
 965                                                 /* numerator    denominator */
 966                                                 rockchip,bits = <0 32>;
 967                                                 rockchip,clkops-idx =
 968                                                         <CLKOPS_RATE_FRAC>;
 969                                                 #clock-cells = <0>;
 970                                         };
 971
 972                                 };
 973
 974                                 clk_sel_con20: sel-con@00b0 {
 975                                         compatible = "rockchip,rk3188-selcon";
 976                                         reg = <0x00b0 0x4>;
 977                                         #address-cells = <1>;
 978                                         #size-cells = <1>;
 979
 980                                         uart3_frac: uart3_frac {
 981                                                 compatible = "rockchip,rk3188-frac-con";
 982                                                 clocks = <&clk_uart3_div>;
 983                                                 clock-output-names = "uart3_frac";
 984                                                 /* numerator    denominator */
 985                                                 rockchip,bits = <0 32>;
 986                                                 rockchip,clkops-idx =
 987                                                         <CLKOPS_RATE_FRAC>;
 988                                                 #clock-cells = <0>;
 989                                         };
 990                                 };
 991
 992                                 clk_sel_con21: sel-con@00b4 {
 993                                         compatible = "rockchip,rk3188-selcon";
 994                                         reg = <0x00b4 0x4>;
 995                                         #address-cells = <1>;
 996                                         #size-cells = <1>;
 997
 998                                         clk_mac_pll: clk_mac_pll_mux {
 999                                                 compatible = "rockchip,rk3188-mux-con";
1000                                                 rockchip,bits = <0 2>;
1001                                                 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>;
1002                                                 clock-output-names = "clk_mac_pll";
1003                                                 #clock-cells = <0>;
1004                                         };
1005
1006                                         /* reg[3:2]: reserved */
1007
1008                                         clk_mac: clk_mac_mux {
1009                                                 compatible = "rockchip,rk3188-mux-con";
1010                                                 rockchip,bits = <4 1>;
1011                                                 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1012                                                 clock-output-names = "clk_mac";
1013                                                 #clock-cells = <0>;
1014                                                 rockchip,clkops-idx =
1015                                                         <CLKOPS_RATE_MAC_REF>;
1016                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1017                                         };
1018
1019                                         /* reg[7:5]: reserved */
1020
1021                                         clk_mac_pll_div: clk_mac_pll_div {
1022                                                 compatible = "rockchip,rk3188-div-con";
1023                                                 rockchip,bits = <8 5>;
1024                                                 clocks = <&clk_mac_pll>;
1025                                                 clock-output-names = "clk_mac_pll";
1026                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1027                                                 #clock-cells = <0>;
1028                                                 rockchip,clkops-idx =
1029                                                         <CLKOPS_RATE_MUX_DIV>;
1030                                         };
1031
1032                                         /* reg[15:13]: reserved */
1033                                 };
1034
1035                                 clk_sel_con22: sel-con@00b8 {
1036                                         compatible = "rockchip,rk3188-selcon";
1037                                         reg = <0x00b8 0x4>;
1038                                         #address-cells = <1>;
1039                                         #size-cells = <1>;
1040
1041                                         clk_hsadc_pll: clk_hsadc_pll_mux {
1042                                                 compatible = "rockchip,rk3188-mux-con";
1043                                                 rockchip,bits = <0 1>;
1044                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1045                                                 clock-output-names = "clk_hsadc_pll";
1046                                                 #clock-cells = <0>;
1047                                         };
1048 /*
1049                                         wifi_pll_mux: wifi_pll_mux {
1050                                                 compatible = "rockchip,rk3188-mux-con";
1051                                                 rockchip,bits = <1 1>;
1052                                                 clocks = <&>, <&>;
1053                                                 clock-output-names = "wifi_pll_mux";
1054                                                 #clock-cells = <0>;
1055                                         };
1056 */
1057
1058                                         /* reg[3:2]: reserved */
1059
1060                                         clk_hsadc_out: clk_hsadc_out {
1061                                                 compatible = "rockchip,rk3188-mux-con";
1062                                                 rockchip,bits = <4 1>;
1063                                                 clocks = <&clk_hsadc_pll>, <&clk_hsadc_ext>;
1064                                                 clock-output-names = "clk_hsadc_out";
1065                                                 #clock-cells = <0>;
1066                                                 rockchip,clkops-idx =
1067                                                         <CLKOPS_RATE_HSADC>;
1068                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1069                                         };
1070
1071                                         /* reg[6:5]: reserved */
1072
1073                                         clk_hsadc: clk_hsadc {
1074                                                 compatible = "rockchip,rk3188-mux-con";
1075                                                 rockchip,bits = <7 1>;
1076                                                 clocks = <&clk_hsadc_out>, <&clk_hsadc_inv>;
1077                                                 clock-output-names = "clk_hsadc";
1078                                                 #clock-cells = <0>;
1079                                         };
1080
1081                                         clk_hsadc_pll_div: clk_hsadc_pll_div {
1082                                                 compatible = "rockchip,rk3188-div-con";
1083                                                 rockchip,bits = <8 8>;
1084                                                 clocks = <&clk_hsadc_pll>;
1085                                                 clock-output-names = "clk_hsadc_pll";
1086                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1087                                                 #clock-cells = <0>;
1088                                                 rockchip,clkops-idx =
1089                                                         <CLKOPS_RATE_MUX_DIV>;
1090                                         };
1091                                 };
1092 /*
1093                                 clk_sel_con23: sel-con@00bc {
1094                                         compatible = "rockchip,rk3188-selcon";
1095                                         reg = <0x00bc 0x4>;
1096                                         #address-cells = <1>;
1097                                         #size-cells = <1>;
1098
1099                                         wifi_frac: wifi_frac {
1100                                                 compatible = "rockchip,rk3188-frac-con";
1101                                                 clocks = <&>;
1102                                                 clock-output-names = "wifi_frac";
1103                                                 / numerator     denominator /
1104                                                 rockchip,bits = <0 32>;
1105                                                 rockchip,clkops-idx =
1106                                                         <>;
1107                                                 #clock-cells = <0>;
1108                                         };
1109                                 };
1110 */
1111
1112                                 clk_sel_con24: sel-con@00c0 {
1113                                         compatible = "rockchip,rk3188-selcon";
1114                                         reg = <0x00c0 0x4>;
1115                                         #address-cells = <1>;
1116                                         #size-cells = <1>;
1117
1118                                         /* reg[7:0]: reserved */
1119
1120                                         clk_saradc: clk_saradc_div {
1121                                                 compatible = "rockchip,rk3188-div-con";
1122                                                 rockchip,bits = <8 8>;
1123                                                 clocks = <&xin24m>;
1124                                                 clock-output-names = "clk_saradc";
1125                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1126                                                 #clock-cells = <0>;
1127                                         };
1128                                 };
1129
1130                                 clk_sel_con25: sel-con@00c4 {
1131                                         compatible = "rockchip,rk3188-selcon";
1132                                         reg = <0x00c4 0x4>;
1133                                         #address-cells = <1>;
1134                                         #size-cells = <1>;
1135
1136                                         clk_spi0_div: clk_spi0_div {
1137                                                 compatible = "rockchip,rk3188-div-con";
1138                                                 rockchip,bits = <0 7>;
1139                                                 clocks = <&clk_spi0>;
1140                                                 clock-output-names = "clk_spi0";
1141                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1142                                                 #clock-cells = <0>;
1143                                                 rockchip,clkops-idx =
1144                                                         <CLKOPS_RATE_MUX_DIV>;
1145                                         };
1146
1147                                         clk_spi0: clk_spi0_mux {
1148                                                 compatible = "rockchip,rk3188-mux-con";
1149                                                 rockchip,bits = <7 1>;
1150                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1151                                                 clock-output-names = "clk_spi0";
1152                                                 #clock-cells = <0>;
1153                                         };
1154
1155                                         clk_spi1_div: clk_spi1_div {
1156                                                 compatible = "rockchip,rk3188-div-con";
1157                                                 rockchip,bits = <8 7>;
1158                                                 clocks = <&clk_spi1>;
1159                                                 clock-output-names = "clk_spi1";
1160                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1161                                                 #clock-cells = <0>;
1162                                                 rockchip,clkops-idx =
1163                                                         <CLKOPS_RATE_MUX_DIV>;
1164                                         };
1165
1166                                         clk_spi1: clk_spi1_mux {
1167                                                 compatible = "rockchip,rk3188-mux-con";
1168                                                 rockchip,bits = <15 1>;
1169                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1170                                                 clock-output-names = "clk_spi1";
1171                                                 #clock-cells = <0>;
1172                                         };
1173                                 };
1174
1175                                 clk_sel_con26: sel-con@00c8 {
1176                                         compatible = "rockchip,rk3188-selcon";
1177                                         reg = <0x00c8 0x4>;
1178                                         #address-cells = <1>;
1179                                         #size-cells = <1>;
1180
1181                                         ddr_div: ddr_div {
1182                                                 compatible = "rockchip,rk3188-div-con";
1183                                                 rockchip,bits = <0 2>;
1184                                                 clocks = <&clk_ddr>;
1185                                                 clock-output-names = "clk_ddr";
1186                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1187                                                 rockchip,div-relations =
1188                                                                 <0x0 1
1189                                                                  0x1 2
1190                                                                  0x3 4>;
1191                                                 #clock-cells = <0>;
1192                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1193                                                                         CLK_SET_RATE_NO_REPARENT)>;
1194                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
1195                                         };
1196
1197                                         clk_ddr: ddr_clk_pll_mux {
1198                                                 compatible = "rockchip,rk3188-mux-con";
1199                                                 rockchip,bits = <2 1>;
1200                                                 clocks = <&clk_dpll>, <&clk_gpll>;
1201                                                 clock-output-names = "clk_ddr";
1202                                                 #clock-cells = <0>;
1203                                         };
1204
1205                                         /* reg[5:3]: reserved */
1206
1207                                         clk_crypto: crypto_div {
1208                                                 compatible = "rockchip,rk3188-div-con";
1209                                                 rockchip,bits = <6 2>;
1210                                                 clocks = <&aclk_bus>;
1211                                                 clock-output-names = "clk_crypto";
1212                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1213                                                 #clock-cells = <0>;
1214                                                 #clock-init-cells = <1>;
1215                                         };
1216
1217                                         clk_cif_pll: clk_cif_pll_mux {
1218                                                 compatible = "rockchip,rk3188-mux-con";
1219                                                 rockchip,bits = <8 1>;
1220                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1221                                                 clock-output-names = "clk_cif_pll";
1222                                                 #clock-cells = <0>;
1223                                         };
1224
1225                                         clk_cif_out_div: clk_cif_out_div {
1226                                                 compatible = "rockchip,rk3188-div-con";
1227                                                 rockchip,bits = <9 5>;
1228                                                 clocks = <&clk_cif_out>;
1229                                                 clock-output-names = "clk_cif_out";
1230                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1231                                                 #clock-cells = <0>;
1232                                                 rockchip,clkops-idx =
1233                                                         <CLKOPS_RATE_MUX_DIV>;
1234                                         };
1235
1236                                         /* reg[14]: reserved */
1237
1238                                         clk_cif_out: clk_cif_out_mux {
1239                                                 compatible = "rockchip,rk3188-mux-con";
1240                                                 rockchip,bits = <15 1>;
1241                                                 clocks = <&clk_cif_pll>, <&xin24m>;
1242                                                 clock-output-names = "clk_cif_out";
1243                                                 #clock-cells = <0>;
1244                                         };
1245                                 };
1246
1247                                 clk_sel_con27: sel-con@00cc {
1248                                         compatible = "rockchip,rk3188-selcon";
1249                                         reg = <0x00cc 0x4>;
1250                                         #address-cells = <1>;
1251                                         #size-cells = <1>;
1252
1253                                         dclk_lcdc0: dclk_lcdc0_mux {
1254                                                 compatible = "rockchip,rk3188-mux-con";
1255                                                 rockchip,bits = <0 2>;
1256                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1257                                                 clock-output-names = "dclk_lcdc0";
1258                                                 #clock-cells = <0>;
1259                                         };
1260
1261                                         /* reg[7:2]: reserved */
1262
1263                                         dclk_lcdc0_div: dclk_lcdc0_div {
1264                                                 compatible = "rockchip,rk3188-div-con";
1265                                                 rockchip,bits = <8 8>;
1266                                                 clocks = <&dclk_lcdc0>;
1267                                                 clock-output-names = "dclk_lcdc0";
1268                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1269                                                 #clock-cells = <0>;
1270                                                 rockchip,clkops-idx =
1271                                                         <CLKOPS_RATE_MUX_EVENDIV>;
1272                                         };
1273                                 };
1274
1275                                 clk_sel_con28: sel-con@00d0 {
1276                                         compatible = "rockchip,rk3188-selcon";
1277                                         reg = <0x00d0 0x4>;
1278                                         #address-cells = <1>;
1279                                         #size-cells = <1>;
1280
1281                                         clk_edp_div: clk_edp_div {
1282                                                 compatible = "rockchip,rk3188-div-con";
1283                                                 rockchip,bits = <0 6>;
1284                                                 clocks = <&clk_edp>;
1285                                                 clock-output-names = "clk_edp";
1286                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1287                                                 #clock-cells = <0>;
1288                                                 rockchip,clkops-idx =
1289                                                         <CLKOPS_RATE_MUX_DIV>;
1290                                         };
1291
1292                                         clk_edp: clk_edp_mux {
1293                                                 compatible = "rockchip,rk3188-mux-con";
1294                                                 rockchip,bits = <6 2>;
1295                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1296                                                 clock-output-names = "clk_edp";
1297                                                 #clock-cells = <0>;
1298                                         };
1299
1300                                         hclk_vio: hclk_vio_div {
1301                                                 compatible = "rockchip,rk3188-div-con";
1302                                                 rockchip,bits = <8 5>;
1303                                                 clocks = <&aclk_vio0>;
1304                                                 clock-output-names = "hclk_vio";
1305                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1306                                                 #clock-cells = <0>;
1307                                                 #clock-init-cells = <1>;
1308                                         };
1309
1310                                         /* reg[14:13]: reserved */
1311
1312                                         clk_edp_24m: edp_24m_mux {
1313                                                 compatible = "rockchip,rk3188-mux-con";
1314                                                 rockchip,bits = <15 1>;
1315                                                 clocks = <&edp_24m_clkin>, <&xin24m>;
1316                                                 clock-output-names = "clk_edp_24m";
1317                                                 #clock-cells = <0>;
1318                                         };
1319                                 };
1320
1321                                 clk_sel_con29: sel-con@00d4 {
1322                                         compatible = "rockchip,rk3188-selcon";
1323                                         reg = <0x00d4 0x4>;
1324                                         #address-cells = <1>;
1325                                         #size-cells = <1>;
1326
1327                                         hsicphy_480m: hsicphy_480m_mux {
1328                                                 compatible = "rockchip,rk3188-mux-con";
1329                                                 rockchip,bits = <0 2>;
1330                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1331                                                 clock-output-names = "hsicphy_480m";
1332                                                 #clock-cells = <0>;
1333                                         };
1334
1335                                         hsicphy_12m: hsicphy_12m_mux {
1336                                                 compatible = "rockchip,rk3188-mux-con";
1337                                                 rockchip,bits = <2 1>;
1338                                                 clocks = <&clk_gates13 9>, <&hsicphy_12m_div>;
1339                                                 clock-output-names = "hsicphy_12m";
1340                                                 #clock-cells = <0>;
1341                                         };
1342
1343                                         clkin_isp: clkin_isp {
1344                                                 compatible = "rockchip,rk3188-mux-con";
1345                                                 rockchip,bits = <3 1>;
1346                                                 clocks = <&clk_gates16 3>, <&pclkin_isp_inv>;
1347                                                 clock-output-names = "clkin_isp";
1348                                                 #clock-cells = <0>;
1349                                         };
1350
1351                                         clkin_cif: clkin_cif {
1352                                                 compatible = "rockchip,rk3188-mux-con";
1353                                                 rockchip,bits = <4 1>;
1354                                                 clocks = <&clk_gates16 0>, <&pclkin_cif_inv>;
1355                                                 clock-output-names = "clkin_cif";
1356                                                 #clock-cells = <0>;
1357                                         };
1358
1359                                         /* reg[5]: reserved */
1360
1361                                         dclk_lcdc1: dclk_lcdc1_mux {
1362                                                 compatible = "rockchip,rk3188-mux-con";
1363                                                 rockchip,bits = <6 2>;
1364                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1365                                                 clock-output-names = "dclk_lcdc1";
1366                                                 #clock-cells = <0>;
1367                                         };
1368
1369                                         dclk_lcdc1_div: dclk_lcdc1_div {
1370                                                 compatible = "rockchip,rk3188-div-con";
1371                                                 rockchip,bits = <8 8>;
1372                                                 clocks = <&dclk_lcdc1>;
1373                                                 clock-output-names = "dclk_lcdc1";
1374                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1375                                                 #clock-cells = <0>;
1376                                                 rockchip,clkops-idx =
1377                                                         <CLKOPS_RATE_MUX_EVENDIV>;
1378                                         };
1379                                 };
1380
1381                                 clk_sel_con30: sel-con@00d8 {
1382                                         compatible = "rockchip,rk3188-selcon";
1383                                         reg = <0x00d8 0x4>;
1384                                         #address-cells = <1>;
1385                                         #size-cells = <1>;
1386
1387                                         aclk_rga_div: aclk_rga_div {
1388                                                 compatible = "rockchip,rk3188-div-con";
1389                                                 rockchip,bits = <0 5>;
1390                                                 clocks = <&aclk_rga>;
1391                                                 clock-output-names = "aclk_rga";
1392                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1393                                                 #clock-cells = <0>;
1394                                                 rockchip,clkops-idx =
1395                                                         <CLKOPS_RATE_MUX_DIV>;
1396                                         };
1397
1398                                         /* reg[5]: reserved */
1399
1400                                         aclk_rga: aclk_rga_mux {
1401                                                 compatible = "rockchip,rk3188-mux-con";
1402                                                 rockchip,bits = <6 2>;
1403                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1404                                                 clock-output-names = "aclk_rga";
1405                                                 #clock-cells = <0>;
1406                                         };
1407
1408                                         clk_rga_div: clk_rga_div {
1409                                                 compatible = "rockchip,rk3188-div-con";
1410                                                 rockchip,bits = <8 5>;
1411                                                 clocks = <&clk_rga>;
1412                                                 clock-output-names = "clk_rga";
1413                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1414                                                 #clock-cells = <0>;
1415                                                 rockchip,clkops-idx =
1416                                                         <CLKOPS_RATE_MUX_DIV>;
1417                                         };
1418
1419                                         /* reg[13]: reserved */
1420
1421                                         clk_rga: clk_rga_mux {
1422                                                 compatible = "rockchip,rk3188-mux-con";
1423                                                 rockchip,bits = <14 2>;
1424                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1425                                                 clock-output-names = "clk_rga";
1426                                                 #clock-cells = <0>;
1427                                         };
1428                                 };
1429
1430                                 clk_sel_con31: sel-con@00dc {
1431                                         compatible = "rockchip,rk3188-selcon";
1432                                         reg = <0x00dc 0x4>;
1433                                         #address-cells = <1>;
1434                                         #size-cells = <1>;
1435
1436                                         aclk_vio0_div: aclk_vio0_div {
1437                                                 compatible = "rockchip,rk3188-div-con";
1438                                                 rockchip,bits = <0 5>;
1439                                                 clocks = <&aclk_vio0>;
1440                                                 clock-output-names = "aclk_vio0";
1441                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1442                                                 #clock-cells = <0>;
1443                                                 rockchip,clkops-idx =
1444                                                         <CLKOPS_RATE_MUX_DIV>;
1445                                         };
1446
1447                                         /* reg[5]: reserved */
1448
1449                                         aclk_vio0: aclk_vio0_mux {
1450                                                 compatible = "rockchip,rk3188-mux-con";
1451                                                 rockchip,bits = <6 2>;
1452                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1453                                                 clock-output-names = "aclk_vio0";
1454                                                 #clock-cells = <0>;
1455                                                 #clock-init-cells = <1>;
1456                                         };
1457
1458                                         aclk_vio1_div: aclk_vio1_div {
1459                                                 compatible = "rockchip,rk3188-div-con";
1460                                                 rockchip,bits = <8 5>;
1461                                                 clocks = <&aclk_vio1>;
1462                                                 clock-output-names = "aclk_vio1";
1463                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1464                                                 #clock-cells = <0>;
1465                                                 rockchip,clkops-idx =
1466                                                         <CLKOPS_RATE_MUX_DIV>;
1467                                         };
1468
1469                                         /* reg[13]: reserved */
1470
1471                                         aclk_vio1: aclk_vio1_mux {
1472                                                 compatible = "rockchip,rk3188-mux-con";
1473                                                 rockchip,bits = <14 2>;
1474                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1475                                                 clock-output-names = "aclk_vio1";
1476                                                 #clock-cells = <0>;
1477                                                 #clock-init-cells = <1>;
1478                                         };
1479                                 };
1480
1481                                 clk_sel_con32: sel-con@00e0 {
1482                                         compatible = "rockchip,rk3188-selcon";
1483                                         reg = <0x00e0 0x4>;
1484                                         #address-cells = <1>;
1485                                         #size-cells = <1>;
1486
1487                                         clk_vepu_div: clk_vepu_div {
1488                                                 compatible = "rockchip,rk3188-div-con";
1489                                                 rockchip,bits = <0 5>;
1490                                                 clocks = <&clk_vepu>;
1491                                                 clock-output-names = "clk_vepu";
1492                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1493                                                 #clock-cells = <0>;
1494                                                 rockchip,clkops-idx =
1495                                                         <CLKOPS_RATE_MUX_DIV>;
1496                                         };
1497
1498                                         /* reg[5]: reserved */
1499
1500                                         clk_vepu: clk_vepu_mux {
1501                                                 compatible = "rockchip,rk3188-mux-con";
1502                                                 rockchip,bits = <6 2>;
1503                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1504                                                 clock-output-names = "clk_vepu";
1505                                                 #clock-cells = <0>;
1506                                         };
1507
1508                                         clk_vdpu_div: clk_vdpu_div {
1509                                                 compatible = "rockchip,rk3188-div-con";
1510                                                 rockchip,bits = <8 5>;
1511                                                 clocks = <&clk_vdpu>;
1512                                                 clock-output-names = "clk_vdpu";
1513                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1514                                                 #clock-cells = <0>;
1515                                                 rockchip,clkops-idx =
1516                                                         <CLKOPS_RATE_MUX_DIV>;
1517                                         };
1518
1519                                         /* reg[13]: reserved */
1520
1521                                         clk_vdpu: clk_vdpu_mux {
1522                                                 compatible = "rockchip,rk3188-mux-con";
1523                                                 rockchip,bits = <14 2>;
1524                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1525                                                 clock-output-names = "clk_vdpu";
1526                                                 #clock-cells = <0>;
1527                                         };
1528                                 };
1529
1530                                 clk_sel_con33: sel-con@00e4 {
1531                                         compatible = "rockchip,rk3188-selcon";
1532                                         reg = <0x00e4 0x4>;
1533                                         #address-cells = <1>;
1534                                         #size-cells = <1>;
1535
1536                                         pclk_pd_pmu: pclk_pd_pmu_div {
1537                                                 compatible = "rockchip,rk3188-div-con";
1538                                                 rockchip,bits = <0 5>;
1539                                                 clocks = <&clk_gpll>;
1540                                                 clock-output-names = "pclk_pd_pmu";
1541                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1542                                                 #clock-cells = <0>;
1543                                                 #clock-init-cells = <1>;
1544                                         };
1545
1546                                         /* reg[7:5]: reserved */
1547
1548                                         pclk_pd_alive: pclk_pd_alive {
1549                                                 compatible = "rockchip,rk3188-div-con";
1550                                                 rockchip,bits = <8 5>;
1551                                                 clocks = <&clk_gpll>;
1552                                                 clock-output-names = "pclk_pd_alive";
1553                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1554                                                 #clock-cells = <0>;
1555                                                 #clock-init-cells = <1>;
1556                                         };
1557
1558                                         /* reg[15:13]: reserved */
1559                                 };
1560
1561                                 clk_sel_con34: sel-con@00e8 {
1562                                         compatible = "rockchip,rk3188-selcon";
1563                                         reg = <0x00e8 0x4>;
1564                                         #address-cells = <1>;
1565                                         #size-cells = <1>;
1566
1567                                         clk_gpu_div: clk_gpu_div {
1568                                                 compatible = "rockchip,rk3188-div-con";
1569                                                 rockchip,bits = <0 5>;
1570                                                 clocks = <&clk_gpu>;
1571                                                 clock-output-names = "clk_gpu";
1572                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1573                                                 #clock-cells = <0>;
1574                                                 rockchip,clkops-idx =
1575                                                         <CLKOPS_RATE_MUX_DIV>;
1576                                         };
1577
1578                                         /* reg[5]: reserved */
1579
1580                                         clk_gpu: clk_gpu_mux {
1581                                                 compatible = "rockchip,rk3188-mux-con";
1582                                                 rockchip,bits = <6 2>;
1583                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
1584                                                 clock-output-names = "clk_gpu";
1585                                                 #clock-cells = <0>;
1586                                                 #clock-init-cells = <1>;
1587                                         };
1588
1589                                         clk_sdio1_div: clk_sdio1_div {
1590                                                 compatible = "rockchip,rk3188-div-con";
1591                                                 rockchip,bits = <8 6>;
1592                                                 clocks = <&clk_sdio1>;
1593                                                 clock-output-names = "clk_sdio1";
1594                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1595                                                 #clock-cells = <0>;
1596                                                 rockchip,clkops-idx =
1597                                                         <CLKOPS_RATE_MUX_EVENDIV>;
1598                                         };
1599
1600                                         clk_sdio1: clk_sdio1_mux {
1601                                                 compatible = "rockchip,rk3188-mux-con";
1602                                                 rockchip,bits = <14 2>;
1603                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
1604                                                 clock-output-names = "clk_sdio1";
1605                                                 #clock-cells = <0>;
1606                                         };
1607                                 };
1608
1609                                 clk_sel_con35: sel-con@00ec {
1610                                         compatible = "rockchip,rk3188-selcon";
1611                                         reg = <0x00ec 0x4>;
1612                                         #address-cells = <1>;
1613                                         #size-cells = <1>;
1614
1615                                         clk_tsp_div: clk_tsp_div {
1616                                                 compatible = "rockchip,rk3188-div-con";
1617                                                 rockchip,bits = <0 5>;
1618                                                 clocks = <&clk_tsp>;
1619                                                 clock-output-names = "clk_tsp";
1620                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1621                                                 #clock-cells = <0>;
1622                                                 rockchip,clkops-idx =
1623                                                         <CLKOPS_RATE_MUX_DIV>;
1624                                         };
1625
1626                                         /* reg[5]: reserved */
1627
1628                                         clk_tsp: clk_tsp_mux {
1629                                                 compatible = "rockchip,rk3188-mux-con";
1630                                                 rockchip,bits = <6 2>;
1631                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1632                                                 clock-output-names = "clk_tsp";
1633                                                 #clock-cells = <0>;
1634                                         };
1635
1636                                         clk_tspout_div: clk_tspout_div {
1637                                                 compatible = "rockchip,rk3188-div-con";
1638                                                 rockchip,bits = <8 5>;
1639                                                 clocks = <&clk_tspout>;
1640                                                 clock-output-names = "clk_tspout";
1641                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1642                                                 #clock-cells = <0>;
1643                                                 rockchip,clkops-idx =
1644                                                         <CLKOPS_RATE_MUX_DIV>;
1645                                         };
1646
1647                                         /* reg[13]: reserved */
1648
1649                                         clk_tspout: clk_tspout_mux {
1650                                                 compatible = "rockchip,rk3188-mux-con";
1651                                                 rockchip,bits = <14 2>;
1652                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
1653                                                 clock-output-names = "clk_tspout";
1654                                                 #clock-cells = <0>;
1655                                         };
1656                                 };
1657
1658                                 clk_sel_con36: sel-con@00f0 {
1659                                         compatible = "rockchip,rk3188-selcon";
1660                                         reg = <0x00f0 0x4>;
1661                                         #address-cells = <1>;
1662                                         #size-cells = <1>;
1663
1664                                         clk_core0: clk_core0_div {
1665                                                 compatible = "rockchip,rk3188-div-con";
1666                                                 rockchip,bits = <0 3>;
1667                                                 clocks = <&clk_core>;
1668                                                 clock-output-names = "clk_core0";
1669                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1670                                                 #clock-cells = <0>;
1671                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1672                                         };
1673
1674                                         /* reg[3]: reserved */
1675
1676                                         clk_core1: clk_core1_div {
1677                                                 compatible = "rockchip,rk3188-div-con";
1678                                                 rockchip,bits = <4 3>;
1679                                                 clocks = <&clk_core>;
1680                                                 clock-output-names = "clk_core1";
1681                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1682                                                 #clock-cells = <0>;
1683                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1684                                         };
1685
1686                                         /* reg[7]: reserved */
1687
1688                                         clk_core2: clk_core2_div {
1689                                                 compatible = "rockchip,rk3188-div-con";
1690                                                 rockchip,bits = <8 3>;
1691                                                 clocks = <&clk_core>;
1692                                                 clock-output-names = "clk_core2";
1693                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1694                                                 #clock-cells = <0>;
1695                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1696                                         };
1697
1698                                         /* reg[11]: reserved */
1699
1700                                         clk_core3: clk_core3_div {
1701                                                 compatible = "rockchip,rk3188-div-con";
1702                                                 rockchip,bits = <12 3>;
1703                                                 clocks = <&clk_core>;
1704                                                 clock-output-names = "clk_core3";
1705                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1706                                                 #clock-cells = <0>;
1707                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1708                                         };
1709
1710                                         /* reg[15]: reserved */
1711                                 };
1712
1713                                 clk_sel_con37: sel-con@00f4 {
1714                                         compatible = "rockchip,rk3188-selcon";
1715                                         reg = <0x00f4 0x4>;
1716                                         #address-cells = <1>;
1717                                         #size-cells = <1>;
1718
1719                                         clk_l2ram: clk_l2ram_div {
1720                                                 compatible = "rockchip,rk3188-div-con";
1721                                                 rockchip,bits = <0 3>;
1722                                                 clocks = <&clk_core>;
1723                                                 clock-output-names = "clk_l2ram";
1724                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1725                                                 #clock-cells = <0>;
1726                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1727                                         };
1728
1729                                         /* reg[3]: reserved */
1730
1731                                         atclk_core: atclk_core_div {
1732                                                 compatible = "rockchip,rk3188-div-con";
1733                                                 rockchip,bits = <4 5>;
1734                                                 clocks = <&clk_core>;
1735                                                 clock-output-names = "atclk_core";
1736                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1737                                                 #clock-cells = <0>;
1738                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1739                                         };
1740
1741                                         pclk_dbg_src: pclk_core_dbg_div {
1742                                                 compatible = "rockchip,rk3188-div-con";
1743                                                 rockchip,bits = <9 5>;
1744                                                 clocks = <&clk_core>;
1745                                                 clock-output-names = "pclk_dbg_src";
1746                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1747                                                 #clock-cells = <0>;
1748                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1749                                         };
1750
1751                                         /* reg[15:14]: reserved */
1752                                 };
1753
1754                                 clk_sel_con38: sel-con@00f8 {
1755                                         compatible = "rockchip,rk3188-selcon";
1756                                         reg = <0x00f8 0x4>;
1757                                         #address-cells = <1>;
1758                                         #size-cells = <1>;
1759
1760                                         clk_nandc0_div: clk_nandc0_div {
1761                                                 compatible = "rockchip,rk3188-div-con";
1762                                                 rockchip,bits = <0 5>;
1763                                                 clocks = <&clk_nandc0>;
1764                                                 clock-output-names = "clk_nandc0";
1765                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1766                                                 #clock-cells = <0>;
1767                                                 rockchip,clkops-idx =
1768                                                         <CLKOPS_RATE_MUX_DIV>;
1769                                         };
1770
1771                                         /* reg[6:5]: reserved */
1772
1773                                         clk_nandc0: clk_nandc0_mux {
1774                                                 compatible = "rockchip,rk3188-mux-con";
1775                                                 rockchip,bits = <7 1>;
1776                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1777                                                 clock-output-names = "clk_nandc0";
1778                                                 #clock-cells = <0>;
1779                                         };
1780
1781                                         clk_nandc1_div: clk_nandc1_div {
1782                                                 compatible = "rockchip,rk3188-div-con";
1783                                                 rockchip,bits = <8 5>;
1784                                                 clocks = <&clk_nandc1>;
1785                                                 clock-output-names = "clk_nandc1";
1786                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1787                                                 #clock-cells = <0>;
1788                                                 rockchip,clkops-idx =
1789                                                         <CLKOPS_RATE_MUX_DIV>;
1790                                         };
1791
1792                                         /* reg[14:13]: reserved */
1793
1794                                         clk_nandc1: clk_nandc1_mux {
1795                                                 compatible = "rockchip,rk3188-mux-con";
1796                                                 rockchip,bits = <15 1>;
1797                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1798                                                 clock-output-names = "clk_nandc1";
1799                                                 #clock-cells = <0>;
1800                                         };
1801                                 };
1802
1803                                 clk_sel_con39: sel-con@00fc {
1804                                         compatible = "rockchip,rk3188-selcon";
1805                                         reg = <0x00fc 0x4>;
1806                                         #address-cells = <1>;
1807                                         #size-cells = <1>;
1808
1809                                         clk_spi2_div: clk_spi2_div {
1810                                                 compatible = "rockchip,rk3188-div-con";
1811                                                 rockchip,bits = <0 7>;
1812                                                 clocks = <&clk_spi2>;
1813                                                 clock-output-names = "clk_spi2";
1814                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1815                                                 #clock-cells = <0>;
1816                                                 rockchip,clkops-idx =
1817                                                         <CLKOPS_RATE_MUX_DIV>;
1818                                         };
1819
1820                                         clk_spi2: clk_spi2_mux {
1821                                                 compatible = "rockchip,rk3188-mux-con";
1822                                                 rockchip,bits = <7 1>;
1823                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1824                                                 clock-output-names = "clk_spi2";
1825                                                 #clock-cells = <0>;
1826                                         };
1827
1828                                         aclk_hevc_div: aclk_hevc_div {
1829                                                 compatible = "rockchip,rk3188-div-con";
1830                                                 rockchip,bits = <8 5>;
1831                                                 clocks = <&aclk_hevc>;
1832                                                 clock-output-names = "aclk_hevc";
1833                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1834                                                 #clock-cells = <0>;
1835                                                 rockchip,clkops-idx =
1836                                                         <CLKOPS_RATE_MUX_DIV>;
1837                                         };
1838
1839                                         /* reg[13]: reserved */
1840
1841                                         aclk_hevc: aclk_hevc_mux {
1842                                                 compatible = "rockchip,rk3188-mux-con";
1843                                                 rockchip,bits = <14 2>;
1844                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1845                                                 clock-output-names = "aclk_hevc";
1846                                                 #clock-cells = <0>;
1847                                         };
1848                                 };
1849
1850                                 clk_sel_con40: sel-con@0100 {
1851                                         compatible = "rockchip,rk3188-selcon";
1852                                         reg = <0x0100 0x4>;
1853                                         #address-cells = <1>;
1854                                         #size-cells = <1>;
1855
1856                                         spdif_8ch_div: spdif_8ch_div {
1857                                                 compatible = "rockchip,rk3188-div-con";
1858                                                 rockchip,bits = <0 7>;
1859                                                 clocks = <&clk_spdif_pll>;
1860                                                 clock-output-names = "spdif_8ch_div";
1861                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1862                                                 #clock-cells = <0>;
1863                                         };
1864
1865                                         /* reg[7]: reserved */
1866
1867                                         clk_spdif_8ch: spdif_8ch_clk_mux {
1868                                                 compatible = "rockchip,rk3188-mux-con";
1869                                                 rockchip,bits = <8 2>;
1870                                                 clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>;
1871                                                 clock-output-names = "clk_spdif_8ch";
1872                                                 #clock-cells = <0>;
1873                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1874                                         };
1875
1876                                         /* reg[11:10]: reserved */
1877
1878                                         hclk_hevc: hclk_hevc_div {
1879                                                 compatible = "rockchip,rk3188-div-con";
1880                                                 rockchip,bits = <12 2>;
1881                                                 clocks = <&aclk_hevc>;
1882                                                 clock-output-names = "hclk_hevc";
1883                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1884                                                 #clock-cells = <0>;
1885                                         };
1886
1887                                         /* reg[15:14]: reserved */
1888                                 };
1889
1890                                 clk_sel_con41: sel-con@0104 {
1891                                         compatible = "rockchip,rk3188-selcon";
1892                                         reg = <0x0104 0x4>;
1893                                         #address-cells = <1>;
1894                                         #size-cells = <1>;
1895
1896                                         spdif_8ch_frac: spdif_8ch_frac {
1897                                                 compatible = "rockchip,rk3188-frac-con";
1898                                                 clocks = <&spdif_8ch_div>;
1899                                                 clock-output-names = "spdif_8ch_frac";
1900                                                 /* numerator    denominator */
1901                                                 rockchip,bits = <0 32>;
1902                                                 rockchip,clkops-idx =
1903                                                         <CLKOPS_RATE_FRAC>;
1904                                                 #clock-cells = <0>;
1905                                         };
1906                                 };
1907
1908                                 clk_sel_con42: sel-con@0108 {
1909                                         compatible = "rockchip,rk3188-selcon";
1910                                         reg = <0x0108 0x4>;
1911                                         #address-cells = <1>;
1912                                         #size-cells = <1>;
1913
1914                                         clk_hevc_cabac_div: clk_hevc_cabac_div {
1915                                                 compatible = "rockchip,rk3188-div-con";
1916                                                 rockchip,bits = <0 5>;
1917                                                 clocks = <&clk_hevc_cabac>;
1918                                                 clock-output-names = "clk_hevc_cabac";
1919                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1920                                                 #clock-cells = <0>;
1921                                                 rockchip,clkops-idx =
1922                                                         <CLKOPS_RATE_MUX_DIV>;
1923                                         };
1924
1925                                         /* reg[5]: reserved */
1926
1927                                         clk_hevc_cabac: clk_hevc_cabac_mux {
1928                                                 compatible = "rockchip,rk3188-mux-con";
1929                                                 rockchip,bits = <6 2>;
1930                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1931                                                 clock-output-names = "clk_hevc_cabac";
1932                                                 #clock-cells = <0>;
1933                                         };
1934
1935                                         clk_hevc_core_div: clk_hevc_core_div {
1936                                                 compatible = "rockchip,rk3188-div-con";
1937                                                 rockchip,bits = <8 5>;
1938                                                 clocks = <&clk_hevc_core>;
1939                                                 clock-output-names = "clk_hevc_core";
1940                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1941                                                 #clock-cells = <0>;
1942                                                 rockchip,clkops-idx =
1943                                                         <CLKOPS_RATE_MUX_DIV>;
1944                                         };
1945
1946                                         /* reg[13]: reserved */
1947
1948                                         clk_hevc_core: clk_hevc_core_mux {
1949                                                 compatible = "rockchip,rk3188-mux-con";
1950                                                 rockchip,bits = <14 2>;
1951                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1952                                                 clock-output-names = "clk_hevc_core";
1953                                                 #clock-cells = <0>;
1954                                         };
1955                                 };
1956
1957                         };
1958
1959
1960                         /* Gate control regs */
1961                         clk_gate_cons {
1962                                 compatible = "rockchip,rk-gate-cons";
1963                                 #address-cells = <1>;
1964                                 #size-cells = <1>;
1965                                 ranges ;
1966
1967                                 clk_gates0: gate-clk@0160 {
1968                                         compatible = "rockchip,rk3188-gate-clk";
1969                                         reg = <0x0160 0x4>;
1970                                         clocks =
1971                                                 <&dummy>,               <&clk_apll>,
1972                                                 <&clk_gpll>,    <&aclk_bus>,
1973
1974                                                 <&hclk_bus>,    <&pclk_bus>,
1975                                                 <&dummy>,               <&aclk_bus>,
1976
1977                                                 <&clk_dpll>,    <&clk_gpll>,
1978                                                 <&clk_gpll>,    <&clk_cpll>,
1979
1980                                                 <&xin24m>,              <&dummy>,
1981                                                 <&dummy>,               <&dummy>;
1982
1983                                         clock-output-names =
1984                                                 "reserved",             "core_apll",
1985                                                 "clk_arm_gpll",         "g_aclk_bus",
1986
1987                                                 "hclk_bus",             "pclk_bus",
1988                                                 "reserved",             "aclk_bus_2pmu",
1989
1990                                                 "reserved",             "reserved",             /*"clk_ddr_dpll",       "clk_ddr_gpll",*/
1991                                                 "clk_bus_gpll",         "clk_bus_cpll",
1992
1993                                                 "clk_acc_efuse",                "reserved",
1994                                                 "reserved",             "reserved";
1995
1996                                         #clock-cells = <1>;
1997                                 };
1998
1999                                 clk_gates1: gate-clk@0164 {
2000                                         compatible = "rockchip,rk3188-gate-clk";
2001                                         reg = <0x0164 0x4>;
2002                                         clocks =
2003                                                 <&xin24m>,              <&xin24m>,
2004                                                 <&xin24m>,              <&xin24m>,
2005
2006                                                 <&xin24m>,              <&xin24m>,
2007                                                 <&dummy>,               <&dummy>,
2008
2009                                                 <&clk_uart0_pll>,               <&uart0_frac>,
2010                                                 <&clk_uart1_div>,               <&uart1_frac>,
2011
2012                                                 <&clk_uart2_div>,               <&uart2_frac>,
2013                                                 <&clk_uart3_div>,               <&uart3_frac>;
2014
2015                                         clock-output-names =
2016                                                 "clk_timer0",           "clk_timer1",
2017                                                 "clk_timer2",           "clk_timer3",
2018
2019                                                 "clk_timer4",           "clk_timer5",
2020                                                 "reserved",                     "reserved",
2021
2022                                                 "clk_uart0_pll",        "uart0_frac",
2023                                                 "clk_uart1_div",        "uart1_frac",
2024
2025                                                 "clk_uart2_div",        "uart2_frac",
2026                                                 "clk_uart3_div",        "uart3_frac";
2027
2028                                         #clock-cells = <1>;
2029                                 };
2030
2031                                 clk_gates2: gate-clk@0168 {
2032                                         compatible = "rockchip,rk3188-gate-clk";
2033                                         reg = <0x0168 0x4>;
2034                                         clocks =
2035                                                 <&aclk_peri>,           <&aclk_peri>,
2036                                                 <&hclk_peri>,           <&pclk_peri>,
2037
2038                                                 <&dummy>,               <&clk_mac_pll>,
2039                                                 <&clk_hsadc_pll>,               <&clk_tsadc>,
2040
2041                                                 <&clk_saradc>,          <&clk_spi0>,
2042                                                 <&clk_spi1>,            <&clk_spi2>,
2043
2044                                                 <&clk_uart4_div>,               <&uart4_frac>,
2045                                                 <&dummy>,               <&dummy>;
2046
2047                                         clock-output-names =
2048                                                 "aclk_peri",            "g_aclk_periph",
2049                                                 "hclk_peri",            "pclk_peri",
2050
2051                                                 "reserved",             "clk_mac_pll",
2052                                                 "clk_hsadc_pll",                "clk_tsadc",
2053
2054                                                 "clk_saradc",           "clk_spi0",
2055                                                 "clk_spi1",             "clk_spi2",
2056
2057                                                 "clk_uart4_div",                "uart4_frac",
2058                                                 "reserved",             "reserved";
2059
2060                                         #clock-cells = <1>;
2061                                 };
2062
2063                                 clk_gates3: gate-clk@016c {
2064                                         compatible = "rockchip,rk3188-gate-clk";
2065                                         reg = <0x016c 0x4>;
2066                                         clocks =
2067                                                 <&aclk_vio0>,           <&dclk_lcdc0>,
2068                                                 <&aclk_vio1>,           <&dclk_lcdc1>,
2069
2070                                                 <&clk_rga>,                     <&aclk_rga>,
2071                                                 <&hsicphy_480m>,                <&clk_cif_pll>,
2072
2073                                                 <&dummy>,               <&clk_vepu>,
2074                                                 <&dummy>,               <&clk_vdpu>,
2075
2076                                                 <&clk_edp_24m>,         <&clk_edp>,
2077                                                 <&clk_isp>,             <&clk_isp_jpe>;
2078
2079                                         clock-output-names =
2080                                                 "aclk_vio0",            "dclk_lcdc0",
2081                                                 "aclk_vio1",            "dclk_lcdc1",
2082
2083                                                 "clk_rga",              "aclk_rga",
2084                                                 "hsicphy_480m",         "clk_cif_pll",
2085
2086                                                 /*Not use hclk_vpu_gate tmp, fixme*/
2087                                                 "reserved",             "clk_vepu",
2088                                                 "reserved",             "clk_vdpu",
2089
2090                                                 "clk_edp_24m",          "clk_edp",
2091                                                 "clk_isp",              "clk_isp_jpe";
2092
2093                                         #clock-cells = <1>;
2094                                 };
2095
2096                                 clk_gates4: gate-clk@0170 {
2097                                         compatible = "rockchip,rk3188-gate-clk";
2098                                         reg = <0x0170 0x4>;
2099                                         clocks =
2100                                                 <&clk_i2s0_out>,                <&clk_i2s_pll>,
2101                                                 <&i2s0_frac>,           <&clk_i2s0>,
2102
2103                                                 <&spdif_div>,           <&spdif_frac>,
2104                                                 <&clk_spdif>,           <&spdif_8ch_div>,
2105
2106                                                 <&spdif_8ch_frac>,              <&clk_spdif_8ch>,
2107                                                 <&clk_tsp>,             <&clk_tspout>,
2108
2109                                                 <&clk_ddr>,             <&clk_ddr>,
2110                                                 <&jtag_clkin>,          <&dummy>;
2111
2112                                         clock-output-names =
2113                                                 "clk_i2s0_out",         "clk_i2s_pll",
2114                                                 "i2s0_frac",            "g_clk_i2s0",
2115
2116                                                 "spdif_div",            "spdif_frac",
2117                                                 "clk_spdif",            "spdif_8ch_div",
2118
2119                                                 "spdif_8ch_frac",               "clk_spdif_8ch",
2120                                                 "clk_tsp",              "clk_tspout",
2121
2122                                                 /* Not use these ddr gates */
2123                                                 "reserved",             "reserved",        /*"g_clk_ddrphy0",           "g_clk_ddrphy1",*/
2124                                                 "clk_jtag",             "reserved";             /*"testclk_gate_en";*/
2125
2126                                         #clock-cells = <1>;
2127                                 };
2128
2129                                 clk_gates5: gate-clk@0174 {
2130                                         compatible = "rockchip,rk3188-gate-clk";
2131                                         reg = <0x0174 0x4>;
2132                                         clocks =
2133                                                 <&clk_mac>,             <&clk_mac>,
2134                                                 <&clk_mac>,             <&clk_mac>,
2135
2136                                                 <&clk_crypto>,          <&clk_nandc0>,
2137                                                 <&clk_nandc1>,          <&clk_gpu>,
2138
2139                                                 <&pclk_pd_pmu>,         <&dummy>,
2140                                                 <&dummy>,               <&xin32k>,
2141
2142                                                 <&xin24m>,              <&xin24m>,
2143                                                 <&usbphy_480m>,         <&dummy>;
2144
2145                                         clock-output-names =
2146                                                 "g_clk_mac_rx",         "g_clk_mac_tx",
2147                                                 "g_clk_mac_ref",        "g_mac_refout",
2148
2149                                                 "clk_crypto",           "clk_nandc0",
2150                                                 "clk_nandc1",           "clk_gpu",
2151
2152                                                 "pclk_pd_pmu",          "g_clk_pvtm_core",
2153                                                 "g_clk_pvtm_gpu",               "g_hdmi_cec_clk",
2154
2155                                                 "g_hdmi_hdcp_clk",              "g_ps2c_clk",
2156                                                 "usbphy_480m",          "g_mipidsi_24m";
2157
2158                                         #clock-cells = <1>;
2159                                 };
2160
2161                                 clk_gates6: gate-clk@0178 {
2162                                         compatible = "rockchip,rk3188-gate-clk";
2163                                         reg = <0x0178 0x4>;
2164                                         clocks =
2165                                                 <&hclk_peri>,           <&pclk_peri>,
2166                                                 <&aclk_peri>,           <&aclk_peri>,
2167
2168                                                 <&pclk_peri>,           <&pclk_peri>,
2169                                                 <&pclk_peri>,           <&pclk_peri>,
2170
2171                                                 <&pclk_peri>,           <&pclk_peri>,
2172                                                 <&dummy>,                       <&pclk_peri>,
2173
2174                                                 <&pclk_peri>,           <&pclk_peri>,
2175                                                 <&pclk_peri>,           <&pclk_peri>;
2176
2177                                         clock-output-names =
2178                                                 "g_hp_matrix",          "g_pp_axi_matrix",
2179                                                 "g_ap_axi_matrix",              "g_aclk_dmac2",
2180
2181                                                 "g_pclk_spi0",          "g_pclk_spi1",
2182                                                 "g_pclk_spi2",          "g_pclk_ps2c",
2183
2184                                                 "g_pclk_uart0",         "g_pclk_uart1",
2185                                                 "reserved",             "g_pclk_uart2",
2186
2187                                                 "g_pclk_uart3",         "g_pclk_i2c2",
2188                                                 "g_pclk_i2c3",          "g_pclk_i2c4";
2189
2190                                         #clock-cells = <1>;
2191                                 };
2192
2193                                 clk_gates7: gate-clk@017c {
2194                                         compatible = "rockchip,rk3188-gate-clk";
2195                                         reg = <0x017c 0x4>;
2196                                         clocks =
2197                                                 <&pclk_peri>,           <&pclk_peri>,
2198                                                 <&pclk_peri>,           <&pclk_peri>,
2199
2200                                                 <&hclk_peri>,           <&hclk_peri>,
2201                                                 <&hclk_peri>,           <&hclk_peri>,
2202
2203                                                 <&hclk_peri>,           <&hclk_peri>,
2204                                                 <&hclk_peri>,           <&aclk_peri>,
2205
2206                                                 <&hclk_peri>,           <&hclk_peri>,
2207                                                 <&hclk_peri>,           <&hclk_peri>;
2208
2209                                         clock-output-names =
2210                                                 "g_pclk_i2c5",          "g_pclk_saradc",
2211                                                 "g_pclk_tsadc",         "g_pclk_sim",
2212
2213                                                 "g_hclk_otg0",          "g_pmu_hclk_otg0",
2214                                                 "g_hclk_host0",         "g_hclk_host1",
2215
2216                                                 "g_hclk_hsic",          "g_hclk_usb_peri",
2217                                                 "g_hp_ahb_arbi",                "g_aclk_peri_niu",
2218
2219                                                 "g_h_emem_peri",                "g_hclk_mem_peri",
2220                                                 "g_hclk_nandc0",                "g_hclk_nandc1";
2221
2222                                         #clock-cells = <1>;
2223                                 };
2224
2225                                 clk_gates8: gate-clk@0180 {
2226                                         compatible = "rockchip,rk3188-gate-clk";
2227                                         reg = <0x0180 0x4>;
2228                                         clocks =
2229                                                 <&aclk_peri>,           <&pclk_peri>,
2230                                                 <&aclk_peri>,           <&hclk_peri>,
2231
2232                                                 <&hclk_peri>,           <&hclk_peri>,
2233                                                 <&hclk_peri>,           <&hclk_peri>,
2234
2235                                                 <&hclk_peri>,           <&dummy>,
2236                                                 <&dummy>,               <&dummy>,
2237
2238                                                 <&aclk_peri>,           <&dummy>,
2239                                                 <&dummy>,               <&dummy>;
2240
2241                                         clock-output-names =
2242                                                 "g_aclk_gmac",          "g_pclk_gmac",
2243                                                 "g_hclk_gps",           "g_hclk_sdmmc",
2244
2245                                                 "g_hclk_sdio0",         "g_hclk_sdio1",
2246                                                 "g_hclk_emmc",          "g_hclk_hsadc",
2247
2248                                                 "g_hclk_tsp",           "g_hsadc_0_tsp",
2249                                                 "g_hsadc_1_tsp",                "g_clk_27m_tsp",
2250
2251                                                 "g_aclk_peri_mmu",              "reserved",
2252                                                 "reserved",             "reserved";
2253
2254                                         #clock-cells = <1>;
2255                                 };
2256
2257                                 clk_gates9: gate-clk@0184 {
2258                                         compatible = "rockchip,rk3188-gate-clk";
2259                                         reg = <0x0184 0x4>;
2260                                         clocks =
2261                                                 <&dummy>,               <&dummy>,
2262                                                 <&dummy>,               <&dummy>,
2263
2264                                                 <&dummy>,               <&dummy>,
2265                                                 <&dummy>,               <&dummy>,
2266
2267                                                 <&dummy>,               <&dummy>,
2268                                                 <&dummy>,               <&dummy>,
2269
2270                                                 <&dummy>,               <&dummy>,
2271                                                 <&dummy>,               <&dummy>;
2272
2273                                         clock-output-names =
2274                                                 "reserved",             "reserved",             /*"aclk_video_gate_en", "hclk_video_clock_en",*/
2275                                                 "reserved",             "reserved",
2276
2277                                                 "reserved",             "reserved",
2278                                                 "reserved",             "reserved",
2279
2280                                                 "reserved",             "reserved",
2281                                                 "reserved",             "reserved",
2282
2283                                                 "reserved",             "reserved",
2284                                                 "reserved",             "reserved";
2285
2286                                         #clock-cells = <1>;
2287                                 };
2288
2289                                 clk_gates10: gate-clk@0188 {
2290                                         compatible = "rockchip,rk3188-gate-clk";
2291                                         reg = <0x0188 0x4>;
2292                                         clocks =
2293                                                 <&pclk_bus>,            <&pclk_bus>,
2294                                                 <&pclk_bus>,            <&pclk_bus>,
2295
2296                                                 <&aclk_bus>,            <&dummy>,
2297                                                 <&dummy>,               <&dummy>,
2298
2299                                                 <&hclk_bus>,            <&hclk_bus>,
2300                                                 <&hclk_bus>,            <&hclk_bus>,
2301
2302                                                 <&aclk_bus>,            <&aclk_bus>,
2303                                                 <&pclk_bus>,            <&pclk_bus>;
2304
2305                                         clock-output-names =
2306                                                 "g_pclk_pwm",           "g_pclk_timer",
2307                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
2308
2309                                                 "g_aclk_intmem",                "g_clk_intmem0",
2310                                                 "g_clk_intmem1",                "g_clk_intmem2",
2311
2312                                                 "g_hclk_i2s",           "g_hclk_rom",
2313                                                 "g_hclk_spdif",         "g_h_spdif_8ch",
2314
2315                                                 "g_aclk_dmac1",         "g_aclk_strc_sys",
2316                                                 "g_p_ddrupctl0",                "g_pclk_publ0";
2317
2318                                         #clock-cells = <1>;
2319                                 };
2320
2321                                 clk_gates11: gate-clk@018c {
2322                                         compatible = "rockchip,rk3188-gate-clk";
2323                                         reg = <0x018c 0x4>;
2324                                         clocks =
2325                                                 <&pclk_bus>,            <&pclk_bus>,
2326                                                 <&pclk_bus>,            <&pclk_bus>,
2327
2328                                                 <&dummy>,               <&dummy>,
2329                                                 <&aclk_bus>,            <&hclk_bus>,
2330
2331                                                 <&aclk_bus>,            <&pclk_bus>,
2332                                                 <&pclk_bus>,            <&pclk_bus>,
2333
2334                                                 <&dummy>,               <&dummy>,
2335                                                 <&dummy>,               <&dummy>;
2336
2337                                         clock-output-names =
2338                                                 "g_p_ddrupctl1",                "g_pclk_publ1",
2339                                                 "g_p_efuse_1024",               "g_pclk_tzpc",
2340
2341                                                 "reserved",             "reserved",             /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
2342                                                 "g_aclk_crypto",                "g_hclk_crypto",
2343
2344                                                 "g_aclk_ccp",   "g_pclk_uart2",
2345                                                 "g_p_efuse_256",        "g_pclk_rkpwm",
2346
2347                                                 "reserved",             "reserved",
2348                                                 "reserved",             "reserved";
2349
2350                                         #clock-cells = <1>;
2351                                 };
2352
2353                                 clk_gates12: gate-clk@0190 {
2354                                         compatible = "rockchip,rk3188-gate-clk";
2355                                         reg = <0x0190 0x4>;
2356                                         clocks =
2357                                                 <&clk_core0>,           <&clk_core1>,
2358                                                 <&clk_core2>,           <&clk_core3>,
2359
2360                                                 <&clk_l2ram>,           <&aclk_core_m0>,
2361                                                 <&aclk_core_mp>,                <&atclk_core>,
2362
2363                                                 <&pclk_dbg_src>,                <&clk_gates12 8>,
2364                                                 <&clk_gates12 8>,               <&clk_gates12 8>,
2365
2366                                                 <&dummy>,               <&dummy>,
2367                                                 <&dummy>,               <&dummy>;
2368
2369                                         clock-output-names =
2370                                                 "clk_core0",            "clk_core1",
2371                                                 "clk_core2",            "clk_core3",
2372
2373                                                 "clk_l2ram",            "aclk_core_m0",
2374                                                 "aclk_core_mp",         "atclk_core",
2375
2376                                                 "pclk_dbg_src",         "g_dbg_core_clk",
2377                                                 "g_cs_dbg_clk",         "g_pclk_core_niu",
2378
2379                                                 "reserved",             "reserved",
2380                                                 "reserved",             "reserved";
2381
2382                                         #clock-cells = <1>;
2383                                 };
2384
2385                                 clk_gates13: gate-clk@0194 {
2386                                         compatible = "rockchip,rk3188-gate-clk";
2387                                         reg = <0x0194 0x4>;
2388                                         clocks =
2389                                                 <&clk_sdmmc0>,          <&clk_sdio0>,
2390                                                 <&clk_sdio1>,           <&clk_emmc>,
2391
2392                                                 <&xin24m>,              <&xin24m>,
2393                                                 <&xin24m>,              <&xin32k>,
2394
2395                                                 <&aclk_bus_src>,                <&xin12m>,
2396                                                 <&dummy>,               <&dummy>,
2397
2398                                                 <&dummy>,               <&aclk_hevc>,
2399                                                 <&clk_hevc_cabac>,              <&clk_hevc_core>;
2400
2401                                         clock-output-names =
2402                                                 "clk_sdmmc0",           "clk_sdio0",
2403                                                 "clk_sdio1",            "clk_emmc",
2404
2405                                                 "clk_otgphy0",          "clk_otgphy1",
2406                                                 "clk_otgphy2",          "clk_otg_adp",
2407
2408                                                 "g_clk_c2c_host",               "g_clk_hsic_12m",
2409                                                 "g_clk_lcdc_pwm0",              "g_clk_lcdc_pwm1",
2410
2411                                                 "g_clk_wifi",           "aclk_hevc",
2412                                                 "clk_hevc_cabac",               "clk_hevc_core";
2413
2414                                         #clock-cells = <1>;
2415                                 };
2416
2417                                 clk_gates14: gate-clk@0198 {
2418                                         compatible = "rockchip,rk3188-gate-clk";
2419                                         reg = <0x0198 0x4>;
2420                                         clocks =
2421                                                 <&dummy>,               <&pclk_pd_alive>,
2422                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2423
2424                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2425                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2426
2427                                                 <&pclk_pd_alive>,               <&dummy>,
2428                                                 <&dummy>,               <&pclk_pd_alive>,
2429
2430                                                 <&pclk_pd_alive>,               <&dummy>,
2431                                                 <&dummy>,               <&dummy>;
2432
2433                                         clock-output-names =
2434                                                 "reserved",             "g_pclk_gpio1",
2435                                                 "g_pclk_gpio2",         "g_pclk_gpio3",
2436
2437                                                 "g_pclk_gpio4",         "g_pclk_gpio5",
2438                                                 "g_pclk_gpio6",         "g_pclk_gpio7",
2439
2440                                                 "g_pclk_gpio8",         "reserved",
2441                                                 "reserved",             "g_pclk_grf",
2442
2443                                                 "g_p_alive_niu",                "reserved",
2444                                                 "reserved",             "reserved";
2445
2446                                         #clock-cells = <1>;
2447                                 };
2448
2449                                 clk_gates15: gate-clk@019c {
2450                                         compatible = "rockchip,rk3188-gate-clk";
2451                                         reg = <0x019c 0x4>;
2452                                         clocks =
2453                                                 <&aclk_rga>,            <&hclk_vio>,
2454                                                 <&aclk_vio0>,           <&hclk_vio>,
2455
2456                                                 <&dummy>,               <&aclk_vio0>,
2457                                                 <&hclk_vio>,            <&aclk_vio1>,
2458
2459                                                 <&hclk_vio>,            <&hclk_vio>,
2460                                                 <&hclk_vio>,            <&aclk_vio0>,
2461
2462                                                 <&aclk_vio1>,           <&aclk_rga>,
2463                                                 <&aclk_vio0>,           <&hclk_vio>;
2464
2465                                         clock-output-names =
2466                                                 "g_aclk_rga",           "g_hclk_rga",
2467                                                 "g_aclk_iep",           "g_hclk_iep",
2468
2469                                                 "g_aclk_lcdc_iep",              "g_aclk_lcdc0",
2470                                                 "g_hclk_lcdc0",         "g_aclk_lcdc1",
2471
2472                                                 "g_hclk_lcdc1",         "g_h_vio_ahb",
2473                                                 "g_hclk_vio_niu",               "g_aclk_vio0_niu",
2474
2475                                                 "g_aclk_vio1_niu",              "g_aclk_vio2_niu",
2476                                                 "g_aclk_vip",           "g_hclk_vip";
2477
2478                                         #clock-cells = <1>;
2479                                 };
2480
2481                                 clk_gates16: gate-clk@01a0 {
2482                                         compatible = "rockchip,rk3188-gate-clk";
2483                                         reg = <0x01a0 0x4>;
2484                                         clocks =
2485                                                 <&pclkin_cif>,          <&hclk_vio>,
2486                                                 <&aclk_vio1>,           <&pclkin_isp>,
2487
2488                                                 <&hclk_vio>,            <&hclk_vio>,
2489                                                 <&hclk_vio>,            <&hclk_vio>,
2490
2491                                                 <&hclk_vio>,            <&hclk_vio>,
2492                                                 <&hclk_vio>,            <&hclk_vio>,
2493
2494                                                 <&dummy>,               <&dummy>,
2495                                                 <&dummy>,               <&dummy>;
2496
2497                                         clock-output-names =
2498                                                 "g_pclkin_cif",         "g_hclk_isp",
2499                                                 "g_aclk_isp",           "g_pclkin_isp",
2500
2501                                                 "g_p_mipi_dsi0",                "g_p_mipi_dsi1",
2502                                                 "g_p_mipi_csi",         "g_pclk_lvds_phy",
2503
2504                                                 "g_pclk_edp_ctrl",              "g_p_hdmi_ctrl",
2505                                                 "g_hclk_vio2_h2p",              "g_pclk_vio2_h2p",
2506
2507                                                 "reserved",             "reserved",
2508                                                 "reserved",             "reserved";
2509
2510                                         #clock-cells = <1>;
2511                                 };
2512
2513                                 clk_gates17: gate-clk@01a4 {
2514                                         compatible = "rockchip,rk3188-gate-clk";
2515                                         reg = <0x01a4 0x4>;
2516                                         clocks =
2517                                                 <&pclk_pd_pmu>,         <&pclk_pd_pmu>,
2518                                                 <&pclk_pd_pmu>,         <&pclk_pd_pmu>,
2519
2520                                                 <&pclk_pd_pmu>,         <&dummy>,
2521                                                 <&dummy>,               <&dummy>,
2522
2523                                                 <&dummy>,               <&dummy>,
2524                                                 <&dummy>,               <&dummy>,
2525
2526                                                 <&dummy>,               <&dummy>,
2527                                                 <&dummy>,               <&dummy>;
2528
2529                                         clock-output-names =
2530                                                 "g_pclk_pmu",           "g_pclk_intmem1",
2531                                                 "g_pclk_pmu_niu",               "g_pclk_sgrf",
2532
2533                                                 "g_pclk_gpio0",         "reserved",
2534                                                 "reserved",             "reserved",
2535
2536                                                 "reserved",             "reserved",
2537                                                 "reserved",             "reserved",
2538
2539                                                 "reserved",             "reserved",
2540                                                 "reserved",             "reserved";
2541
2542                                         #clock-cells = <1>;
2543                                 };
2544
2545                                 clk_gates18: gate-clk@01a8 {
2546                                         compatible = "rockchip,rk3188-gate-clk";
2547                                         reg = <0x01a8 0x4>;
2548                                         clocks =
2549                                                 <&clk_gpu>,             <&dummy>,
2550                                                 <&dummy>,               <&dummy>,
2551
2552                                                 <&dummy>,               <&dummy>,
2553                                                 <&dummy>,               <&dummy>,
2554
2555                                                 <&dummy>,               <&dummy>,
2556                                                 <&dummy>,               <&dummy>,
2557
2558                                                 <&dummy>,               <&dummy>,
2559                                                 <&dummy>,               <&dummy>;
2560
2561                                         clock-output-names =
2562                                                 "g_aclk_gpu",           "reserved",
2563                                                 "reserved",             "reserved",
2564
2565                                                 "reserved",             "reserved",
2566                                                 "reserved",             "reserved",
2567
2568                                                 "reserved",             "reserved",
2569                                                 "reserved",             "reserved",
2570
2571                                                 "reserved",             "reserved",
2572                                                 "reserved",             "reserved";
2573
2574                                         #clock-cells = <1>;
2575                                 };
2576
2577                         };
2578                 };
2579         };
2580 };