arch/arm/boot/dts/rk3288-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3288.h>
  15
  16 /{
  17         clocks {
  18                 compatible = "rockchip,rk-clocks";
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges = <0x0 0xFF760000 0x01b0>;
  22
  23                 fixed_rate_cons {
  24                         compatible = "rockchip,rk-fixed-rate-cons";
  25
  26                         xin24m: xin24m {
  27                                 compatible = "rockchip,rk-fixed-clock";
  28                                 clock-output-names = "xin24m";
  29                                 clock-frequency = <24000000>;
  30                                 #clock-cells = <0>;
  31                         };
  32
  33                         xin12m: xin12m {
  34                                 compatible = "rockchip,rk-fixed-clock";
  35                                 clocks = <&xin24m>;
  36                                 clock-output-names = "xin12m";
  37                                 clock-frequency = <12000000>;
  38                                 #clock-cells = <0>;
  39                         };
  40
  41                         xin32k: xin32k {
  42                                 compatible = "rockchip,rk-fixed-clock";
  43                                 clock-output-names = "xin32k";
  44                                 clock-frequency = <32000>;
  45                                 #clock-cells = <0>;
  46                         };
  47
  48                         io_27m_in: io_27m_in {
  49                                 compatible = "rockchip,rk-fixed-clock";
  50                                 clock-output-names = "io_27m_in";
  51                                 clock-frequency = <27000000>;
  52                                 #clock-cells = <0>;
  53                         };
  54
  55                         dummy: dummy {
  56                                 compatible = "rockchip,rk-fixed-clock";
  57                                 clock-output-names = "dummy";
  58                                 clock-frequency = <0>;
  59                                 #clock-cells = <0>;
  60                         };
  61
  62                         i2s_clkin: i2s_clkin {
  63                                 compatible = "rockchip,rk-fixed-clock";
  64                                 clock-output-names = "i2s_clkin";
  65                                 clock-frequency = <0>;
  66                                 #clock-cells = <0>;
  67                         };
  68
  69                         edp_24m_clkin: edp_24m_clkin {
  70                                 compatible = "rockchip,rk-fixed-clock";
  71                                 #clock-cells = <0>;
  72                                 clock-output-names = "edp_24m_clkin";
  73                                 clock-frequency = <0>;
  74                         };
  75
  76                         gmac_clkin: gmac_clkin {
  77                                 compatible = "rockchip,rk-fixed-clock";
  78                                 #clock-cells = <0>;
  79                                 clock-output-names = "gmac_clkin";
  80                                 clock-frequency = <0>;
  81                         };
  82
  83                         clk_hsadc_ext: clk_hsadc_ext {
  84                                 compatible = "rockchip,rk-fixed-clock";
  85                                 #clock-cells = <0>;
  86                                 clock-output-names = "clk_hsadc_ext";
  87                                 clock-frequency = <0>;
  88                         };
  89
  90                         jtag_clkin: jtag_clkin {
  91                                 compatible = "rockchip,rk-fixed-clock";
  92                                 #clock-cells = <0>;
  93                                 clock-output-names = "jtag_clkin";
  94                                 clock-frequency = <0>;
  95                         };
  96
  97                         pclkin_cif: pclkin_cif {
  98                                 compatible = "rockchip,rk-fixed-clock";
  99                                 #clock-cells = <0>;
 100                                 clock-output-names = "pclkin_cif";
 101                                 clock-frequency = <0>;
 102                         };
 103
 104                         pclkin_isp: pclkin_isp {
 105                                 compatible = "rockchip,rk-fixed-clock";
 106                                 #clock-cells = <0>;
 107                                 clock-output-names = "pclkin_isp";
 108                                 clock-frequency = <0>;
 109                         };
 110
 111                         hsadc_0_tsp: hsadc_0_tsp {
 112                                 compatible = "rockchip,rk-fixed-clock";
 113                                 #clock-cells = <0>;
 114                                 clock-output-names = "hsadc_0_tsp";
 115                                 clock-frequency = <0>;
 116                         };
 117
 118                         hsadc_1_tsp: hsadc_1_tsp {
 119                                 compatible = "rockchip,rk-fixed-clock";
 120                                 #clock-cells = <0>;
 121                                 clock-output-names = "hsadc_1_tsp";
 122                                 clock-frequency = <0>;
 123                         };
 124
 125                 };
 126
 127                 fixed_factor_cons {
 128                                 compatible = "rockchip,rk-fixed-factor-cons";
 129
 130                         otgphy0_480m: otgphy0_480m {
 131                                 compatible = "rockchip,rk-fixed-factor-clock";
 132                                 clocks = <&clk_gates13 4>;
 133                                 clock-output-names = "otgphy0_480m";
 134                                 clock-div = <1>;
 135                                 clock-mult = <20>;
 136                                 #clock-cells = <0>;
 137                         };
 138
 139                         otgphy1_480m: otgphy1_480m {
 140                                 compatible = "rockchip,rk-fixed-factor-clock";
 141                                 clocks = <&clk_gates13 5>;
 142                                 clock-output-names = "otgphy1_480m";
 143                                 clock-div = <1>;
 144                                 clock-mult = <20>;
 145                                 #clock-cells = <0>;
 146                         };
 147
 148                         otgphy2_480m: otgphy2_480m {
 149                                 compatible = "rockchip,rk-fixed-factor-clock";
 150                                 clocks = <&clk_gates13 6>;
 151                                 clock-output-names = "otgphy2_480m";
 152                                 clock-div = <1>;
 153                                 clock-mult = <20>;
 154                                 #clock-cells = <0>;
 155                         };
 156
 157                         clk_hsadc_inv: clk_hsadc_inv {
 158                                 compatible = "rockchip,rk-fixed-factor-clock";
 159                                 clocks = <&clk_hsadc_out>;
 160                                 clock-output-names = "clk_hsadc_inv";
 161                                 clock-div = <1>;
 162                                 clock-mult = <1>;
 163                                 #clock-cells = <0>;
 164                         };
 165
 166                         pclkin_cif_inv: pclkin_cif_inv {
 167                                 compatible = "rockchip,rk-fixed-factor-clock";
 168                                 clocks = <&clk_gates16 0>;
 169                                 clock-output-names = "pclkin_cif_inv";
 170                                 clock-div = <1>;
 171                                 clock-mult = <1>;
 172                                 #clock-cells = <0>;
 173                         };
 174
 175                         pclkin_isp_inv: pclkin_isp_inv {
 176                                 compatible = "rockchip,rk-fixed-factor-clock";
 177                                 clocks = <&clk_gates16 3>;
 178                                 clock-output-names = "pclkin_isp_inv";
 179                                 clock-div = <1>;
 180                                 clock-mult = <1>;
 181                                 #clock-cells = <0>;
 182                         };
 183
 184                         hclk_vepu: hclk_vepu {
 185                                 compatible = "rockchip,rk-fixed-factor-clock";
 186                                 clocks = <&clk_vepu>;
 187                                 clock-output-names = "hclk_vepu";
 188                                 clock-div = <4>;
 189                                 clock-mult = <1>;
 190                                 #clock-cells = <0>;
 191                         };
 192
 193                         hclk_vdpu: hclk_vdpu {
 194                                 compatible = "rockchip,rk-fixed-factor-clock";
 195                                 clocks = <&clk_vdpu>;
 196                                 clock-output-names = "hclk_vdpu";
 197                                 clock-div = <4>;
 198                                 clock-mult = <1>;
 199                                 #clock-cells = <0>;
 200                         };
 201                 };
 202
 203                 pd_cons {
 204                         compatible = "rockchip,rk-pd-cons";
 205
 206                         pd_gpu: pd_gpu {
 207                                 compatible = "rockchip,rk-pd-clock";
 208                                 clock-output-names = "pd_gpu";
 209                                 rockchip,pd-id = <CLK_PD_GPU>;
 210                                 #clock-cells = <0>;
 211                         };
 212
 213                         pd_video: pd_video {
 214                                 compatible = "rockchip,rk-pd-clock";
 215                                 clock-output-names = "pd_video";
 216                                 rockchip,pd-id = <CLK_PD_VIDEO>;
 217                                 #clock-cells = <0>;
 218                         };
 219
 220                         pd_vio: pd_vio {
 221                                 compatible = "rockchip,rk-pd-clock";
 222                                 clock-output-names = "pd_vio";
 223                                 rockchip,pd-id = <CLK_PD_VIO>;
 224                                 #clock-cells = <0>;
 225                         };
 226
 227                         pd_hevc: pd_hevc {
 228                                 compatible = "rockchip,rk-pd-clock";
 229                                 clock-output-names = "pd_hevc";
 230                                 rockchip,pd-id = <CLK_PD_HEVC>;
 231                                 #clock-cells = <0>;
 232                         };
 233
 234                         pd_edp: pd_edp {
 235                                 compatible = "rockchip,rk-pd-clock";
 236                                 clocks = <&pd_vio>;
 237                                 clock-output-names = "pd_edp";
 238                                 rockchip,pd-id = <CLK_PD_VIRT>;
 239                                 #clock-cells = <0>;
 240                         };
 241
 242                         pd_vop0: pd_vop0 {
 243                                 compatible = "rockchip,rk-pd-clock";
 244                                 clocks = <&pd_vio>;
 245                                 clock-output-names = "pd_vop0";
 246                                 rockchip,pd-id = <CLK_PD_VIRT>;
 247                                 #clock-cells = <0>;
 248                         };
 249
 250                         pd_vop1: pd_vop1 {
 251                                 compatible = "rockchip,rk-pd-clock";
 252                                 clocks = <&pd_vio>;
 253                                 clock-output-names = "pd_vop1";
 254                                 rockchip,pd-id = <CLK_PD_VIRT>;
 255                                 #clock-cells = <0>;
 256                         };
 257
 258                         pd_isp: pd_isp {
 259                                 compatible = "rockchip,rk-pd-clock";
 260                                 clocks = <&pd_vio>;
 261                                 clock-output-names = "pd_isp";
 262                                 rockchip,pd-id = <CLK_PD_VIRT>;
 263                                 #clock-cells = <0>;
 264                         };
 265
 266                         pd_iep: pd_iep {
 267                                 compatible = "rockchip,rk-pd-clock";
 268                                 clocks = <&pd_vio>;
 269                                 clock-output-names = "pd_iep";
 270                                 rockchip,pd-id = <CLK_PD_VIRT>;
 271                                 #clock-cells = <0>;
 272                         };
 273
 274                         pd_rga: pd_rga {
 275                                 compatible = "rockchip,rk-pd-clock";
 276                                 clocks = <&pd_vio>;
 277                                 clock-output-names = "pd_rga";
 278                                 rockchip,pd-id = <CLK_PD_VIRT>;
 279                                 #clock-cells = <0>;
 280                         };
 281
 282                         pd_mipicsi: pd_mipicsi {
 283                                 compatible = "rockchip,rk-pd-clock";
 284                                 clocks = <&pd_vio>;
 285                                 clock-output-names = "pd_mipicsi";
 286                                 rockchip,pd-id = <CLK_PD_VIRT>;
 287                                 #clock-cells = <0>;
 288                         };
 289
 290                         pd_mipidsi: pd_mipidsi {
 291                                 compatible = "rockchip,rk-pd-clock";
 292                                 clocks = <&pd_vio>;
 293                                 clock-output-names = "pd_mipidsi";
 294                                 rockchip,pd-id = <CLK_PD_VIRT>;
 295                                 #clock-cells = <0>;
 296                         };
 297
 298                         pd_lvds: pd_lvds {
 299                                 compatible = "rockchip,rk-pd-clock";
 300                                 clocks = <&pd_vio>;
 301                                 clock-output-names = "pd_lvds";
 302                                 rockchip,pd-id = <CLK_PD_VIRT>;
 303                                 #clock-cells = <0>;
 304                         };
 305
 306                         pd_hdmi: pd_hdmi {
 307                                 compatible = "rockchip,rk-pd-clock";
 308                                 clocks = <&pd_vio>;
 309                                 clock-output-names = "pd_hdmi";
 310                                 rockchip,pd-id = <CLK_PD_VIRT>;
 311                                 #clock-cells = <0>;
 312                         };
 313
 314                 };
 315
 316
 317                 clock_regs {
 318                         compatible = "rockchip,rk-clock-regs";
 319                         #address-cells = <1>;
 320                         #size-cells = <1>;
 321                         reg = <0x0000 0x3ff>;
 322                         ranges;
 323
 324                         /* PLL control regs */
 325                         pll_cons {
 326                                 compatible = "rockchip,rk-pll-cons";
 327                                 #address-cells = <1>;
 328                                 #size-cells = <1>;
 329                                 ranges ;
 330
 331                                 clk_apll: pll-clk@0000 {
 332                                         compatible = "rockchip,rk3188-pll-clk";
 333                                         reg = <0x0000 0x10>;
 334                                         mode-reg = <0x0050 0>;
 335                                         status-reg = <0x0284 6>;
 336                                         clocks = <&xin24m>;
 337                                         clock-output-names = "clk_apll";
 338                                         rockchip,pll-type = <CLK_PLL_3288_APLL>;
 339                                         #clock-cells = <0>;
 340                                 };
 341
 342                                 clk_dpll: pll-clk@0010 {
 343                                         compatible = "rockchip,rk3188-pll-clk";
 344                                         reg = <0x0010 0x10>;
 345                                         mode-reg = <0x0050 4>;
 346                                         status-reg = <0x0284 5>;
 347                                         clocks = <&xin24m>;
 348                                         clock-output-names = "clk_dpll";
 349                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 350                                         #clock-cells = <0>;
 351                                 };
 352
 353                                 clk_cpll: pll-clk@0020 {
 354                                         compatible = "rockchip,rk3188-pll-clk";
 355                                         reg = <0x0020 0x10>;
 356                                         mode-reg = <0x0050 8>;
 357                                         status-reg = <0x0284 7>;
 358                                         clocks = <&xin24m>;
 359                                         clock-output-names = "clk_cpll";
 360                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 361                                         #clock-cells = <0>;
 362                                         #clock-init-cells = <1>;
 363                                 };
 364
 365                                 clk_gpll: pll-clk@0030 {
 366                                         compatible = "rockchip,rk3188-pll-clk";
 367                                         reg = <0x0030 0x10>;
 368                                         mode-reg = <0x0050 12>;
 369                                         status-reg = <0x0284 8>;
 370                                         clocks = <&xin24m>;
 371                                         clock-output-names = "clk_gpll";
 372                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 373                                         #clock-cells = <0>;
 374                                         #clock-init-cells = <1>;
 375                                 };
 376
 377                                 clk_npll: pll-clk@0040 {
 378                                         compatible = "rockchip,rk3188-pll-clk";
 379                                         reg = <0x0040 0x10>;
 380                                         mode-reg = <0x0050 14>;
 381                                         status-reg = <0x0284 9>;
 382                                         clocks = <&xin24m>;
 383                                         clock-output-names = "clk_npll";
 384                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 385                                         #clock-cells = <0>;
 386                                         #clock-init-cells = <1>;
 387                                 };
 388
 389                         };
 390
 391                         /* Select control regs */
 392                         clk_sel_cons {
 393                                 compatible = "rockchip,rk-sel-cons";
 394                                 #address-cells = <1>;
 395                                 #size-cells = <1>;
 396                                 ranges;
 397
 398                                 clk_sel_con0: sel-con@0060 {
 399                                         compatible = "rockchip,rk3188-selcon";
 400                                         reg = <0x0060 0x4>;
 401                                         #address-cells = <1>;
 402                                         #size-cells = <1>;
 403
 404                                         aclk_core_m0: aclk_core_m0_div {
 405                                                 compatible = "rockchip,rk3188-div-con";
 406                                                 rockchip,bits = <0 4>;
 407                                                 clocks = <&clk_core>;
 408                                                 clock-output-names = "aclk_core_m0";
 409                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 410                                                 #clock-cells = <0>;
 411                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 412                                         };
 413
 414                                         aclk_core_mp: aclk_core_mp_div {
 415                                                 compatible = "rockchip,rk3188-div-con";
 416                                                 rockchip,bits = <4 4>;
 417                                                 clocks = <&clk_core>;
 418                                                 clock-output-names = "aclk_core_mp";
 419                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 420                                                 #clock-cells = <0>;
 421                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 422                                         };
 423
 424                                         clk_core_div: clk_core_div {
 425                                                 compatible = "rockchip,rk3188-div-con";
 426                                                 rockchip,bits = <8 5>;
 427                                                 clocks = <&clk_core>;
 428                                                 clock-output-names = "clk_core";
 429                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 430                                                 #clock-cells = <0>;
 431                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 432                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 433                                                                         CLK_SET_RATE_NO_REPARENT)>;
 434                                         };
 435
 436                                         /* reg[14:13]: reserved */
 437
 438                                         clk_core: clk_core_mux {
 439                                                 compatible = "rockchip,rk3188-mux-con";
 440                                                 rockchip,bits = <15 1>;
 441                                                 clocks = <&clk_apll>, <&clk_gates0 2>;
 442                                                 clock-output-names = "clk_core";
 443                                                 #clock-cells = <0>;
 444                                                 #clock-init-cells = <1>;
 445                                         };
 446
 447                                 };
 448
 449                                 clk_sel_con1: sel-con@0064 {
 450                                         compatible = "rockchip,rk3188-selcon";
 451                                         reg = <0x0064 0x4>;
 452                                         #address-cells = <1>;
 453                                         #size-cells = <1>;
 454
 455                                         aclk_bus: aclk_bus_div {
 456                                                 compatible = "rockchip,rk3188-div-con";
 457                                                 rockchip,bits = <0 3>;
 458                                                 clocks = <&aclk_bus_src_div>;
 459                                                 clock-output-names = "aclk_bus";
 460                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 461                                                 #clock-cells = <0>;
 462                                                 #clock-init-cells = <1>;
 463                                         };
 464
 465                                         aclk_bus_src_div: aclk_bus_src_div {
 466                                                 compatible = "rockchip,rk3188-div-con";
 467                                                 rockchip,bits = <3 5>;
 468                                                 clocks = <&aclk_bus_src>;
 469                                                 clock-output-names = "aclk_bus_src";
 470                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 471                                                 #clock-cells = <0>;
 472                                                 rockchip,clkops-idx =
 473                                                         <CLKOPS_RATE_MUX_DIV>;
 474                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 475                                         };
 476
 477                                         hclk_bus: hclk_bus_div {
 478                                                 compatible = "rockchip,rk3188-div-con";
 479                                                 rockchip,bits = <8 2>;
 480                                                 clocks = <&aclk_bus>;
 481                                                 clock-output-names = "hclk_bus";
 482                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 483                                                 rockchip,div-relations =
 484                                                                 <0x0 1
 485                                                                  0x1 2
 486                                                                  0x3 4>;
 487                                                 #clock-cells = <0>;
 488                                                 #clock-init-cells = <1>;
 489                                         };
 490
 491                                         /* reg[11:10]: reserved */
 492
 493                                         pclk_bus: pclk_bus_div {
 494                                                 compatible = "rockchip,rk3188-div-con";
 495                                                 rockchip,bits = <12 3>;
 496                                                 clocks = <&aclk_bus>;
 497                                                 clock-output-names = "pclk_bus";
 498                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 499                                                 #clock-cells = <0>;
 500                                                 #clock-init-cells = <1>;
 501                                         };
 502
 503                                         aclk_bus_src: aclk_bus_src_mux {
 504                                                 compatible = "rockchip,rk3188-mux-con";
 505                                                 rockchip,bits = <15 1>;
 506                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 507                                                 /*clocks = <&clk_gates0 11>, <&clk_gates0 10>; FIXME*/
 508                                                 clock-output-names = "aclk_bus_src";
 509                                                 #clock-cells = <0>;
 510                                                 #clock-init-cells = <1>;
 511                                         };
 512
 513                                 };
 514
 515                                 clk_sel_con2: sel-con@0068 {
 516                                         compatible = "rockchip,rk3188-selcon";
 517                                         reg = <0x0068 0x4>;
 518                                         #address-cells = <1>;
 519                                         #size-cells = <1>;
 520
 521                                         clk_tsadc: clk_tsadc_div {
 522                                                 compatible = "rockchip,rk3188-div-con";
 523                                                 rockchip,bits = <0 6>;
 524                                                 clocks = <&xin32k>;
 525                                                 clock-output-names = "clk_tsadc";
 526                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 527                                                 #clock-cells = <0>;
 528                                         };
 529
 530                                         /* reg[7:6]: reserved */
 531
 532                                         testout_div: testout_div {
 533                                                 compatible = "rockchip,rk3188-div-con";
 534                                                 rockchip,bits = <8 5>;
 535                                                 clocks = <&dummy>;
 536                                                 clock-output-names = "testout_div";
 537                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 538                                                 #clock-cells = <0>;
 539                                         };
 540
 541                                         /* reg[15:13]: reserved */
 542                                 };
 543
 544                                 clk_sel_con3: sel-con@006c {
 545                                         compatible = "rockchip,rk3188-selcon";
 546                                         reg = <0x006c 0x4>;
 547                                         #address-cells = <1>;
 548                                         #size-cells = <1>;
 549
 550                                         clk_uart4_div: clk_uart4_div {
 551                                                 compatible = "rockchip,rk3188-div-con";
 552                                                 rockchip,bits = <0 7>;
 553                                                 clocks = <&uart_pll_mux>;
 554                                                 clock-output-names = "clk_uart4_div";
 555                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 556                                                 #clock-cells = <0>;
 557                                         };
 558
 559                                         /* reg[7]: reserved */
 560
 561                                         clk_uart4: uart4_mux {
 562                                                 compatible = "rockchip,rk3188-mux-con";
 563                                                 rockchip,bits = <8 2>;
 564                                                 clocks = <&clk_uart4_div>, <&uart4_frac>, <&xin24m>, <&dummy>;
 565                                                 clock-output-names = "clk_uart4";
 566                                                 #clock-cells = <0>;
 567                                                 rockchip,clkops-idx =
 568                                                         <CLKOPS_RATE_RK3288_I2S>;
 569                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 570                                         };
 571
 572                                         /* reg[15:10]: reserved */
 573
 574                                 };
 575
 576                                 clk_sel_con4: sel-con@0070 {
 577                                         compatible = "rockchip,rk3188-selcon";
 578                                         reg = <0x0070 0x4>;
 579                                         #address-cells = <1>;
 580                                         #size-cells = <1>;
 581
 582                                         i2s_pll_div: i2s_pll_div {
 583                                                 compatible = "rockchip,rk3188-div-con";
 584                                                 rockchip,bits = <0 7>;
 585                                                 clocks = <&clk_i2s_pll>;
 586                                                 clock-output-names = "clk_i2s_pll";
 587                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 588                                                 #clock-cells = <0>;
 589                                                 rockchip,clkops-idx =
 590                                                         <CLKOPS_RATE_MUX_DIV>;
 591                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 592                                         };
 593
 594                                         /* reg[7]: reserved */
 595
 596                                         clk_i2s: i2s_mux {
 597                                                 compatible = "rockchip,rk3188-mux-con";
 598                                                 rockchip,bits = <8 2>;
 599                                                 clocks = <&clk_i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
 600                                                 clock-output-names = "clk_i2s";
 601                                                 #clock-cells = <0>;
 602                                                 rockchip,clkops-idx =
 603                                                         <CLKOPS_RATE_RK3288_I2S>;
 604                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 605                                         };
 606
 607                                         /* reg[11:10]: reserved */
 608
 609                                         clk_i2s_out: i2s_outclk_mux {
 610                                                 compatible = "rockchip,rk3188-mux-con";
 611                                                 rockchip,bits = <12 1>;
 612                                                 clocks = <&clk_i2s>, <&xin12m>;
 613                                                 clock-output-names = "clk_i2s_out";
 614                                                 #clock-cells = <0>;
 615                                         };
 616
 617                                         /* reg[14:13]: reserved */
 618
 619                                         clk_i2s_pll: i2s_pll_mux {
 620                                                 compatible = "rockchip,rk3188-mux-con";
 621                                                 rockchip,bits = <15 1>;
 622                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 623                                                 clock-output-names = "clk_i2s_pll";
 624                                                 #clock-cells = <0>;
 625                                                 #clock-init-cells = <1>;
 626                                         };
 627                                 };
 628
 629                                 clk_sel_con5: sel-con@0074 {
 630                                         compatible = "rockchip,rk3188-selcon";
 631                                         reg = <0x0074 0x4>;
 632                                         #address-cells = <1>;
 633                                         #size-cells = <1>;
 634
 635                                         spdif_div: spdif_div {
 636                                                 compatible = "rockchip,rk3188-div-con";
 637                                                 rockchip,bits = <0 7>;
 638                                                 clocks = <&clk_spdif_pll>;
 639                                                 clock-output-names = "spdif_div";
 640                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 641                                                 #clock-cells = <0>;
 642                                         };
 643
 644                                         /* reg[7]: reserved */
 645
 646                                         clk_spdif: spdif_mux {
 647                                                 compatible = "rockchip,rk3188-mux-con";
 648                                                 rockchip,bits = <8 2>;
 649                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>, <&dummy>;
 650                                                 clock-output-names = "clk_spdif";
 651                                                 #clock-cells = <0>;
 652                                                 rockchip,clkops-idx =
 653                                                         <CLKOPS_RATE_RK3288_I2S>;
 654                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 655                                         };
 656
 657                                         /* reg[14:10]: reserved */
 658
 659                                         clk_spdif_pll: spdif_pll_mux {
 660                                                 compatible = "rockchip,rk3188-mux-con";
 661                                                 rockchip,bits = <15 1>;
 662                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 663                                                 clock-output-names = "clk_spdif_pll";
 664                                                 #clock-cells = <0>;
 665                                         };
 666                                 };
 667
 668                                 clk_sel_con6: sel-con@0078 {
 669                                         compatible = "rockchip,rk3188-selcon";
 670                                         reg = <0x0078 0x4>;
 671                                         #address-cells = <1>;
 672                                         #size-cells = <1>;
 673
 674                                         clk_isp_div: clk_isp_div {
 675                                                 compatible = "rockchip,rk3188-div-con";
 676                                                 rockchip,bits = <0 6>;
 677                                                 clocks = <&clk_isp>;
 678                                                 clock-output-names = "clk_isp";
 679                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 680                                                 #clock-cells = <0>;
 681                                                 rockchip,clkops-idx =
 682                                                         <CLKOPS_RATE_MUX_DIV>;
 683                                         };
 684
 685                                         clk_isp: clk_isp_mux {
 686                                                 compatible = "rockchip,rk3188-mux-con";
 687                                                 rockchip,bits = <6 2>;
 688                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
 689                                                 clock-output-names = "clk_isp";
 690                                                 #clock-cells = <0>;
 691                                                 #clock-init-cells = <1>;
 692                                         };
 693
 694                                         clk_isp_jpe_div: clk_isp_jpe_div {
 695                                                 compatible = "rockchip,rk3188-div-con";
 696                                                 rockchip,bits = <8 6>;
 697                                                 clocks = <&clk_isp_jpe>;
 698                                                 clock-output-names = "clk_isp_jpe";
 699                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 700                                                 #clock-cells = <0>;
 701                                                 rockchip,clkops-idx =
 702                                                         <CLKOPS_RATE_MUX_DIV>;
 703                                         };
 704
 705                                         clk_isp_jpe: clk_isp_jpe_mux {
 706                                                 compatible = "rockchip,rk3188-mux-con";
 707                                                 rockchip,bits = <14 2>;
 708                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
 709                                                 clock-output-names = "clk_isp_jpe";
 710                                                 #clock-cells = <0>;
 711                                                 #clock-init-cells = <1>;
 712                                         };
 713                                 };
 714
 715                                 clk_sel_con7: sel-con@007c {
 716                                         compatible = "rockchip,rk3188-selcon";
 717                                         reg = <0x007c 0x4>;
 718                                         #address-cells = <1>;
 719                                         #size-cells = <1>;
 720
 721                                         uart4_frac: uart4_frac {
 722                                                 compatible = "rockchip,rk3188-frac-con";
 723                                                 clocks = <&clk_uart4_div>;
 724                                                 clock-output-names = "uart4_frac";
 725                                                 /* numerator    denominator */
 726                                                 rockchip,bits = <0 32>;
 727                                                 rockchip,clkops-idx =
 728                                                         <CLKOPS_RATE_FRAC>;
 729                                                 #clock-cells = <0>;
 730                                         };
 731                                 };
 732
 733                                 clk_sel_con8: sel-con@0080 {
 734                                         compatible = "rockchip,rk3188-selcon";
 735                                         reg = <0x0080 0x4>;
 736                                         #address-cells = <1>;
 737                                         #size-cells = <1>;
 738
 739                                         i2s_frac: i2s_frac {
 740                                                 compatible = "rockchip,rk3188-frac-con";
 741                                                 clocks = <&clk_i2s_pll>;
 742                                                 clock-output-names = "i2s_frac";
 743                                                 /* numerator    denominator */
 744                                                 rockchip,bits = <0 32>;
 745                                                 rockchip,clkops-idx =
 746                                                         <CLKOPS_RATE_FRAC>;
 747                                                 #clock-cells = <0>;
 748                                         };
 749                                 };
 750
 751                                 clk_sel_con9: sel-con@0084 {
 752                                         compatible = "rockchip,rk3188-selcon";
 753                                         reg = <0x0084 0x4>;
 754                                         #address-cells = <1>;
 755                                         #size-cells = <1>;
 756
 757                                         spdif_frac: spdif_frac {
 758                                                 compatible = "rockchip,rk3188-frac-con";
 759                                                 clocks = <&spdif_div>;
 760                                                 clock-output-names = "spdif_frac";
 761                                                 /* numerator    denominator */
 762                                                 rockchip,bits = <0 32>;
 763                                                 rockchip,clkops-idx =
 764                                                         <CLKOPS_RATE_FRAC>;
 765                                                 #clock-cells = <0>;
 766                                         };
 767                                 };
 768
 769                                 clk_sel_con10: sel-con@0088 {
 770                                         compatible = "rockchip,rk3188-selcon";
 771                                         reg = <0x0088 0x4>;
 772                                         #address-cells = <1>;
 773                                         #size-cells = <1>;
 774
 775                                         aclk_peri_div: aclk_peri_div {
 776                                                 compatible = "rockchip,rk3188-div-con";
 777                                                 rockchip,bits = <0 5>;
 778                                                 clocks = <&aclk_peri>;
 779                                                 clock-output-names = "aclk_peri";
 780                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 781                                                 #clock-cells = <0>;
 782                                                 rockchip,clkops-idx =
 783                                                         <CLKOPS_RATE_MUX_DIV>;
 784                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 785                                         };
 786
 787                                         /* reg[7:5]: reserved */
 788
 789                                         hclk_peri: hclk_peri_div {
 790                                                 compatible = "rockchip,rk3188-div-con";
 791                                                 rockchip,bits = <8 2>;
 792                                                 clocks = <&aclk_peri>;
 793                                                 clock-output-names = "hclk_peri";
 794                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 795                                                 rockchip,div-relations =
 796                                                                 <0x0 1
 797                                                                  0x1 2
 798                                                                  0x2 4>;
 799                                                 #clock-cells = <0>;
 800                                                 #clock-init-cells = <1>;
 801                                         };
 802
 803                                         /* reg[11:10]: reserved */
 804
 805                                         pclk_peri: pclk_peri_div {
 806                                                 compatible = "rockchip,rk3188-div-con";
 807                                                 rockchip,bits = <12 2>;
 808                                                 clocks = <&aclk_peri>;
 809                                                 clock-output-names = "pclk_peri";
 810                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 811                                                 rockchip,div-relations =
 812                                                                 <0x0 1
 813                                                                  0x1 2
 814                                                                  0x2 4
 815                                                                  0x3 8>;
 816                                                 #clock-cells = <0>;
 817                                                 #clock-init-cells = <1>;
 818                                         };
 819
 820                                         /* reg[14]: reserved */
 821
 822                                         aclk_peri: aclk_peri_mux {
 823                                                 compatible = "rockchip,rk3188-mux-con";
 824                                                 rockchip,bits = <15 1>;
 825                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 826                                                 clock-output-names = "aclk_peri";
 827                                                 #clock-cells = <0>;
 828                                                 #clock-init-cells = <1>;
 829                                         };
 830                                 };
 831
 832                                 clk_sel_con11: sel-con@008c {
 833                                         compatible = "rockchip,rk3188-selcon";
 834                                         reg = <0x008c 0x4>;
 835                                         #address-cells = <1>;
 836                                         #size-cells = <1>;
 837
 838                                         clk_sdmmc_div: clk_sdmmc_div {
 839                                                 compatible = "rockchip,rk3188-div-con";
 840                                                 rockchip,bits = <0 6>;
 841                                                 clocks = <&clk_sdmmc>;
 842                                                 clock-output-names = "clk_sdmmc";
 843                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 844                                                 #clock-cells = <0>;
 845                                                 rockchip,clkops-idx =
 846                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 847                                         };
 848
 849                                         clk_sdmmc: clk_sdmmc_mux {
 850                                                 compatible = "rockchip,rk3188-mux-con";
 851                                                 rockchip,bits = <6 2>;
 852                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
 853                                                 clock-output-names = "clk_sdmmc";
 854                                                 #clock-cells = <0>;
 855                                         };
 856
 857                                         hsicphy_12m_div: hsicphy_12m_div {
 858                                                 compatible = "rockchip,rk3188-div-con";
 859                                                 rockchip,bits = <8 6>;
 860                                                 clocks = <&hsicphy_480m>;
 861                                                 clock-output-names = "hsicphy_12m_div";
 862                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 863                                                 #clock-cells = <0>;
 864                                         };
 865
 866                                 };
 867
 868                                 clk_sel_con12: sel-con@0090 {
 869                                         compatible = "rockchip,rk3188-selcon";
 870                                         reg = <0x0090 0x4>;
 871                                         #address-cells = <1>;
 872                                         #size-cells = <1>;
 873
 874                                         clk_sdio0_div: clk_sdio0_div {
 875                                                 compatible = "rockchip,rk3188-div-con";
 876                                                 rockchip,bits = <0 6>;
 877                                                 clocks = <&clk_sdio0>;
 878                                                 clock-output-names = "clk_sdio0";
 879                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 880                                                 #clock-cells = <0>;
 881                                                 rockchip,clkops-idx =
 882                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 883                                         };
 884
 885                                         clk_sdio0: clk_sdio0_mux {
 886                                                 compatible = "rockchip,rk3188-mux-con";
 887                                                 rockchip,bits = <6 2>;
 888                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
 889                                                 clock-output-names = "clk_sdio0";
 890                                                 #clock-cells = <0>;
 891                                         };
 892
 893                                         clk_emmc_div: clk_emmc_div {
 894                                                 compatible = "rockchip,rk3188-div-con";
 895                                                 rockchip,bits = <8 6>;
 896                                                 clocks = <&clk_emmc>;
 897                                                 clock-output-names = "clk_emmc";
 898                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 899                                                 #clock-cells = <0>;
 900                                                 rockchip,clkops-idx =
 901                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 902                                         };
 903
 904                                         clk_emmc: clk_emmc_mux {
 905                                                 compatible = "rockchip,rk3188-mux-con";
 906                                                 rockchip,bits = <14 2>;
 907                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
 908                                                 clock-output-names = "clk_emmc";
 909                                                 #clock-cells = <0>;
 910                                         };
 911                                 };
 912
 913                                 clk_sel_con13: sel-con@0094 {
 914                                         compatible = "rockchip,rk3188-selcon";
 915                                         reg = <0x0094 0x4>;
 916                                         #address-cells = <1>;
 917                                         #size-cells = <1>;
 918
 919                                         clk_uart0_pll_div: clk_uart0_pll_div {
 920                                                 compatible = "rockchip,rk3188-div-con";
 921                                                 rockchip,bits = <0 7>;
 922                                                 clocks = <&clk_uart0_pll>;
 923                                                 clock-output-names = "clk_uart0_pll";
 924                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 925                                                 #clock-cells = <0>;
 926                                                 rockchip,clkops-idx =
 927                                                         <CLKOPS_RATE_MUX_DIV>;
 928                                         };
 929
 930                                         /* reg[7]: reserved */
 931
 932                                         clk_uart0: uart0_mux {
 933                                                 compatible = "rockchip,rk3188-mux-con";
 934                                                 rockchip,bits = <8 2>;
 935                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&dummy>;
 936                                                 clock-output-names = "clk_uart0";
 937                                                 #clock-cells = <0>;
 938                                                 rockchip,clkops-idx =
 939                                                         <CLKOPS_RATE_RK3288_I2S>;
 940                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 941                                         };
 942
 943                                         /* reg[10]: reserved */
 944
 945                                         usbphy_480m: usbphy_480m_mux {
 946                                                 compatible = "rockchip,rk3188-mux-con";
 947                                                 rockchip,bits = <11 2>;
 948                                                 clocks = <&otgphy0_480m>, <&otgphy1_480m>, <&otgphy2_480m>;
 949                                                 clock-output-names = "usbphy_480m";
 950                                                 #clock-cells = <0>;
 951                                                 rockchip,clkops-idx =
 952                                                         <CLKOPS_RATE_RK3288_USB480M>;
 953                                                 #clock-init-cells = <1>;
 954                                         };
 955
 956                                         clk_uart0_pll: clk_uart0_pll_mux {
 957                                                 compatible = "rockchip,rk3188-mux-con";
 958                                                 rockchip,bits = <13 2>;
 959                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
 960                                                 clock-output-names = "clk_uart0_pll";
 961                                                 #clock-cells = <0>;
 962                                         };
 963
 964                                         uart_pll_mux: uart_pll_mux {
 965                                                 compatible = "rockchip,rk3188-mux-con";
 966                                                 rockchip,bits = <15 1>;
 967                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 968                                                 clock-output-names = "uart_pll_mux";
 969                                                 #clock-cells = <0>;
 970                                                 #clock-init-cells = <1>;
 971                                         };
 972                                 };
 973
 974                                 clk_sel_con14: sel-con@0098 {
 975                                         compatible = "rockchip,rk3188-selcon";
 976                                         reg = <0x0098 0x4>;
 977                                         #address-cells = <1>;
 978                                         #size-cells = <1>;
 979
 980                                         clk_uart1_div: clk_uart1_div {
 981                                                 compatible = "rockchip,rk3188-div-con";
 982                                                 rockchip,bits = <0 7>;
 983                                                 clocks = <&uart_pll_mux>;
 984                                                 clock-output-names = "clk_uart1_div";
 985                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 986                                                 #clock-cells = <0>;
 987                                         };
 988
 989                                         /* reg[7]: reserved */
 990
 991                                         clk_uart1: uart1_mux {
 992                                                 compatible = "rockchip,rk3188-mux-con";
 993                                                 rockchip,bits = <8 2>;
 994                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>, <&dummy>;
 995                                                 clock-output-names = "clk_uart1";
 996                                                 #clock-cells = <0>;
 997                                                 rockchip,clkops-idx =
 998                                                         <CLKOPS_RATE_RK3288_I2S>;
 999                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1000                                         };
1001
1002                                         /* reg[15:10]: reserved */
1003                                 };
1004
1005                                 clk_sel_con15: sel-con@009c {
1006                                         compatible = "rockchip,rk3188-selcon";
1007                                         reg = <0x009c 0x4>;
1008                                         #address-cells = <1>;
1009                                         #size-cells = <1>;
1010
1011                                         clk_uart2_div: clk_uart2_div {
1012                                                 compatible = "rockchip,rk3188-div-con";
1013                                                 rockchip,bits = <0 7>;
1014                                                 clocks = <&uart_pll_mux>;
1015                                                 clock-output-names = "clk_uart2_div";
1016                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1017                                                 #clock-cells = <0>;
1018                                         };
1019
1020                                         /* reg[7]: reserved */
1021
1022                                         clk_uart2: uart2_mux {
1023                                                 compatible = "rockchip,rk3188-mux-con";
1024                                                 rockchip,bits = <8 2>;
1025                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>, <&dummy>;
1026                                                 clock-output-names = "clk_uart2";
1027                                                 #clock-cells = <0>;
1028                                                 rockchip,clkops-idx =
1029                                                         <CLKOPS_RATE_RK3288_I2S>;
1030                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1031                                         };
1032
1033                                         /* reg[15:10]: reserved */
1034                                 };
1035
1036                                 clk_sel_con16: sel-con@00a0 {
1037                                         compatible = "rockchip,rk3188-selcon";
1038                                         reg = <0x00a0 0x4>;
1039                                         #address-cells = <1>;
1040                                         #size-cells = <1>;
1041
1042                                         clk_uart3_div: clk_uart3_div {
1043                                                 compatible = "rockchip,rk3188-div-con";
1044                                                 rockchip,bits = <0 7>;
1045                                                 clocks = <&uart_pll_mux>;
1046                                                 clock-output-names = "clk_uart3_div";
1047                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1048                                                 #clock-cells = <0>;
1049                                         };
1050
1051                                         /* reg[7]: reserved */
1052
1053                                         clk_uart3: uart3_mux {
1054                                                 compatible = "rockchip,rk3188-mux-con";
1055                                                 rockchip,bits = <8 2>;
1056                                                 clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>, <&dummy>;
1057                                                 clock-output-names = "clk_uart3";
1058                                                 #clock-cells = <0>;
1059                                                 rockchip,clkops-idx =
1060                                                         <CLKOPS_RATE_RK3288_I2S>;
1061                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1062                                         };
1063
1064                                         /* reg[15:10]: reserved */
1065                                 };
1066
1067                                 clk_sel_con17: sel-con@00a4 {
1068                                         compatible = "rockchip,rk3188-selcon";
1069                                         reg = <0x00a4 0x4>;
1070                                         #address-cells = <1>;
1071                                         #size-cells = <1>;
1072
1073                                         uart0_frac: uart0_frac {
1074                                                 compatible = "rockchip,rk3188-frac-con";
1075                                                 clocks = <&clk_uart0_pll>;
1076                                                 clock-output-names = "uart0_frac";
1077                                                 /* numerator    denominator */
1078                                                 rockchip,bits = <0 32>;
1079                                                 rockchip,clkops-idx =
1080                                                         <CLKOPS_RATE_FRAC>;
1081                                                 #clock-cells = <0>;
1082                                         };
1083                                 };
1084
1085                                 clk_sel_con18: sel-con@00a8 {
1086                                         compatible = "rockchip,rk3188-selcon";
1087                                         reg = <0x00a8 0x4>;
1088                                         #address-cells = <1>;
1089                                         #size-cells = <1>;
1090
1091                                         uart1_frac: uart1_frac {
1092                                                 compatible = "rockchip,rk3188-frac-con";
1093                                                 clocks = <&clk_uart1_div>;
1094                                                 clock-output-names = "uart1_frac";
1095                                                 /* numerator    denominator */
1096                                                 rockchip,bits = <0 32>;
1097                                                 rockchip,clkops-idx =
1098                                                         <CLKOPS_RATE_FRAC>;
1099                                                 #clock-cells = <0>;
1100                                         };
1101                                 };
1102
1103                                 clk_sel_con19: sel-con@00ac {
1104                                         compatible = "rockchip,rk3188-selcon";
1105                                         reg = <0x00ac 0x4>;
1106                                         #address-cells = <1>;
1107                                         #size-cells = <1>;
1108
1109                                         uart2_frac: uart2_frac {
1110                                                 compatible = "rockchip,rk3188-frac-con";
1111                                                 clocks = <&clk_uart2_div>;
1112                                                 clock-output-names = "uart2_frac";
1113                                                 /* numerator    denominator */
1114                                                 rockchip,bits = <0 32>;
1115                                                 rockchip,clkops-idx =
1116                                                         <CLKOPS_RATE_FRAC>;
1117                                                 #clock-cells = <0>;
1118                                         };
1119
1120                                 };
1121
1122                                 clk_sel_con20: sel-con@00b0 {
1123                                         compatible = "rockchip,rk3188-selcon";
1124                                         reg = <0x00b0 0x4>;
1125                                         #address-cells = <1>;
1126                                         #size-cells = <1>;
1127
1128                                         uart3_frac: uart3_frac {
1129                                                 compatible = "rockchip,rk3188-frac-con";
1130                                                 clocks = <&clk_uart3_div>;
1131                                                 clock-output-names = "uart3_frac";
1132                                                 /* numerator    denominator */
1133                                                 rockchip,bits = <0 32>;
1134                                                 rockchip,clkops-idx =
1135                                                         <CLKOPS_RATE_FRAC>;
1136                                                 #clock-cells = <0>;
1137                                         };
1138                                 };
1139
1140                                 clk_sel_con21: sel-con@00b4 {
1141                                         compatible = "rockchip,rk3188-selcon";
1142                                         reg = <0x00b4 0x4>;
1143                                         #address-cells = <1>;
1144                                         #size-cells = <1>;
1145
1146                                         clk_mac_pll: clk_mac_pll_mux {
1147                                                 compatible = "rockchip,rk3188-mux-con";
1148                                                 rockchip,bits = <0 2>;
1149                                                 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>;
1150                                                 clock-output-names = "clk_mac_pll";
1151                                                 #clock-cells = <0>;
1152                                         };
1153
1154                                         /* reg[3:2]: reserved */
1155
1156                                         clk_mac: clk_mac_mux {
1157                                                 compatible = "rockchip,rk3188-mux-con";
1158                                                 rockchip,bits = <4 1>;
1159                                                 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1160                                                 clock-output-names = "clk_mac";
1161                                                 #clock-cells = <0>;
1162                                                 rockchip,clkops-idx =
1163                                                         <CLKOPS_RATE_MAC_REF>;
1164                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1165                                                 #clock-init-cells = <1>;
1166                                         };
1167
1168                                         /* reg[7:5]: reserved */
1169
1170                                         clk_mac_pll_div: clk_mac_pll_div {
1171                                                 compatible = "rockchip,rk3188-div-con";
1172                                                 rockchip,bits = <8 5>;
1173                                                 clocks = <&clk_mac_pll>;
1174                                                 clock-output-names = "clk_mac_pll";
1175                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1176                                                 #clock-cells = <0>;
1177                                                 rockchip,clkops-idx =
1178                                                         <CLKOPS_RATE_MUX_DIV>;
1179                                         };
1180
1181                                         /* reg[15:13]: reserved */
1182                                 };
1183
1184                                 clk_sel_con22: sel-con@00b8 {
1185                                         compatible = "rockchip,rk3188-selcon";
1186                                         reg = <0x00b8 0x4>;
1187                                         #address-cells = <1>;
1188                                         #size-cells = <1>;
1189
1190                                         clk_hsadc_pll: clk_hsadc_pll_mux {
1191                                                 compatible = "rockchip,rk3188-mux-con";
1192                                                 rockchip,bits = <0 1>;
1193                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1194                                                 clock-output-names = "clk_hsadc_pll";
1195                                                 #clock-cells = <0>;
1196                                         };
1197 /*
1198                                         wifi_pll_mux: wifi_pll_mux {
1199                                                 compatible = "rockchip,rk3188-mux-con";
1200                                                 rockchip,bits = <1 1>;
1201                                                 clocks = <&>, <&>;
1202                                                 clock-output-names = "wifi_pll_mux";
1203                                                 #clock-cells = <0>;
1204                                         };
1205 */
1206
1207                                         /* reg[3:2]: reserved */
1208
1209                                         clk_hsadc_out: clk_hsadc_out {
1210                                                 compatible = "rockchip,rk3188-mux-con";
1211                                                 rockchip,bits = <4 1>;
1212                                                 clocks = <&clk_hsadc_pll>, <&clk_hsadc_ext>;
1213                                                 clock-output-names = "clk_hsadc_out";
1214                                                 #clock-cells = <0>;
1215                                                 rockchip,clkops-idx =
1216                                                         <CLKOPS_RATE_HSADC>;
1217                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1218                                         };
1219
1220                                         /* reg[6:5]: reserved */
1221
1222                                         clk_hsadc: clk_hsadc {
1223                                                 compatible = "rockchip,rk3188-mux-con";
1224                                                 rockchip,bits = <7 1>;
1225                                                 clocks = <&clk_hsadc_out>, <&clk_hsadc_inv>;
1226                                                 clock-output-names = "clk_hsadc";
1227                                                 #clock-cells = <0>;
1228                                         };
1229
1230                                         clk_hsadc_pll_div: clk_hsadc_pll_div {
1231                                                 compatible = "rockchip,rk3188-div-con";
1232                                                 rockchip,bits = <8 8>;
1233                                                 clocks = <&clk_hsadc_pll>;
1234                                                 clock-output-names = "clk_hsadc_pll";
1235                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1236                                                 #clock-cells = <0>;
1237                                                 rockchip,clkops-idx =
1238                                                         <CLKOPS_RATE_MUX_DIV>;
1239                                         };
1240                                 };
1241 /*
1242                                 clk_sel_con23: sel-con@00bc {
1243                                         compatible = "rockchip,rk3188-selcon";
1244                                         reg = <0x00bc 0x4>;
1245                                         #address-cells = <1>;
1246                                         #size-cells = <1>;
1247
1248                                         wifi_frac: wifi_frac {
1249                                                 compatible = "rockchip,rk3188-frac-con";
1250                                                 clocks = <&>;
1251                                                 clock-output-names = "wifi_frac";
1252                                                 / numerator     denominator /
1253                                                 rockchip,bits = <0 32>;
1254                                                 rockchip,clkops-idx =
1255                                                         <>;
1256                                                 #clock-cells = <0>;
1257                                         };
1258                                 };
1259 */
1260
1261                                 clk_sel_con24: sel-con@00c0 {
1262                                         compatible = "rockchip,rk3188-selcon";
1263                                         reg = <0x00c0 0x4>;
1264                                         #address-cells = <1>;
1265                                         #size-cells = <1>;
1266
1267                                         /* reg[7:0]: reserved */
1268
1269                                         clk_saradc: clk_saradc_div {
1270                                                 compatible = "rockchip,rk3188-div-con";
1271                                                 rockchip,bits = <8 8>;
1272                                                 clocks = <&xin24m>;
1273                                                 clock-output-names = "clk_saradc";
1274                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1275                                                 #clock-cells = <0>;
1276                                         };
1277                                 };
1278
1279                                 clk_sel_con25: sel-con@00c4 {
1280                                         compatible = "rockchip,rk3188-selcon";
1281                                         reg = <0x00c4 0x4>;
1282                                         #address-cells = <1>;
1283                                         #size-cells = <1>;
1284
1285                                         clk_spi0_div: clk_spi0_div {
1286                                                 compatible = "rockchip,rk3188-div-con";
1287                                                 rockchip,bits = <0 7>;
1288                                                 clocks = <&clk_spi0>;
1289                                                 clock-output-names = "clk_spi0";
1290                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1291                                                 #clock-cells = <0>;
1292                                                 rockchip,clkops-idx =
1293                                                         <CLKOPS_RATE_MUX_DIV>;
1294                                         };
1295
1296                                         clk_spi0: clk_spi0_mux {
1297                                                 compatible = "rockchip,rk3188-mux-con";
1298                                                 rockchip,bits = <7 1>;
1299                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1300                                                 clock-output-names = "clk_spi0";
1301                                                 #clock-cells = <0>;
1302                                         };
1303
1304                                         clk_spi1_div: clk_spi1_div {
1305                                                 compatible = "rockchip,rk3188-div-con";
1306                                                 rockchip,bits = <8 7>;
1307                                                 clocks = <&clk_spi1>;
1308                                                 clock-output-names = "clk_spi1";
1309                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1310                                                 #clock-cells = <0>;
1311                                                 rockchip,clkops-idx =
1312                                                         <CLKOPS_RATE_MUX_DIV>;
1313                                         };
1314
1315                                         clk_spi1: clk_spi1_mux {
1316                                                 compatible = "rockchip,rk3188-mux-con";
1317                                                 rockchip,bits = <15 1>;
1318                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1319                                                 clock-output-names = "clk_spi1";
1320                                                 #clock-cells = <0>;
1321                                         };
1322                                 };
1323
1324                                 clk_sel_con26: sel-con@00c8 {
1325                                         compatible = "rockchip,rk3188-selcon";
1326                                         reg = <0x00c8 0x4>;
1327                                         #address-cells = <1>;
1328                                         #size-cells = <1>;
1329
1330                                         ddr_div: ddr_div {
1331                                                 compatible = "rockchip,rk3188-div-con";
1332                                                 rockchip,bits = <0 2>;
1333                                                 clocks = <&clk_ddr>;
1334                                                 clock-output-names = "clk_ddr";
1335                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1336                                                 rockchip,div-relations =
1337                                                                 <0x0 1
1338                                                                  0x1 2
1339                                                                  0x3 4>;
1340                                                 #clock-cells = <0>;
1341                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1342                                                                         CLK_SET_RATE_NO_REPARENT)>;
1343                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
1344                                         };
1345
1346                                         clk_ddr: ddr_clk_pll_mux {
1347                                                 compatible = "rockchip,rk3188-mux-con";
1348                                                 rockchip,bits = <2 1>;
1349                                                 clocks = <&clk_dpll>, <&clk_gpll>;
1350                                                 clock-output-names = "clk_ddr";
1351                                                 #clock-cells = <0>;
1352                                         };
1353
1354                                         /* reg[5:3]: reserved */
1355
1356                                         clk_crypto: crypto_div {
1357                                                 compatible = "rockchip,rk3188-div-con";
1358                                                 rockchip,bits = <6 2>;
1359                                                 clocks = <&aclk_bus>;
1360                                                 clock-output-names = "clk_crypto";
1361                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1362                                                 #clock-cells = <0>;
1363                                                 #clock-init-cells = <1>;
1364                                         };
1365
1366                                         clk_cif_pll: clk_cif_pll_mux {
1367                                                 compatible = "rockchip,rk3188-mux-con";
1368                                                 rockchip,bits = <8 1>;
1369                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1370                                                 clock-output-names = "clk_cif_pll";
1371                                                 #clock-cells = <0>;
1372                                         };
1373
1374                                         clk_cif_out_div: clk_cif_out_div {
1375                                                 compatible = "rockchip,rk3188-div-con";
1376                                                 rockchip,bits = <9 5>;
1377                                                 clocks = <&clk_cif_out>;
1378                                                 clock-output-names = "clk_cif_out";
1379                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1380                                                 #clock-cells = <0>;
1381                                                 rockchip,clkops-idx =
1382                                                         <CLKOPS_RATE_MUX_DIV>;
1383                                         };
1384
1385                                         /* reg[14]: reserved */
1386
1387                                         clk_cif_out: clk_cif_out_mux {
1388                                                 compatible = "rockchip,rk3188-mux-con";
1389                                                 rockchip,bits = <15 1>;
1390                                                 clocks = <&clk_cif_pll>, <&xin24m>;
1391                                                 clock-output-names = "clk_cif_out";
1392                                                 #clock-cells = <0>;
1393                                         };
1394                                 };
1395
1396                                 clk_sel_con27: sel-con@00cc {
1397                                         compatible = "rockchip,rk3188-selcon";
1398                                         reg = <0x00cc 0x4>;
1399                                         #address-cells = <1>;
1400                                         #size-cells = <1>;
1401
1402                                         dclk_lcdc0: dclk_lcdc0_mux {
1403                                                 compatible = "rockchip,rk3188-mux-con";
1404                                                 rockchip,bits = <0 2>;
1405                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1406                                                 clock-output-names = "dclk_lcdc0";
1407                                                 #clock-cells = <0>;
1408                                         };
1409
1410                                         /* reg[7:2]: reserved */
1411
1412                                         dclk_lcdc0_div: dclk_lcdc0_div {
1413                                                 compatible = "rockchip,rk3188-div-con";
1414                                                 rockchip,bits = <8 8>;
1415                                                 clocks = <&dclk_lcdc0>;
1416                                                 clock-output-names = "dclk_lcdc0";
1417                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1418                                                 #clock-cells = <0>;
1419                                                 rockchip,clkops-idx =
1420                                                         <CLKOPS_RATE_MUX_EVENDIV>;
1421                                         };
1422                                 };
1423
1424                                 clk_sel_con28: sel-con@00d0 {
1425                                         compatible = "rockchip,rk3188-selcon";
1426                                         reg = <0x00d0 0x4>;
1427                                         #address-cells = <1>;
1428                                         #size-cells = <1>;
1429
1430                                         clk_edp_div: clk_edp_div {
1431                                                 compatible = "rockchip,rk3188-div-con";
1432                                                 rockchip,bits = <0 6>;
1433                                                 clocks = <&clk_edp>;
1434                                                 clock-output-names = "clk_edp";
1435                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1436                                                 #clock-cells = <0>;
1437                                                 rockchip,clkops-idx =
1438                                                         <CLKOPS_RATE_MUX_DIV>;
1439                                         };
1440
1441                                         clk_edp: clk_edp_mux {
1442                                                 compatible = "rockchip,rk3188-mux-con";
1443                                                 rockchip,bits = <6 2>;
1444                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1445                                                 clock-output-names = "clk_edp";
1446                                                 #clock-cells = <0>;
1447                                                 #clock-init-cells = <1>;
1448                                         };
1449
1450                                         hclk_vio: hclk_vio_div {
1451                                                 compatible = "rockchip,rk3188-div-con";
1452                                                 rockchip,bits = <8 5>;
1453                                                 clocks = <&aclk_vio0>;
1454                                                 clock-output-names = "hclk_vio";
1455                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1456                                                 #clock-cells = <0>;
1457                                                 #clock-init-cells = <1>;
1458                                         };
1459
1460                                         /* reg[14:13]: reserved */
1461
1462                                         clk_edp_24m: edp_24m_mux {
1463                                                 compatible = "rockchip,rk3188-mux-con";
1464                                                 rockchip,bits = <15 1>;
1465                                                 clocks = <&edp_24m_clkin>, <&xin24m>;
1466                                                 clock-output-names = "clk_edp_24m";
1467                                                 #clock-cells = <0>;
1468                                         };
1469                                 };
1470
1471                                 clk_sel_con29: sel-con@00d4 {
1472                                         compatible = "rockchip,rk3188-selcon";
1473                                         reg = <0x00d4 0x4>;
1474                                         #address-cells = <1>;
1475                                         #size-cells = <1>;
1476
1477                                         hsicphy_480m: hsicphy_480m_mux {
1478                                                 compatible = "rockchip,rk3188-mux-con";
1479                                                 rockchip,bits = <0 2>;
1480                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1481                                                 clock-output-names = "hsicphy_480m";
1482                                                 #clock-cells = <0>;
1483                                         };
1484
1485                                         hsicphy_12m: hsicphy_12m_mux {
1486                                                 compatible = "rockchip,rk3188-mux-con";
1487                                                 rockchip,bits = <2 1>;
1488                                                 clocks = <&clk_gates13 9>, <&hsicphy_12m_div>;
1489                                                 clock-output-names = "hsicphy_12m";
1490                                                 #clock-cells = <0>;
1491                                         };
1492
1493                                         clkin_isp: clkin_isp {
1494                                                 compatible = "rockchip,rk3188-mux-con";
1495                                                 rockchip,bits = <3 1>;
1496                                                 clocks = <&clk_gates16 3>, <&pclkin_isp_inv>;
1497                                                 clock-output-names = "clkin_isp";
1498                                                 #clock-cells = <0>;
1499                                         };
1500
1501                                         clkin_cif: clkin_cif {
1502                                                 compatible = "rockchip,rk3188-mux-con";
1503                                                 rockchip,bits = <4 1>;
1504                                                 clocks = <&clk_gates16 0>, <&pclkin_cif_inv>;
1505                                                 clock-output-names = "clkin_cif";
1506                                                 #clock-cells = <0>;
1507                                         };
1508
1509                                         /* reg[5]: reserved */
1510
1511                                         dclk_lcdc1: dclk_lcdc1_mux {
1512                                                 compatible = "rockchip,rk3188-mux-con";
1513                                                 rockchip,bits = <6 2>;
1514                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1515                                                 clock-output-names = "dclk_lcdc1";
1516                                                 #clock-cells = <0>;
1517                                         };
1518
1519                                         dclk_lcdc1_div: dclk_lcdc1_div {
1520                                                 compatible = "rockchip,rk3188-div-con";
1521                                                 rockchip,bits = <8 8>;
1522                                                 clocks = <&dclk_lcdc1>;
1523                                                 clock-output-names = "dclk_lcdc1";
1524                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1525                                                 #clock-cells = <0>;
1526                                                 rockchip,clkops-idx =
1527                                                         <CLKOPS_RATE_MUX_DIV>;
1528                                         };
1529                                 };
1530
1531                                 clk_sel_con30: sel-con@00d8 {
1532                                         compatible = "rockchip,rk3188-selcon";
1533                                         reg = <0x00d8 0x4>;
1534                                         #address-cells = <1>;
1535                                         #size-cells = <1>;
1536
1537                                         aclk_rga_div: aclk_rga_div {
1538                                                 compatible = "rockchip,rk3188-div-con";
1539                                                 rockchip,bits = <0 5>;
1540                                                 clocks = <&aclk_rga>;
1541                                                 clock-output-names = "aclk_rga";
1542                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1543                                                 #clock-cells = <0>;
1544                                                 rockchip,clkops-idx =
1545                                                         <CLKOPS_RATE_MUX_DIV>;
1546                                         };
1547
1548                                         /* reg[5]: reserved */
1549
1550                                         aclk_rga: aclk_rga_mux {
1551                                                 compatible = "rockchip,rk3188-mux-con";
1552                                                 rockchip,bits = <6 2>;
1553                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1554                                                 clock-output-names = "aclk_rga";
1555                                                 #clock-cells = <0>;
1556                                                 #clock-init-cells = <1>;
1557                                         };
1558
1559                                         clk_rga_div: clk_rga_div {
1560                                                 compatible = "rockchip,rk3188-div-con";
1561                                                 rockchip,bits = <8 5>;
1562                                                 clocks = <&clk_rga>;
1563                                                 clock-output-names = "clk_rga";
1564                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1565                                                 #clock-cells = <0>;
1566                                                 rockchip,clkops-idx =
1567                                                         <CLKOPS_RATE_MUX_DIV>;
1568                                         };
1569
1570                                         /* reg[13]: reserved */
1571
1572                                         clk_rga: clk_rga_mux {
1573                                                 compatible = "rockchip,rk3188-mux-con";
1574                                                 rockchip,bits = <14 2>;
1575                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1576                                                 clock-output-names = "clk_rga";
1577                                                 #clock-cells = <0>;
1578                                                 #clock-init-cells = <1>;
1579                                         };
1580                                 };
1581
1582                                 clk_sel_con31: sel-con@00dc {
1583                                         compatible = "rockchip,rk3188-selcon";
1584                                         reg = <0x00dc 0x4>;
1585                                         #address-cells = <1>;
1586                                         #size-cells = <1>;
1587
1588                                         aclk_vio0_div: aclk_vio0_div {
1589                                                 compatible = "rockchip,rk3188-div-con";
1590                                                 rockchip,bits = <0 5>;
1591                                                 clocks = <&aclk_vio0>;
1592                                                 clock-output-names = "aclk_vio0";
1593                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1594                                                 #clock-cells = <0>;
1595                                                 rockchip,clkops-idx =
1596                                                         <CLKOPS_RATE_MUX_DIV>;
1597                                         };
1598
1599                                         /* reg[5]: reserved */
1600
1601                                         aclk_vio0: aclk_vio0_mux {
1602                                                 compatible = "rockchip,rk3188-mux-con";
1603                                                 rockchip,bits = <6 2>;
1604                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1605                                                 clock-output-names = "aclk_vio0";
1606                                                 #clock-cells = <0>;
1607                                                 #clock-init-cells = <1>;
1608                                         };
1609
1610                                         aclk_vio1_div: aclk_vio1_div {
1611                                                 compatible = "rockchip,rk3188-div-con";
1612                                                 rockchip,bits = <8 5>;
1613                                                 clocks = <&aclk_vio1>;
1614                                                 clock-output-names = "aclk_vio1";
1615                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1616                                                 #clock-cells = <0>;
1617                                                 rockchip,clkops-idx =
1618                                                         <CLKOPS_RATE_MUX_DIV>;
1619                                         };
1620
1621                                         /* reg[13]: reserved */
1622
1623                                         aclk_vio1: aclk_vio1_mux {
1624                                                 compatible = "rockchip,rk3188-mux-con";
1625                                                 rockchip,bits = <14 2>;
1626                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1627                                                 clock-output-names = "aclk_vio1";
1628                                                 #clock-cells = <0>;
1629                                                 #clock-init-cells = <1>;
1630                                         };
1631                                 };
1632
1633                                 clk_sel_con32: sel-con@00e0 {
1634                                         compatible = "rockchip,rk3188-selcon";
1635                                         reg = <0x00e0 0x4>;
1636                                         #address-cells = <1>;
1637                                         #size-cells = <1>;
1638
1639                                         clk_vepu_div: clk_vepu_div {
1640                                                 compatible = "rockchip,rk3188-div-con";
1641                                                 rockchip,bits = <0 5>;
1642                                                 clocks = <&clk_vepu>;
1643                                                 clock-output-names = "clk_vepu";
1644                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1645                                                 #clock-cells = <0>;
1646                                                 rockchip,clkops-idx =
1647                                                         <CLKOPS_RATE_MUX_DIV>;
1648                                         };
1649
1650                                         /* reg[5]: reserved */
1651
1652                                         clk_vepu: clk_vepu_mux {
1653                                                 compatible = "rockchip,rk3188-mux-con";
1654                                                 rockchip,bits = <6 2>;
1655                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1656                                                 clock-output-names = "clk_vepu";
1657                                                 #clock-cells = <0>;
1658                                                 #clock-init-cells = <1>;
1659                                         };
1660
1661                                         clk_vdpu_div: clk_vdpu_div {
1662                                                 compatible = "rockchip,rk3188-div-con";
1663                                                 rockchip,bits = <8 5>;
1664                                                 clocks = <&clk_vdpu>;
1665                                                 clock-output-names = "clk_vdpu";
1666                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1667                                                 #clock-cells = <0>;
1668                                                 rockchip,clkops-idx =
1669                                                         <CLKOPS_RATE_MUX_DIV>;
1670                                         };
1671
1672                                         /* reg[13]: reserved */
1673
1674                                         clk_vdpu: clk_vdpu_mux {
1675                                                 compatible = "rockchip,rk3188-mux-con";
1676                                                 rockchip,bits = <14 2>;
1677                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1678                                                 clock-output-names = "clk_vdpu";
1679                                                 #clock-cells = <0>;
1680                                                 #clock-init-cells = <1>;
1681                                         };
1682                                 };
1683
1684                                 clk_sel_con33: sel-con@00e4 {
1685                                         compatible = "rockchip,rk3188-selcon";
1686                                         reg = <0x00e4 0x4>;
1687                                         #address-cells = <1>;
1688                                         #size-cells = <1>;
1689
1690                                         pclk_pd_pmu: pclk_pd_pmu_div {
1691                                                 compatible = "rockchip,rk3188-div-con";
1692                                                 rockchip,bits = <0 5>;
1693                                                 clocks = <&clk_gpll>;
1694                                                 clock-output-names = "pclk_pd_pmu";
1695                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1696                                                 #clock-cells = <0>;
1697                                                 #clock-init-cells = <1>;
1698                                         };
1699
1700                                         /* reg[7:5]: reserved */
1701
1702                                         pclk_pd_alive: pclk_pd_alive {
1703                                                 compatible = "rockchip,rk3188-div-con";
1704                                                 rockchip,bits = <8 5>;
1705                                                 clocks = <&clk_gpll>;
1706                                                 clock-output-names = "pclk_pd_alive";
1707                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1708                                                 #clock-cells = <0>;
1709                                                 #clock-init-cells = <1>;
1710                                         };
1711
1712                                         /* reg[15:13]: reserved */
1713                                 };
1714
1715                                 clk_sel_con34: sel-con@00e8 {
1716                                         compatible = "rockchip,rk3188-selcon";
1717                                         reg = <0x00e8 0x4>;
1718                                         #address-cells = <1>;
1719                                         #size-cells = <1>;
1720
1721                                         clk_gpu_div: clk_gpu_div {
1722                                                 compatible = "rockchip,rk3188-div-con";
1723                                                 rockchip,bits = <0 5>;
1724                                                 clocks = <&clk_gpu>;
1725                                                 clock-output-names = "clk_gpu";
1726                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1727                                                 #clock-cells = <0>;
1728                                                 rockchip,clkops-idx =
1729                                                         <CLKOPS_RATE_MUX_DIV>;
1730                                         };
1731
1732                                         /* reg[5]: reserved */
1733
1734                                         clk_gpu: clk_gpu_mux {
1735                                                 compatible = "rockchip,rk3188-mux-con";
1736                                                 rockchip,bits = <6 2>;
1737                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
1738                                                 clock-output-names = "clk_gpu";
1739                                                 #clock-cells = <0>;
1740                                                 #clock-init-cells = <1>;
1741                                         };
1742
1743                                         clk_sdio1_div: clk_sdio1_div {
1744                                                 compatible = "rockchip,rk3188-div-con";
1745                                                 rockchip,bits = <8 6>;
1746                                                 clocks = <&clk_sdio1>;
1747                                                 clock-output-names = "clk_sdio1";
1748                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1749                                                 #clock-cells = <0>;
1750                                                 rockchip,clkops-idx =
1751                                                         <CLKOPS_RATE_MUX_EVENDIV>;
1752                                         };
1753
1754                                         clk_sdio1: clk_sdio1_mux {
1755                                                 compatible = "rockchip,rk3188-mux-con";
1756                                                 rockchip,bits = <14 2>;
1757                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
1758                                                 clock-output-names = "clk_sdio1";
1759                                                 #clock-cells = <0>;
1760                                         };
1761                                 };
1762
1763                                 clk_sel_con35: sel-con@00ec {
1764                                         compatible = "rockchip,rk3188-selcon";
1765                                         reg = <0x00ec 0x4>;
1766                                         #address-cells = <1>;
1767                                         #size-cells = <1>;
1768
1769                                         clk_tsp_div: clk_tsp_div {
1770                                                 compatible = "rockchip,rk3188-div-con";
1771                                                 rockchip,bits = <0 5>;
1772                                                 clocks = <&clk_tsp>;
1773                                                 clock-output-names = "clk_tsp";
1774                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1775                                                 #clock-cells = <0>;
1776                                                 rockchip,clkops-idx =
1777                                                         <CLKOPS_RATE_MUX_DIV>;
1778                                         };
1779
1780                                         /* reg[5]: reserved */
1781
1782                                         clk_tsp: clk_tsp_mux {
1783                                                 compatible = "rockchip,rk3188-mux-con";
1784                                                 rockchip,bits = <6 2>;
1785                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1786                                                 clock-output-names = "clk_tsp";
1787                                                 #clock-cells = <0>;
1788                                                 #clock-init-cells = <1>;
1789                                         };
1790
1791                                         clk_tspout_div: clk_tspout_div {
1792                                                 compatible = "rockchip,rk3188-div-con";
1793                                                 rockchip,bits = <8 5>;
1794                                                 clocks = <&clk_tspout>;
1795                                                 clock-output-names = "clk_tspout";
1796                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1797                                                 #clock-cells = <0>;
1798                                                 rockchip,clkops-idx =
1799                                                         <CLKOPS_RATE_MUX_DIV>;
1800                                         };
1801
1802                                         /* reg[13]: reserved */
1803
1804                                         clk_tspout: clk_tspout_mux {
1805                                                 compatible = "rockchip,rk3188-mux-con";
1806                                                 rockchip,bits = <14 2>;
1807                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
1808                                                 clock-output-names = "clk_tspout";
1809                                                 #clock-cells = <0>;
1810                                                 #clock-init-cells = <1>;
1811                                         };
1812                                 };
1813
1814                                 clk_sel_con36: sel-con@00f0 {
1815                                         compatible = "rockchip,rk3188-selcon";
1816                                         reg = <0x00f0 0x4>;
1817                                         #address-cells = <1>;
1818                                         #size-cells = <1>;
1819
1820                                         clk_core0: clk_core0_div {
1821                                                 compatible = "rockchip,rk3188-div-con";
1822                                                 rockchip,bits = <0 3>;
1823                                                 clocks = <&clk_core>;
1824                                                 clock-output-names = "clk_core0";
1825                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1826                                                 #clock-cells = <0>;
1827                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1828                                         };
1829
1830                                         /* reg[3]: reserved */
1831
1832                                         clk_core1: clk_core1_div {
1833                                                 compatible = "rockchip,rk3188-div-con";
1834                                                 rockchip,bits = <4 3>;
1835                                                 clocks = <&clk_core>;
1836                                                 clock-output-names = "clk_core1";
1837                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1838                                                 #clock-cells = <0>;
1839                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1840                                         };
1841
1842                                         /* reg[7]: reserved */
1843
1844                                         clk_core2: clk_core2_div {
1845                                                 compatible = "rockchip,rk3188-div-con";
1846                                                 rockchip,bits = <8 3>;
1847                                                 clocks = <&clk_core>;
1848                                                 clock-output-names = "clk_core2";
1849                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1850                                                 #clock-cells = <0>;
1851                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1852                                         };
1853
1854                                         /* reg[11]: reserved */
1855
1856                                         clk_core3: clk_core3_div {
1857                                                 compatible = "rockchip,rk3188-div-con";
1858                                                 rockchip,bits = <12 3>;
1859                                                 clocks = <&clk_core>;
1860                                                 clock-output-names = "clk_core3";
1861                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1862                                                 #clock-cells = <0>;
1863                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1864                                         };
1865
1866                                         /* reg[15]: reserved */
1867                                 };
1868
1869                                 clk_sel_con37: sel-con@00f4 {
1870                                         compatible = "rockchip,rk3188-selcon";
1871                                         reg = <0x00f4 0x4>;
1872                                         #address-cells = <1>;
1873                                         #size-cells = <1>;
1874
1875                                         clk_l2ram: clk_l2ram_div {
1876                                                 compatible = "rockchip,rk3188-div-con";
1877                                                 rockchip,bits = <0 3>;
1878                                                 clocks = <&clk_core>;
1879                                                 clock-output-names = "clk_l2ram";
1880                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1881                                                 #clock-cells = <0>;
1882                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1883                                         };
1884
1885                                         /* reg[3]: reserved */
1886
1887                                         atclk_core: atclk_core_div {
1888                                                 compatible = "rockchip,rk3188-div-con";
1889                                                 rockchip,bits = <4 5>;
1890                                                 clocks = <&clk_core>;
1891                                                 clock-output-names = "atclk_core";
1892                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1893                                                 #clock-cells = <0>;
1894                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1895                                         };
1896
1897                                         pclk_dbg_src: pclk_core_dbg_div {
1898                                                 compatible = "rockchip,rk3188-div-con";
1899                                                 rockchip,bits = <9 5>;
1900                                                 clocks = <&clk_core>;
1901                                                 clock-output-names = "pclk_dbg_src";
1902                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1903                                                 #clock-cells = <0>;
1904                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1905                                         };
1906
1907                                         /* reg[15:14]: reserved */
1908                                 };
1909
1910                                 clk_sel_con38: sel-con@00f8 {
1911                                         compatible = "rockchip,rk3188-selcon";
1912                                         reg = <0x00f8 0x4>;
1913                                         #address-cells = <1>;
1914                                         #size-cells = <1>;
1915
1916                                         clk_nandc0_div: clk_nandc0_div {
1917                                                 compatible = "rockchip,rk3188-div-con";
1918                                                 rockchip,bits = <0 5>;
1919                                                 clocks = <&clk_nandc0>;
1920                                                 clock-output-names = "clk_nandc0";
1921                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1922                                                 #clock-cells = <0>;
1923                                                 rockchip,clkops-idx =
1924                                                         <CLKOPS_RATE_MUX_DIV>;
1925                                         };
1926
1927                                         /* reg[6:5]: reserved */
1928
1929                                         clk_nandc0: clk_nandc0_mux {
1930                                                 compatible = "rockchip,rk3188-mux-con";
1931                                                 rockchip,bits = <7 1>;
1932                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1933                                                 clock-output-names = "clk_nandc0";
1934                                                 #clock-cells = <0>;
1935                                         };
1936
1937                                         clk_nandc1_div: clk_nandc1_div {
1938                                                 compatible = "rockchip,rk3188-div-con";
1939                                                 rockchip,bits = <8 5>;
1940                                                 clocks = <&clk_nandc1>;
1941                                                 clock-output-names = "clk_nandc1";
1942                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1943                                                 #clock-cells = <0>;
1944                                                 rockchip,clkops-idx =
1945                                                         <CLKOPS_RATE_MUX_DIV>;
1946                                         };
1947
1948                                         /* reg[14:13]: reserved */
1949
1950                                         clk_nandc1: clk_nandc1_mux {
1951                                                 compatible = "rockchip,rk3188-mux-con";
1952                                                 rockchip,bits = <15 1>;
1953                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1954                                                 clock-output-names = "clk_nandc1";
1955                                                 #clock-cells = <0>;
1956                                         };
1957                                 };
1958
1959                                 clk_sel_con39: sel-con@00fc {
1960                                         compatible = "rockchip,rk3188-selcon";
1961                                         reg = <0x00fc 0x4>;
1962                                         #address-cells = <1>;
1963                                         #size-cells = <1>;
1964
1965                                         clk_spi2_div: clk_spi2_div {
1966                                                 compatible = "rockchip,rk3188-div-con";
1967                                                 rockchip,bits = <0 7>;
1968                                                 clocks = <&clk_spi2>;
1969                                                 clock-output-names = "clk_spi2";
1970                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1971                                                 #clock-cells = <0>;
1972                                                 rockchip,clkops-idx =
1973                                                         <CLKOPS_RATE_MUX_DIV>;
1974                                         };
1975
1976                                         clk_spi2: clk_spi2_mux {
1977                                                 compatible = "rockchip,rk3188-mux-con";
1978                                                 rockchip,bits = <7 1>;
1979                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1980                                                 clock-output-names = "clk_spi2";
1981                                                 #clock-cells = <0>;
1982                                         };
1983
1984                                         aclk_hevc_div: aclk_hevc_div {
1985                                                 compatible = "rockchip,rk3188-div-con";
1986                                                 rockchip,bits = <8 5>;
1987                                                 clocks = <&aclk_hevc>;
1988                                                 clock-output-names = "aclk_hevc";
1989                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1990                                                 #clock-cells = <0>;
1991                                                 rockchip,clkops-idx =
1992                                                         <CLKOPS_RATE_MUX_DIV>;
1993                                         };
1994
1995                                         /* reg[13]: reserved */
1996
1997                                         aclk_hevc: aclk_hevc_mux {
1998                                                 compatible = "rockchip,rk3188-mux-con";
1999                                                 rockchip,bits = <14 2>;
2000                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
2001                                                 clock-output-names = "aclk_hevc";
2002                                                 #clock-cells = <0>;
2003                                                 #clock-init-cells = <1>;
2004                                         };
2005                                 };
2006
2007                                 clk_sel_con40: sel-con@0100 {
2008                                         compatible = "rockchip,rk3188-selcon";
2009                                         reg = <0x0100 0x4>;
2010                                         #address-cells = <1>;
2011                                         #size-cells = <1>;
2012
2013                                         spdif_8ch_div: spdif_8ch_div {
2014                                                 compatible = "rockchip,rk3188-div-con";
2015                                                 rockchip,bits = <0 7>;
2016                                                 clocks = <&clk_spdif_pll>;
2017                                                 clock-output-names = "spdif_8ch_div";
2018                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2019                                                 #clock-cells = <0>;
2020                                         };
2021
2022                                         /* reg[7]: reserved */
2023
2024                                         clk_spdif_8ch: spdif_8ch_clk_mux {
2025                                                 compatible = "rockchip,rk3188-mux-con";
2026                                                 rockchip,bits = <8 2>;
2027                                                 clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>;
2028                                                 clock-output-names = "clk_spdif_8ch";
2029                                                 #clock-cells = <0>;
2030                                                 rockchip,clkops-idx =
2031                                                         <CLKOPS_RATE_RK3288_I2S>;
2032                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
2033                                         };
2034
2035                                         /* reg[11:10]: reserved */
2036
2037                                         hclk_hevc: hclk_hevc_div {
2038                                                 compatible = "rockchip,rk3188-div-con";
2039                                                 rockchip,bits = <12 2>;
2040                                                 clocks = <&aclk_hevc>;
2041                                                 clock-output-names = "hclk_hevc";
2042                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2043                                                 #clock-cells = <0>;
2044                                                 #clock-init-cells = <1>;
2045                                         };
2046
2047                                         /* reg[15:14]: reserved */
2048                                 };
2049
2050                                 clk_sel_con41: sel-con@0104 {
2051                                         compatible = "rockchip,rk3188-selcon";
2052                                         reg = <0x0104 0x4>;
2053                                         #address-cells = <1>;
2054                                         #size-cells = <1>;
2055
2056                                         spdif_8ch_frac: spdif_8ch_frac {
2057                                                 compatible = "rockchip,rk3188-frac-con";
2058                                                 clocks = <&spdif_8ch_div>;
2059                                                 clock-output-names = "spdif_8ch_frac";
2060                                                 /* numerator    denominator */
2061                                                 rockchip,bits = <0 32>;
2062                                                 rockchip,clkops-idx =
2063                                                         <CLKOPS_RATE_FRAC>;
2064                                                 #clock-cells = <0>;
2065                                         };
2066                                 };
2067
2068                                 clk_sel_con42: sel-con@0108 {
2069                                         compatible = "rockchip,rk3188-selcon";
2070                                         reg = <0x0108 0x4>;
2071                                         #address-cells = <1>;
2072                                         #size-cells = <1>;
2073
2074                                         clk_hevc_cabac_div: clk_hevc_cabac_div {
2075                                                 compatible = "rockchip,rk3188-div-con";
2076                                                 rockchip,bits = <0 5>;
2077                                                 clocks = <&clk_hevc_cabac>;
2078                                                 clock-output-names = "clk_hevc_cabac";
2079                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2080                                                 #clock-cells = <0>;
2081                                                 rockchip,clkops-idx =
2082                                                         <CLKOPS_RATE_MUX_DIV>;
2083                                         };
2084
2085                                         /* reg[5]: reserved */
2086
2087                                         clk_hevc_cabac: clk_hevc_cabac_mux {
2088                                                 compatible = "rockchip,rk3188-mux-con";
2089                                                 rockchip,bits = <6 2>;
2090                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
2091                                                 clock-output-names = "clk_hevc_cabac";
2092                                                 #clock-cells = <0>;
2093                                                 #clock-init-cells = <1>;
2094                                         };
2095
2096                                         clk_hevc_core_div: clk_hevc_core_div {
2097                                                 compatible = "rockchip,rk3188-div-con";
2098                                                 rockchip,bits = <8 5>;
2099                                                 clocks = <&clk_hevc_core>;
2100                                                 clock-output-names = "clk_hevc_core";
2101                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2102                                                 #clock-cells = <0>;
2103                                                 rockchip,clkops-idx =
2104                                                         <CLKOPS_RATE_MUX_DIV>;
2105                                         };
2106
2107                                         /* reg[13]: reserved */
2108
2109                                         clk_hevc_core: clk_hevc_core_mux {
2110                                                 compatible = "rockchip,rk3188-mux-con";
2111                                                 rockchip,bits = <14 2>;
2112                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
2113                                                 clock-output-names = "clk_hevc_core";
2114                                                 #clock-cells = <0>;
2115                                                 #clock-init-cells = <1>;
2116                                         };
2117                                 };
2118
2119                         };
2120
2121
2122                         /* Gate control regs */
2123                         clk_gate_cons {
2124                                 compatible = "rockchip,rk-gate-cons";
2125                                 #address-cells = <1>;
2126                                 #size-cells = <1>;
2127                                 ranges ;
2128
2129                                 clk_gates0: gate-clk@0160 {
2130                                         compatible = "rockchip,rk3188-gate-clk";
2131                                         reg = <0x0160 0x4>;
2132                                         clocks =
2133                                                 <&dummy>,               <&clk_apll>,
2134                                                 <&clk_gpll>,    <&aclk_bus>,
2135
2136                                                 <&hclk_bus>,    <&pclk_bus>,
2137                                                 <&dummy>,               <&aclk_bus>,
2138
2139                                                 <&clk_dpll>,    <&clk_gpll>,
2140                                                 <&clk_gpll>,    <&clk_cpll>,
2141
2142                                                 <&xin24m>,              <&dummy>,
2143                                                 <&dummy>,               <&dummy>;
2144
2145                                         clock-output-names =
2146                                                 "reserved",                     "reserved",      /* do not use bit1 = "core_apll" */
2147                                                 "clk_arm_gpll",         "g_aclk_bus",
2148
2149                                                 "hclk_bus",             "pclk_bus",
2150                                                 "reserved",             "aclk_bus_2pmu",
2151
2152                                                 "reserved",             "reserved",             /*"clk_ddr_dpll",       "clk_ddr_gpll",*/
2153                                                 "reserved",             "reserved",             /*"clk_bus_gpll",       "clk_bus_cpll",*/
2154
2155                                                 "clk_acc_efuse",                "reserved",
2156                                                 "reserved",             "reserved";
2157                                         rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>;
2158
2159                                         #clock-cells = <1>;
2160                                 };
2161
2162                                 clk_gates1: gate-clk@0164 {
2163                                         compatible = "rockchip,rk3188-gate-clk";
2164                                         reg = <0x0164 0x4>;
2165                                         clocks =
2166                                                 <&xin24m>,              <&xin24m>,
2167                                                 <&xin24m>,              <&xin24m>,
2168
2169                                                 <&xin24m>,              <&xin24m>,
2170                                                 <&dummy>,               <&dummy>,
2171
2172                                                 <&clk_uart0_pll>,               <&uart0_frac>,
2173                                                 <&clk_uart1_div>,               <&uart1_frac>,
2174
2175                                                 <&clk_uart2_div>,               <&uart2_frac>,
2176                                                 <&clk_uart3_div>,               <&uart3_frac>;
2177
2178                                         clock-output-names =
2179                                                 "clk_timer0",           "clk_timer1",
2180                                                 "clk_timer2",           "clk_timer3",
2181
2182                                                 "clk_timer4",           "clk_timer5",
2183                                                 "reserved",                     "reserved",
2184
2185                                                 "clk_uart0_pll",        "uart0_frac",
2186                                                 "clk_uart1_div",        "uart1_frac",
2187
2188                                                 "clk_uart2_div",        "uart2_frac",
2189                                                 "clk_uart3_div",        "uart3_frac";
2190
2191                                          rockchip,suspend-clkgating-setting=<0x0 0x0>;
2192                                         #clock-cells = <1>;
2193                                 };
2194
2195                                 clk_gates2: gate-clk@0168 {
2196                                         compatible = "rockchip,rk3188-gate-clk";
2197                                         reg = <0x0168 0x4>;
2198                                         clocks =
2199                                                 <&aclk_peri>,           <&aclk_peri>,
2200                                                 <&hclk_peri>,           <&pclk_peri>,
2201
2202                                                 <&dummy>,               <&clk_mac_pll>,
2203                                                 <&clk_hsadc_pll>,               <&clk_tsadc>,
2204
2205                                                 <&clk_saradc>,          <&clk_spi0>,
2206                                                 <&clk_spi1>,            <&clk_spi2>,
2207
2208                                                 <&clk_uart4_div>,               <&uart4_frac>,
2209                                                 <&dummy>,               <&dummy>;
2210
2211                                         clock-output-names =
2212                                                 "aclk_peri",            "reserved", /*"g_aclk_periph",*/
2213                                                 "hclk_peri",            "pclk_peri",
2214
2215                                                 "reserved",             "clk_mac_pll",
2216                                                 "clk_hsadc_pll",                "clk_tsadc",
2217
2218                                                 "clk_saradc",           "clk_spi0",
2219                                                 "clk_spi1",             "clk_spi2",
2220
2221                                                 "clk_uart4_div",                "uart4_frac",
2222                                                 "reserved",             "reserved";
2223                                             rockchip,suspend-clkgating-setting=<0x000f 0x000f>;
2224
2225                                         #clock-cells = <1>;
2226                                 };
2227
2228                                 clk_gates3: gate-clk@016c {
2229                                         compatible = "rockchip,rk3188-gate-clk";
2230                                         reg = <0x016c 0x4>;
2231                                         clocks =
2232                                                 <&aclk_vio0>,           <&dclk_lcdc0>,
2233                                                 <&aclk_vio1>,           <&dclk_lcdc1>,
2234
2235                                                 <&clk_rga>,                     <&aclk_rga>,
2236                                                 <&hsicphy_480m>,                <&clk_cif_pll>,
2237
2238                                                 <&dummy>,               <&clk_vepu>,
2239                                                 <&dummy>,               <&clk_vdpu>,
2240
2241                                                 <&clk_edp_24m>,         <&clk_edp>,
2242                                                 <&clk_isp>,             <&clk_isp_jpe>;
2243
2244                                         clock-output-names =
2245                                                 "aclk_vio0",            "dclk_lcdc0",
2246                                                 "aclk_vio1",            "dclk_lcdc1",
2247
2248                                                 "clk_rga",              "aclk_rga",
2249                                                 "hsicphy_480m",         "clk_cif_pll",
2250
2251                                                 /*Not use hclk_vpu_gate tmp, fixme*/
2252                                                 "reserved",             "clk_vepu",
2253                                                 "reserved",             "clk_vdpu",
2254
2255                                                 "clk_edp_24m",          "clk_edp",
2256                                                 "clk_isp",              "clk_isp_jpe";
2257                                                 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
2258
2259                                         #clock-cells = <1>;
2260                                 };
2261
2262                                 clk_gates4: gate-clk@0170 {
2263                                         compatible = "rockchip,rk3188-gate-clk";
2264                                         reg = <0x0170 0x4>;
2265                                         clocks =
2266                                                 <&clk_i2s_out>,         <&clk_i2s_pll>,
2267                                                 <&i2s_frac>,            <&clk_i2s>,
2268
2269                                                 <&spdif_div>,           <&spdif_frac>,
2270                                                 <&clk_spdif>,           <&spdif_8ch_div>,
2271
2272                                                 <&spdif_8ch_frac>,              <&clk_spdif_8ch>,
2273                                                 <&clk_tsp>,             <&clk_tspout>,
2274
2275                                                 <&clk_ddr>,             <&clk_ddr>,
2276                                                 <&jtag_clkin>,          <&dummy>;
2277
2278                                         clock-output-names =
2279                                                 "clk_i2s_out",          "clk_i2s_pll",
2280                                                 "i2s_frac",             "clk_i2s",
2281
2282                                                 "spdif_div",            "spdif_frac",
2283                                                 "clk_spdif",            "spdif_8ch_div",
2284
2285                                                 "spdif_8ch_frac",               "clk_spdif_8ch",
2286                                                 "clk_tsp",              "clk_tspout",
2287
2288                                                 /* Not use these ddr gates */
2289                                                 "reserved",             "reserved",        /*"g_clk_ddrphy0",           "g_clk_ddrphy1",*/
2290                                                 "clk_jtag",             "reserved";             /*"testclk_gate_en";*/
2291
2292                                             rockchip,suspend-clkgating-setting=<0xf000 0xf000>;
2293                                         #clock-cells = <1>;
2294                                 };
2295
2296                                 clk_gates5: gate-clk@0174 {
2297                                         compatible = "rockchip,rk3188-gate-clk";
2298                                         reg = <0x0174 0x4>;
2299                                         clocks =
2300                                                 <&clk_mac>,             <&clk_mac>,
2301                                                 <&clk_mac>,             <&clk_mac>,
2302
2303                                                 <&clk_crypto>,          <&clk_nandc0>,
2304                                                 <&clk_nandc1>,          <&clk_gpu>,
2305
2306                                                 <&pclk_pd_pmu>,         <&xin24m>,
2307                                                 <&xin24m>,              <&xin32k>,
2308
2309                                                 <&xin24m>,              <&xin24m>,
2310                                                 <&usbphy_480m>,         <&xin24m>;
2311
2312                                         clock-output-names =
2313                                                 "g_clk_mac_rx",         "g_clk_mac_tx",
2314                                                 "g_clk_mac_ref",        "g_mac_refout",
2315
2316                                                 "clk_crypto",           "clk_nandc0",
2317                                                 "clk_nandc1",           "clk_gpu",
2318
2319                                                 "pclk_pd_pmu",          "g_clk_pvtm_core",
2320                                                 "g_clk_pvtm_gpu",               "g_hdmi_cec_clk",
2321
2322                                                 "g_hdmi_hdcp_clk",              "g_ps2c_clk",
2323                                                 "usbphy_480m",          "g_mipidsi_24m";
2324                                                 rockchip,suspend-clkgating-setting=<0x0100 0x0100>;
2325
2326                                         #clock-cells = <1>;
2327                                 };
2328
2329                                 clk_gates6: gate-clk@0178 {
2330                                         compatible = "rockchip,rk3188-gate-clk";
2331                                         reg = <0x0178 0x4>;
2332                                         clocks =
2333                                                 <&hclk_peri>,           <&pclk_peri>,
2334                                                 <&aclk_peri>,           <&aclk_peri>,
2335
2336                                                 <&pclk_peri>,           <&pclk_peri>,
2337                                                 <&pclk_peri>,           <&pclk_peri>,
2338
2339                                                 <&pclk_peri>,           <&pclk_peri>,
2340                                                 <&dummy>,                       <&pclk_peri>,
2341
2342                                                 <&pclk_peri>,           <&pclk_peri>,
2343                                                 <&pclk_peri>,           <&pclk_peri>;
2344
2345                                         clock-output-names =
2346                                                 "g_hp_matrix",          "g_pp_axi_matrix",
2347                                                 "g_ap_axi_matrix",              "g_aclk_dmac2",
2348
2349                                                 "g_pclk_spi0",          "g_pclk_spi1",
2350                                                 "g_pclk_spi2",          "g_pclk_ps2c",
2351
2352                                                 "g_pclk_uart0",         "g_pclk_uart1",
2353                                                 "reserved",             "g_pclk_uart3",
2354
2355                                                 "g_pclk_uart4",         "g_pclk_i2c2",
2356                                                 "g_pclk_i2c3",          "g_pclk_i2c4";
2357                                             rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
2358
2359                                         #clock-cells = <1>;
2360                                 };
2361
2362                                 clk_gates7: gate-clk@017c {
2363                                         compatible = "rockchip,rk3188-gate-clk";
2364                                         reg = <0x017c 0x4>;
2365                                         clocks =
2366                                                 <&pclk_peri>,           <&pclk_peri>,
2367                                                 <&pclk_peri>,           <&pclk_peri>,
2368
2369                                                 <&hclk_peri>,           <&hclk_peri>,
2370                                                 <&hclk_peri>,           <&hclk_peri>,
2371
2372                                                 <&hclk_peri>,           <&hclk_peri>,
2373                                                 <&hclk_peri>,           <&aclk_peri>,
2374
2375                                                 <&hclk_peri>,           <&hclk_peri>,
2376                                                 <&hclk_peri>,           <&hclk_peri>;
2377
2378                                         clock-output-names =
2379                                                 "g_pclk_i2c5",          "g_pclk_saradc",
2380                                                 "g_pclk_tsadc",         "g_pclk_sim",
2381
2382                                                 "g_hclk_otg0",          "g_pmu_hclk_otg0",
2383                                                 "g_hclk_host0",         "g_hclk_host1",
2384
2385                                                 "g_hclk_hsic",          "g_hclk_usb_peri",
2386                                                 "g_hp_ahb_arbi",                "g_aclk_peri_niu",
2387
2388                                                 "g_h_emem_peri",                "g_hclk_mem_peri",
2389                                                 "g_hclk_nandc0",                "g_hclk_nandc1";
2390                                                 rockchip,suspend-clkgating-setting=<0x0c00 0xc000>;
2391
2392                                         #clock-cells = <1>;
2393                                 };
2394
2395                                 clk_gates8: gate-clk@0180 {
2396                                         compatible = "rockchip,rk3188-gate-clk";
2397                                         reg = <0x0180 0x4>;
2398                                         clocks =
2399                                                 <&aclk_peri>,           <&pclk_peri>,
2400                                                 <&aclk_peri>,           <&hclk_peri>,
2401
2402                                                 <&hclk_peri>,           <&hclk_peri>,
2403                                                 <&hclk_peri>,           <&hclk_peri>,
2404
2405                                                 <&hclk_peri>,           <&hsadc_0_tsp>,
2406                                                 <&hsadc_1_tsp>,         <&io_27m_in>,
2407
2408                                                 <&aclk_peri>,           <&dummy>,
2409                                                 <&dummy>,               <&dummy>;
2410
2411                                         clock-output-names =
2412                                                 "g_aclk_gmac",          "g_pclk_gmac",
2413                                                 "g_hclk_gps",           "g_hclk_sdmmc",
2414
2415                                                 "g_hclk_sdio0",         "g_hclk_sdio1",
2416                                                 "g_hclk_emmc",          "g_hclk_hsadc",
2417
2418                                                 "g_hclk_tsp",           "g_hsadc_0_tsp",
2419                                                 "g_hsadc_1_tsp",                "g_clk_27m_tsp",
2420
2421                                                 "g_aclk_peri_mmu",              "reserved",
2422                                                 "reserved",             "reserved";
2423
2424                                         rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
2425                                         #clock-cells = <1>;
2426                                 };
2427
2428                                 clk_gates9: gate-clk@0184 {
2429                                         compatible = "rockchip,rk3188-gate-clk";
2430                                         reg = <0x0184 0x4>;
2431                                         clocks =
2432                                                 <&dummy>,               <&dummy>,
2433                                                 <&dummy>,               <&dummy>,
2434
2435                                                 <&dummy>,               <&dummy>,
2436                                                 <&dummy>,               <&dummy>,
2437
2438                                                 <&dummy>,               <&dummy>,
2439                                                 <&dummy>,               <&dummy>,
2440
2441                                                 <&dummy>,               <&dummy>,
2442                                                 <&dummy>,               <&dummy>;
2443
2444                                         clock-output-names =
2445                                                 "reserved",             "reserved",             /*"aclk_video_gate_en", "hclk_video_clock_en",*/
2446                                                 "reserved",             "reserved",
2447
2448                                                 "reserved",             "reserved",
2449                                                 "reserved",             "reserved",
2450
2451                                                 "reserved",             "reserved",
2452                                                 "reserved",             "reserved",
2453
2454                                                 "reserved",             "reserved",
2455                                                 "reserved",             "reserved";
2456                                     rockchip,suspend-clkgating-setting=<0x0 0x0>;
2457
2458                                         #clock-cells = <1>;
2459                                 };
2460
2461                                 clk_gates10: gate-clk@0188 {
2462                                         compatible = "rockchip,rk3188-gate-clk";
2463                                         reg = <0x0188 0x4>;
2464                                         clocks =
2465                                                 <&pclk_bus>,            <&pclk_bus>,
2466                                                 <&pclk_bus>,            <&pclk_bus>,
2467
2468                                                 <&aclk_bus>,            <&aclk_bus>,
2469                                                 <&aclk_bus>,            <&aclk_bus>,
2470
2471                                                 <&hclk_bus>,            <&hclk_bus>,
2472                                                 <&hclk_bus>,            <&hclk_bus>,
2473
2474                                                 <&aclk_bus>,            <&aclk_bus>,
2475                                                 <&pclk_bus>,            <&pclk_bus>;
2476
2477                                         clock-output-names =
2478                                                 "g_pclk_pwm",           "g_pclk_timer",
2479                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
2480
2481                                                 "g_aclk_intmem",                "g_clk_intmem0",
2482                                                 "g_clk_intmem1",                "g_clk_intmem2",
2483
2484                                                 "g_hclk_i2s",           "g_hclk_rom",
2485                                                 "g_hclk_spdif",         "g_h_spdif_8ch",
2486
2487                                                 "g_aclk_dmac1",         "g_aclk_strc_sys",
2488                                                 "reserved",             "reserved";     /*"g_p_ddrupctl0",      "g_pclk_publ0";*/
2489
2490                                                 //rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>;          // use sram  mem no gating
2491                                                 rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>;       // pwm logic vol
2492
2493                                         #clock-cells = <1>;
2494                                 };
2495
2496                                 clk_gates11: gate-clk@018c {
2497                                         compatible = "rockchip,rk3188-gate-clk";
2498                                         reg = <0x018c 0x4>;
2499                                         clocks =
2500                                                 <&pclk_bus>,            <&pclk_bus>,
2501                                                 <&pclk_bus>,            <&pclk_bus>,
2502
2503                                                 <&dummy>,               <&dummy>,
2504                                                 <&aclk_bus>,            <&hclk_bus>,
2505
2506                                                 <&aclk_bus>,            <&pclk_bus>,
2507                                                 <&pclk_bus>,            <&pclk_bus>,
2508
2509                                                 <&dummy>,               <&dummy>,
2510                                                 <&dummy>,               <&dummy>;
2511
2512                                         clock-output-names =
2513                                                 "reserved",     "reserved",     /*"g_p_ddrupctl1",      "g_pclk_publ1",*/
2514                                                 "g_p_efuse_1024",       "g_pclk_tzpc",
2515
2516                                                 "reserved",             "reserved",             /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
2517                                                 "g_aclk_crypto",        "g_hclk_crypto",
2518
2519                                                 "g_aclk_ccp",   "g_pclk_uart2",
2520                                                 "g_p_efuse_256",        "g_pclk_rkpwm",
2521
2522                                                 "reserved",             "reserved",
2523                                                 "reserved",             "reserved";
2524                                                rockchip,suspend-clkgating-setting=<0x0033 0x0033>;
2525
2526                                         #clock-cells = <1>;
2527                                 };
2528
2529                                 clk_gates12: gate-clk@0190 {
2530                                         compatible = "rockchip,rk3188-gate-clk";
2531                                         reg = <0x0190 0x4>;
2532                                         clocks =
2533                                                 <&clk_core0>,           <&clk_core1>,
2534                                                 <&clk_core2>,           <&clk_core3>,
2535
2536                                                 <&clk_l2ram>,           <&aclk_core_m0>,
2537                                                 <&aclk_core_mp>,                <&atclk_core>,
2538
2539                                                 <&pclk_dbg_src>,                <&clk_gates12 8>,
2540                                                 <&clk_gates12 8>,               <&clk_gates12 8>,
2541
2542                                                 <&dummy>,               <&dummy>,
2543                                                 <&dummy>,               <&dummy>;
2544
2545                                         clock-output-names =
2546                                                 "clk_core0",            "clk_core1",
2547                                                 "clk_core2",            "clk_core3",
2548
2549                                                 "clk_l2ram",            "aclk_core_m0",
2550                                                 "aclk_core_mp",         "atclk_core",
2551
2552                                                 "pclk_dbg_src",         "reserved",     /*"g_dbg_core_clk",*/
2553                                                 "reserved",             "reserved",             /*"g_cs_dbg_clk",       "g_pclk_core_niu",*/
2554
2555                                                 "reserved",             "reserved",
2556                                                 "reserved",             "reserved";
2557                                             rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>;
2558
2559                                         #clock-cells = <1>;
2560                                 };
2561
2562                                 clk_gates13: gate-clk@0194 {
2563                                         compatible = "rockchip,rk3188-gate-clk";
2564                                         reg = <0x0194 0x4>;
2565                                         clocks =
2566                                                 <&clk_sdmmc>,           <&clk_sdio0>,
2567                                                 <&clk_sdio1>,           <&clk_emmc>,
2568
2569                                                 <&xin24m>,              <&xin24m>,
2570                                                 <&xin24m>,              <&xin32k>,
2571
2572                                                 <&aclk_bus_src>,                <&xin12m>,
2573                                                 <&xin24m>,              <&xin24m>,
2574
2575                                                 <&dummy>,               <&aclk_hevc>,
2576                                                 <&clk_hevc_cabac>,              <&clk_hevc_core>;
2577
2578                                         clock-output-names =
2579                                                 "clk_sdmmc",            "clk_sdio0",
2580                                                 "clk_sdio1",            "clk_emmc",
2581
2582                                                 "clk_otgphy0",          "clk_otgphy1",
2583                                                 "clk_otgphy2",          "clk_otg_adp",
2584
2585                                                 "g_clk_c2c_host",               "g_clk_hsic_12m",
2586                                                 "g_clk_lcdc_pwm0",              "g_clk_lcdc_pwm1",
2587
2588                                                 "g_clk_wifi",           "aclk_hevc",
2589                                                 "clk_hevc_cabac",               "clk_hevc_core";
2590                                                 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2591
2592                                         #clock-cells = <1>;
2593                                 };
2594
2595                                 clk_gates14: gate-clk@0198 {
2596                                         compatible = "rockchip,rk3188-gate-clk";
2597                                         reg = <0x0198 0x4>;
2598                                         clocks =
2599                                                 <&dummy>,               <&pclk_pd_alive>,
2600                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2601
2602                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2603                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2604
2605                                                 <&pclk_pd_alive>,               <&dummy>,
2606                                                 <&dummy>,               <&pclk_pd_alive>,
2607
2608                                                 <&pclk_pd_alive>,               <&dummy>,
2609                                                 <&dummy>,               <&dummy>;
2610
2611                                         clock-output-names =
2612                                                 "reserved",             "g_pclk_gpio1",
2613                                                 "g_pclk_gpio2",         "g_pclk_gpio3",
2614
2615                                                 "g_pclk_gpio4",         "g_pclk_gpio5",
2616                                                 "g_pclk_gpio6",         "g_pclk_gpio7",
2617
2618                                                 "g_pclk_gpio8",         "reserved",
2619                                                 "reserved",             "g_pclk_grf",
2620
2621                                                 "g_p_alive_niu",                "reserved",
2622                                                 "reserved",             "reserved";
2623                                                 //rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
2624
2625                                                 rockchip,suspend-clkgating-setting=<0x1801 0x1801>;
2626
2627                                         #clock-cells = <1>;
2628                                 };
2629
2630                                 clk_gates15: gate-clk@019c {
2631                                         compatible = "rockchip,rk3188-gate-clk";
2632                                         reg = <0x019c 0x4>;
2633                                         clocks =
2634                                                 <&aclk_rga>,            <&hclk_vio>,
2635                                                 <&aclk_vio0>,           <&hclk_vio>,
2636
2637                                                 <&dummy>,               <&aclk_vio0>,
2638                                                 <&hclk_vio>,            <&aclk_vio1>,
2639
2640                                                 <&hclk_vio>,            <&hclk_vio>,
2641                                                 <&hclk_vio>,            <&aclk_vio0>,
2642
2643                                                 <&aclk_vio1>,           <&aclk_rga>,
2644                                                 <&aclk_vio0>,           <&hclk_vio>;
2645
2646                                         clock-output-names =
2647                                                 "reserved", /*"g_aclk_rga",*/   "g_hclk_rga",
2648                                                 "g_aclk_iep",           "g_hclk_iep",
2649
2650                                                 "g_aclk_lcdc_iep",              "g_aclk_lcdc0",
2651                                                 "g_hclk_lcdc0",         "g_aclk_lcdc1",
2652
2653                                                 "g_hclk_lcdc1",         "g_h_vio_ahb",
2654                                                 "g_hclk_vio_niu",               "g_aclk_vio0_niu",
2655
2656                                                 "g_aclk_vio1_niu",              "reserved",/*"g_aclk_rga_niu",*/
2657                                                 "g_aclk_vip",           "g_hclk_vip";
2658                                                 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2659
2660                                         #clock-cells = <1>;
2661                                 };
2662
2663                                 clk_gates16: gate-clk@01a0 {
2664                                         compatible = "rockchip,rk3188-gate-clk";
2665                                         reg = <0x01a0 0x4>;
2666                                         clocks =
2667                                                 <&pclkin_cif>,          <&hclk_vio>,
2668                                                 <&aclk_vio1>,           <&pclkin_isp>,
2669
2670                                                 <&hclk_vio>,            <&hclk_vio>,
2671                                                 <&hclk_vio>,            <&hclk_vio>,
2672
2673                                                 <&hclk_vio>,            <&hclk_vio>,
2674                                                 <&hclk_vio>,            <&hclk_vio>,
2675
2676                                                 <&dummy>,               <&dummy>,
2677                                                 <&dummy>,               <&dummy>;
2678
2679                                         clock-output-names =
2680                                                 "g_pclkin_cif",         "g_hclk_isp",
2681                                                 "g_aclk_isp",           "g_pclkin_isp",
2682
2683                                                 "g_p_mipi_dsi0",                "g_p_mipi_dsi1",
2684                                                 "g_p_mipi_csi",         "g_pclk_lvds_phy",
2685
2686                                                 "g_pclk_edp_ctrl",              "g_p_hdmi_ctrl",
2687                                                 "g_hclk_vio2_h2p",              "g_pclk_vio2_h2p",
2688
2689                                                 "reserved",             "reserved",
2690                                                 "reserved",             "reserved";
2691                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
2692
2693                                         #clock-cells = <1>;
2694                                 };
2695
2696                                 clk_gates17: gate-clk@01a4 {
2697                                         compatible = "rockchip,rk3188-gate-clk";
2698                                         reg = <0x01a4 0x4>;
2699                                         clocks =
2700                                                 <&pclk_pd_pmu>,         <&pclk_pd_pmu>,
2701                                                 <&pclk_pd_pmu>,         <&pclk_pd_pmu>,
2702
2703                                                 <&pclk_pd_pmu>,         <&dummy>,
2704                                                 <&dummy>,               <&dummy>,
2705
2706                                                 <&dummy>,               <&dummy>,
2707                                                 <&dummy>,               <&dummy>,
2708
2709                                                 <&dummy>,               <&dummy>,
2710                                                 <&dummy>,               <&dummy>;
2711
2712                                         clock-output-names =
2713                                                 "g_pclk_pmu",           "g_pclk_intmem1",
2714                                                 "g_pclk_pmu_niu",               "g_pclk_sgrf",
2715
2716                                                 "g_pclk_gpio0",         "reserved",
2717                                                 "reserved",             "reserved",
2718
2719                                                 "reserved",             "reserved",
2720                                                 "reserved",             "reserved",
2721
2722                                                 "reserved",             "reserved",
2723                                                 "reserved",             "reserved";
2724                                              rockchip,suspend-clkgating-setting=<0x01f 0x01f>;
2725
2726                                         #clock-cells = <1>;
2727                                 };
2728
2729                                 clk_gates18: gate-clk@01a8 {
2730                                         compatible = "rockchip,rk3188-gate-clk";
2731                                         reg = <0x01a8 0x4>;
2732                                         clocks =
2733                                                 <&clk_gpu>,             <&dummy>,
2734                                                 <&dummy>,               <&dummy>,
2735
2736                                                 <&dummy>,               <&dummy>,
2737                                                 <&dummy>,               <&dummy>,
2738
2739                                                 <&dummy>,               <&dummy>,
2740                                                 <&dummy>,               <&dummy>,
2741
2742                                                 <&dummy>,               <&dummy>,
2743                                                 <&dummy>,               <&dummy>;
2744
2745                                         clock-output-names =
2746                                                 "reserved", /*"g_aclk_gpu",*/   "reserved",
2747                                                 "reserved",             "reserved",
2748
2749                                                 "reserved",             "reserved",
2750                                                 "reserved",             "reserved",
2751
2752                                                 "reserved",             "reserved",
2753                                                 "reserved",             "reserved",
2754
2755                                                 "reserved",             "reserved",
2756                                                 "reserved",             "reserved";
2757
2758                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
2759                                         #clock-cells = <1>;
2760                                 };
2761
2762                         };
2763                 };
2764         };
2765 };