arch/arm/boot/dts/rk3288-clocks.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/rockchip,rk3288.h>
  15
  16 /{
  17         clocks {
  18                 compatible = "rockchip,rk-clocks";
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges = <0x0 0xFF760000 0x01b0>;
  22
  23                 fixed_rate_cons {
  24                         compatible = "rockchip,rk-fixed-rate-cons";
  25
  26                         xin24m: xin24m {
  27                                 compatible = "rockchip,rk-fixed-clock";
  28                                 clock-output-names = "xin24m";
  29                                 clock-frequency = <24000000>;
  30                                 #clock-cells = <0>;
  31                         };
  32
  33                         xin12m: xin12m {
  34                                 compatible = "rockchip,rk-fixed-clock";
  35                                 clocks = <&xin24m>;
  36                                 clock-output-names = "xin12m";
  37                                 clock-frequency = <12000000>;
  38                                 #clock-cells = <0>;
  39                         };
  40
  41                         xin32k: xin32k {
  42                                 compatible = "rockchip,rk-fixed-clock";
  43                                 clock-output-names = "xin32k";
  44                                 clock-frequency = <32000>;
  45                                 #clock-cells = <0>;
  46                         };
  47
  48                         io_27m_in: io_27m_in {
  49                                 compatible = "rockchip,rk-fixed-clock";
  50                                 clock-output-names = "io_27m_in";
  51                                 clock-frequency = <27000000>;
  52                                 #clock-cells = <0>;
  53                         };
  54
  55                         dummy: dummy {
  56                                 compatible = "rockchip,rk-fixed-clock";
  57                                 clock-output-names = "dummy";
  58                                 clock-frequency = <0>;
  59                                 #clock-cells = <0>;
  60                         };
  61
  62                         dummy_480m: dummy_480m {
  63                                 compatible = "rockchip,rk-fixed-clock";
  64                                 clock-output-names = "dummy_480m";
  65                                 clock-frequency = <0>;
  66                                 #clock-cells = <0>;
  67                         };
  68
  69                         i2s_clkin: i2s_clkin {
  70                                 compatible = "rockchip,rk-fixed-clock";
  71                                 clock-output-names = "i2s_clkin";
  72                                 clock-frequency = <0>;
  73                                 #clock-cells = <0>;
  74                         };
  75
  76                         edp_24m_clkin: edp_24m_clkin {
  77                                 compatible = "rockchip,rk-fixed-clock";
  78                                 #clock-cells = <0>;
  79                                 clock-output-names = "edp_24m_clkin";
  80                                 clock-frequency = <0>;
  81                         };
  82
  83                         gmac_clkin: gmac_clkin {
  84                                 compatible = "rockchip,rk-fixed-clock";
  85                                 #clock-cells = <0>;
  86                                 clock-output-names = "gmac_clkin";
  87                                 clock-frequency = <0>;
  88                         };
  89
  90                         clk_hsadc_ext: clk_hsadc_ext {
  91                                 compatible = "rockchip,rk-fixed-clock";
  92                                 #clock-cells = <0>;
  93                                 clock-output-names = "clk_hsadc_ext";
  94                                 clock-frequency = <0>;
  95                         };
  96
  97                         jtag_clkin: jtag_clkin {
  98                                 compatible = "rockchip,rk-fixed-clock";
  99                                 #clock-cells = <0>;
 100                                 clock-output-names = "jtag_clkin";
 101                                 clock-frequency = <0>;
 102                         };
 103
 104                         pclkin_cif: pclkin_cif {
 105                                 compatible = "rockchip,rk-fixed-clock";
 106                                 #clock-cells = <0>;
 107                                 clock-output-names = "pclkin_cif";
 108                                 clock-frequency = <0>;
 109                         };
 110
 111                         pclkin_isp: pclkin_isp {
 112                                 compatible = "rockchip,rk-fixed-clock";
 113                                 #clock-cells = <0>;
 114                                 clock-output-names = "pclkin_isp";
 115                                 clock-frequency = <0>;
 116                         };
 117
 118                         hsadc_0_tsp: hsadc_0_tsp {
 119                                 compatible = "rockchip,rk-fixed-clock";
 120                                 #clock-cells = <0>;
 121                                 clock-output-names = "hsadc_0_tsp";
 122                                 clock-frequency = <0>;
 123                         };
 124
 125                         hsadc_1_tsp: hsadc_1_tsp {
 126                                 compatible = "rockchip,rk-fixed-clock";
 127                                 #clock-cells = <0>;
 128                                 clock-output-names = "hsadc_1_tsp";
 129                                 clock-frequency = <0>;
 130                         };
 131
 132                 };
 133
 134                 fixed_factor_cons {
 135                                 compatible = "rockchip,rk-fixed-factor-cons";
 136
 137                         otgphy0_480m: otgphy0_480m {
 138                                 compatible = "rockchip,rk-fixed-factor-clock";
 139                                 clocks = <&clk_gates13 4>;
 140                                 clock-output-names = "otgphy0_480m";
 141                                 clock-div = <1>;
 142                                 clock-mult = <20>;
 143                                 #clock-cells = <0>;
 144                         };
 145
 146                         otgphy1_480m: otgphy1_480m {
 147                                 compatible = "rockchip,rk-fixed-factor-clock";
 148                                 clocks = <&clk_gates13 5>;
 149                                 clock-output-names = "otgphy1_480m";
 150                                 clock-div = <1>;
 151                                 clock-mult = <20>;
 152                                 #clock-cells = <0>;
 153                         };
 154
 155                         otgphy2_480m: otgphy2_480m {
 156                                 compatible = "rockchip,rk-fixed-factor-clock";
 157                                 clocks = <&clk_gates13 6>;
 158                                 clock-output-names = "otgphy2_480m";
 159                                 clock-div = <1>;
 160                                 clock-mult = <20>;
 161                                 #clock-cells = <0>;
 162                         };
 163
 164                         clk_hsadc_inv: clk_hsadc_inv {
 165                                 compatible = "rockchip,rk-fixed-factor-clock";
 166                                 clocks = <&clk_hsadc_out>;
 167                                 clock-output-names = "clk_hsadc_inv";
 168                                 clock-div = <1>;
 169                                 clock-mult = <1>;
 170                                 #clock-cells = <0>;
 171                         };
 172
 173                         pclkin_cif_inv: pclkin_cif_inv {
 174                                 compatible = "rockchip,rk-fixed-factor-clock";
 175                                 clocks = <&clk_gates16 0>;
 176                                 clock-output-names = "pclkin_cif_inv";
 177                                 clock-div = <1>;
 178                                 clock-mult = <1>;
 179                                 #clock-cells = <0>;
 180                         };
 181
 182                         pclkin_isp_inv: pclkin_isp_inv {
 183                                 compatible = "rockchip,rk-fixed-factor-clock";
 184                                 clocks = <&clk_gates16 3>;
 185                                 clock-output-names = "pclkin_isp_inv";
 186                                 clock-div = <1>;
 187                                 clock-mult = <1>;
 188                                 #clock-cells = <0>;
 189                         };
 190
 191                         hclk_vepu: hclk_vepu {
 192                                 compatible = "rockchip,rk-fixed-factor-clock";
 193                                 clocks = <&clk_vepu>;
 194                                 clock-output-names = "hclk_vepu";
 195                                 clock-div = <4>;
 196                                 clock-mult = <1>;
 197                                 #clock-cells = <0>;
 198                         };
 199
 200                         hclk_vdpu: hclk_vdpu {
 201                                 compatible = "rockchip,rk-fixed-factor-clock";
 202                                 clocks = <&clk_vdpu>;
 203                                 clock-output-names = "hclk_vdpu";
 204                                 clock-div = <4>;
 205                                 clock-mult = <1>;
 206                                 #clock-cells = <0>;
 207                         };
 208                 };
 209
 210                 pd_cons {
 211                         compatible = "rockchip,rk-pd-cons";
 212
 213                         pd_gpu: pd_gpu {
 214                                 compatible = "rockchip,rk-pd-clock";
 215                                 clock-output-names = "pd_gpu";
 216                                 rockchip,pd-id = <CLK_PD_GPU>;
 217                                 #clock-cells = <0>;
 218                         };
 219
 220                         pd_video: pd_video {
 221                                 compatible = "rockchip,rk-pd-clock";
 222                                 clock-output-names = "pd_video";
 223                                 rockchip,pd-id = <CLK_PD_VIDEO>;
 224                                 #clock-cells = <0>;
 225                         };
 226
 227                         pd_vio: pd_vio {
 228                                 compatible = "rockchip,rk-pd-clock";
 229                                 clock-output-names = "pd_vio";
 230                                 rockchip,pd-id = <CLK_PD_VIO>;
 231                                 #clock-cells = <0>;
 232                         };
 233
 234                         pd_hevc: pd_hevc {
 235                                 compatible = "rockchip,rk-pd-clock";
 236                                 clock-output-names = "pd_hevc";
 237                                 rockchip,pd-id = <CLK_PD_HEVC>;
 238                                 #clock-cells = <0>;
 239                         };
 240
 241                 };
 242
 243
 244                 clock_regs {
 245                         compatible = "rockchip,rk-clock-regs";
 246                         #address-cells = <1>;
 247                         #size-cells = <1>;
 248                         reg = <0x0000 0x3ff>;
 249                         ranges;
 250
 251                         /* PLL control regs */
 252                         pll_cons {
 253                                 compatible = "rockchip,rk-pll-cons";
 254                                 #address-cells = <1>;
 255                                 #size-cells = <1>;
 256                                 ranges ;
 257
 258                                 clk_apll: pll-clk@0000 {
 259                                         compatible = "rockchip,rk3188-pll-clk";
 260                                         reg = <0x0000 0x10>;
 261                                         mode-reg = <0x0050 0>;
 262                                         status-reg = <0x0284 6>;
 263                                         clocks = <&xin24m>;
 264                                         clock-output-names = "clk_apll";
 265                                         rockchip,pll-type = <CLK_PLL_3288_APLL>;
 266                                         #clock-cells = <0>;
 267                                 };
 268
 269                                 clk_dpll: pll-clk@0010 {
 270                                         compatible = "rockchip,rk3188-pll-clk";
 271                                         reg = <0x0010 0x10>;
 272                                         mode-reg = <0x0050 4>;
 273                                         status-reg = <0x0284 5>;
 274                                         clocks = <&xin24m>;
 275                                         clock-output-names = "clk_dpll";
 276                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 277                                         #clock-cells = <0>;
 278                                 };
 279
 280                                 clk_cpll: pll-clk@0020 {
 281                                         compatible = "rockchip,rk3188-pll-clk";
 282                                         reg = <0x0020 0x10>;
 283                                         mode-reg = <0x0050 8>;
 284                                         status-reg = <0x0284 7>;
 285                                         clocks = <&xin24m>;
 286                                         clock-output-names = "clk_cpll";
 287                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 288                                         #clock-cells = <0>;
 289                                         #clock-init-cells = <1>;
 290                                 };
 291
 292                                 clk_gpll: pll-clk@0030 {
 293                                         compatible = "rockchip,rk3188-pll-clk";
 294                                         reg = <0x0030 0x10>;
 295                                         mode-reg = <0x0050 12>;
 296                                         status-reg = <0x0284 8>;
 297                                         clocks = <&xin24m>;
 298                                         clock-output-names = "clk_gpll";
 299                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 300                                         #clock-cells = <0>;
 301                                         #clock-init-cells = <1>;
 302                                 };
 303
 304                                 clk_npll: pll-clk@0040 {
 305                                         compatible = "rockchip,rk3188-pll-clk";
 306                                         reg = <0x0040 0x10>;
 307                                         mode-reg = <0x0050 14>;
 308                                         status-reg = <0x0284 9>;
 309                                         clocks = <&xin24m>;
 310                                         clock-output-names = "clk_npll";
 311                                         rockchip,pll-type = <CLK_PLL_3188PLUS>;
 312                                         #clock-cells = <0>;
 313                                         #clock-init-cells = <1>;
 314                                 };
 315
 316                         };
 317
 318                         /* Select control regs */
 319                         clk_sel_cons {
 320                                 compatible = "rockchip,rk-sel-cons";
 321                                 #address-cells = <1>;
 322                                 #size-cells = <1>;
 323                                 ranges;
 324
 325                                 clk_sel_con0: sel-con@0060 {
 326                                         compatible = "rockchip,rk3188-selcon";
 327                                         reg = <0x0060 0x4>;
 328                                         #address-cells = <1>;
 329                                         #size-cells = <1>;
 330
 331                                         aclk_core_m0: aclk_core_m0_div {
 332                                                 compatible = "rockchip,rk3188-div-con";
 333                                                 rockchip,bits = <0 4>;
 334                                                 clocks = <&clk_core>;
 335                                                 clock-output-names = "aclk_core_m0";
 336                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 337                                                 #clock-cells = <0>;
 338                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 339                                         };
 340
 341                                         aclk_core_mp: aclk_core_mp_div {
 342                                                 compatible = "rockchip,rk3188-div-con";
 343                                                 rockchip,bits = <4 4>;
 344                                                 clocks = <&clk_core>;
 345                                                 clock-output-names = "aclk_core_mp";
 346                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 347                                                 #clock-cells = <0>;
 348                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
 349                                         };
 350
 351                                         clk_core_div: clk_core_div {
 352                                                 compatible = "rockchip,rk3188-div-con";
 353                                                 rockchip,bits = <8 5>;
 354                                                 clocks = <&clk_core>;
 355                                                 clock-output-names = "clk_core";
 356                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 357                                                 #clock-cells = <0>;
 358                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
 359                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
 360                                                                         CLK_SET_RATE_NO_REPARENT)>;
 361                                         };
 362
 363                                         /* reg[14:13]: reserved */
 364
 365                                         clk_core: clk_core_mux {
 366                                                 compatible = "rockchip,rk3188-mux-con";
 367                                                 rockchip,bits = <15 1>;
 368                                                 clocks = <&clk_apll>, <&clk_gates0 2>;
 369                                                 clock-output-names = "clk_core";
 370                                                 #clock-cells = <0>;
 371                                                 #clock-init-cells = <1>;
 372                                         };
 373
 374                                 };
 375
 376                                 clk_sel_con1: sel-con@0064 {
 377                                         compatible = "rockchip,rk3188-selcon";
 378                                         reg = <0x0064 0x4>;
 379                                         #address-cells = <1>;
 380                                         #size-cells = <1>;
 381
 382                                         aclk_bus: aclk_bus_div {
 383                                                 compatible = "rockchip,rk3188-div-con";
 384                                                 rockchip,bits = <0 3>;
 385                                                 clocks = <&aclk_bus_src_div>;
 386                                                 clock-output-names = "aclk_bus";
 387                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 388                                                 #clock-cells = <0>;
 389                                                 #clock-init-cells = <1>;
 390                                         };
 391
 392                                         aclk_bus_src_div: aclk_bus_src_div {
 393                                                 compatible = "rockchip,rk3188-div-con";
 394                                                 rockchip,bits = <3 5>;
 395                                                 clocks = <&aclk_bus_src>;
 396                                                 clock-output-names = "aclk_bus_src";
 397                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 398                                                 #clock-cells = <0>;
 399                                                 rockchip,clkops-idx =
 400                                                         <CLKOPS_RATE_MUX_DIV>;
 401                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 402                                         };
 403
 404                                         hclk_bus: hclk_bus_div {
 405                                                 compatible = "rockchip,rk3188-div-con";
 406                                                 rockchip,bits = <8 2>;
 407                                                 clocks = <&aclk_bus>;
 408                                                 clock-output-names = "hclk_bus";
 409                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 410                                                 rockchip,div-relations =
 411                                                                 <0x0 1
 412                                                                  0x1 2
 413                                                                  0x3 4>;
 414                                                 #clock-cells = <0>;
 415                                                 #clock-init-cells = <1>;
 416                                         };
 417
 418                                         /* reg[11:10]: reserved */
 419
 420                                         pclk_bus: pclk_bus_div {
 421                                                 compatible = "rockchip,rk3188-div-con";
 422                                                 rockchip,bits = <12 3>;
 423                                                 clocks = <&aclk_bus>;
 424                                                 clock-output-names = "pclk_bus";
 425                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 426                                                 #clock-cells = <0>;
 427                                                 #clock-init-cells = <1>;
 428                                         };
 429
 430                                         aclk_bus_src: aclk_bus_src_mux {
 431                                                 compatible = "rockchip,rk3188-mux-con";
 432                                                 rockchip,bits = <15 1>;
 433                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 434                                                 /*clocks = <&clk_gates0 11>, <&clk_gates0 10>; FIXME*/
 435                                                 clock-output-names = "aclk_bus_src";
 436                                                 #clock-cells = <0>;
 437                                                 #clock-init-cells = <1>;
 438                                         };
 439
 440                                 };
 441
 442                                 clk_sel_con2: sel-con@0068 {
 443                                         compatible = "rockchip,rk3188-selcon";
 444                                         reg = <0x0068 0x4>;
 445                                         #address-cells = <1>;
 446                                         #size-cells = <1>;
 447
 448                                         clk_tsadc: clk_tsadc_div {
 449                                                 compatible = "rockchip,rk3188-div-con";
 450                                                 rockchip,bits = <0 6>;
 451                                                 clocks = <&xin32k>;
 452                                                 clock-output-names = "clk_tsadc";
 453                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 454                                                 #clock-cells = <0>;
 455                                         };
 456
 457                                         /* reg[7:6]: reserved */
 458
 459                                         testout_div: testout_div {
 460                                                 compatible = "rockchip,rk3188-div-con";
 461                                                 rockchip,bits = <8 5>;
 462                                                 clocks = <&dummy>;
 463                                                 clock-output-names = "testout_div";
 464                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 465                                                 #clock-cells = <0>;
 466                                         };
 467
 468                                         /* reg[15:13]: reserved */
 469                                 };
 470
 471                                 clk_sel_con3: sel-con@006c {
 472                                         compatible = "rockchip,rk3188-selcon";
 473                                         reg = <0x006c 0x4>;
 474                                         #address-cells = <1>;
 475                                         #size-cells = <1>;
 476
 477                                         clk_uart4_div: clk_uart4_div {
 478                                                 compatible = "rockchip,rk3188-div-con";
 479                                                 rockchip,bits = <0 7>;
 480                                                 clocks = <&uart_pll_mux>;
 481                                                 clock-output-names = "clk_uart4_div";
 482                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 483                                                 #clock-cells = <0>;
 484                                         };
 485
 486                                         /* reg[7]: reserved */
 487
 488                                         clk_uart4: uart4_mux {
 489                                                 compatible = "rockchip,rk3188-mux-con";
 490                                                 rockchip,bits = <8 2>;
 491                                                 clocks = <&clk_uart4_div>, <&uart4_frac>, <&xin24m>, <&dummy>;
 492                                                 clock-output-names = "clk_uart4";
 493                                                 #clock-cells = <0>;
 494                                                 rockchip,clkops-idx =
 495                                                         <CLKOPS_RATE_RK3288_I2S>;
 496                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 497                                         };
 498
 499                                         /* reg[15:10]: reserved */
 500
 501                                 };
 502
 503                                 clk_sel_con4: sel-con@0070 {
 504                                         compatible = "rockchip,rk3188-selcon";
 505                                         reg = <0x0070 0x4>;
 506                                         #address-cells = <1>;
 507                                         #size-cells = <1>;
 508
 509                                         i2s_pll_div: i2s_pll_div {
 510                                                 compatible = "rockchip,rk3188-div-con";
 511                                                 rockchip,bits = <0 7>;
 512                                                 clocks = <&clk_i2s_pll>;
 513                                                 clock-output-names = "clk_i2s_pll";
 514                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 515                                                 #clock-cells = <0>;
 516                                                 rockchip,clkops-idx =
 517                                                         <CLKOPS_RATE_MUX_DIV>;
 518                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 519                                         };
 520
 521                                         /* reg[7]: reserved */
 522
 523                                         clk_i2s: i2s_mux {
 524                                                 compatible = "rockchip,rk3188-mux-con";
 525                                                 rockchip,bits = <8 2>;
 526                                                 clocks = <&clk_i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
 527                                                 clock-output-names = "clk_i2s";
 528                                                 #clock-cells = <0>;
 529                                                 rockchip,clkops-idx =
 530                                                         <CLKOPS_RATE_RK3288_I2S>;
 531                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 532                                         };
 533
 534                                         /* reg[11:10]: reserved */
 535
 536                                         clk_i2s_out: i2s_outclk_mux {
 537                                                 compatible = "rockchip,rk3188-mux-con";
 538                                                 rockchip,bits = <12 1>;
 539                                                 clocks = <&clk_i2s>, <&xin12m>;
 540                                                 clock-output-names = "clk_i2s_out";
 541                                                 #clock-cells = <0>;
 542                                         };
 543
 544                                         /* reg[14:13]: reserved */
 545
 546                                         clk_i2s_pll: i2s_pll_mux {
 547                                                 compatible = "rockchip,rk3188-mux-con";
 548                                                 rockchip,bits = <15 1>;
 549                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 550                                                 clock-output-names = "clk_i2s_pll";
 551                                                 #clock-cells = <0>;
 552                                                 #clock-init-cells = <1>;
 553                                         };
 554                                 };
 555
 556                                 clk_sel_con5: sel-con@0074 {
 557                                         compatible = "rockchip,rk3188-selcon";
 558                                         reg = <0x0074 0x4>;
 559                                         #address-cells = <1>;
 560                                         #size-cells = <1>;
 561
 562                                         spdif_div: spdif_div {
 563                                                 compatible = "rockchip,rk3188-div-con";
 564                                                 rockchip,bits = <0 7>;
 565                                                 clocks = <&clk_spdif_pll>;
 566                                                 clock-output-names = "spdif_div";
 567                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 568                                                 #clock-cells = <0>;
 569                                         };
 570
 571                                         /* reg[7]: reserved */
 572
 573                                         clk_spdif: spdif_mux {
 574                                                 compatible = "rockchip,rk3188-mux-con";
 575                                                 rockchip,bits = <8 2>;
 576                                                 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>, <&dummy>;
 577                                                 clock-output-names = "clk_spdif";
 578                                                 #clock-cells = <0>;
 579                                                 rockchip,clkops-idx =
 580                                                         <CLKOPS_RATE_RK3288_I2S>;
 581                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 582                                         };
 583
 584                                         /* reg[14:10]: reserved */
 585
 586                                         clk_spdif_pll: spdif_pll_mux {
 587                                                 compatible = "rockchip,rk3188-mux-con";
 588                                                 rockchip,bits = <15 1>;
 589                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 590                                                 clock-output-names = "clk_spdif_pll";
 591                                                 #clock-cells = <0>;
 592                                         };
 593                                 };
 594
 595                                 clk_sel_con6: sel-con@0078 {
 596                                         compatible = "rockchip,rk3188-selcon";
 597                                         reg = <0x0078 0x4>;
 598                                         #address-cells = <1>;
 599                                         #size-cells = <1>;
 600
 601                                         clk_isp_div: clk_isp_div {
 602                                                 compatible = "rockchip,rk3188-div-con";
 603                                                 rockchip,bits = <0 6>;
 604                                                 clocks = <&clk_isp>;
 605                                                 clock-output-names = "clk_isp";
 606                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 607                                                 #clock-cells = <0>;
 608                                                 rockchip,clkops-idx =
 609                                                         <CLKOPS_RATE_MUX_DIV>;
 610                                         };
 611
 612                                         clk_isp: clk_isp_mux {
 613                                                 compatible = "rockchip,rk3188-mux-con";
 614                                                 rockchip,bits = <6 2>;
 615                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
 616                                                 clock-output-names = "clk_isp";
 617                                                 #clock-cells = <0>;
 618                                                 #clock-init-cells = <1>;
 619                                         };
 620
 621                                         clk_isp_jpe_div: clk_isp_jpe_div {
 622                                                 compatible = "rockchip,rk3188-div-con";
 623                                                 rockchip,bits = <8 6>;
 624                                                 clocks = <&clk_isp_jpe>;
 625                                                 clock-output-names = "clk_isp_jpe";
 626                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 627                                                 #clock-cells = <0>;
 628                                                 rockchip,clkops-idx =
 629                                                         <CLKOPS_RATE_MUX_DIV>;
 630                                         };
 631
 632                                         clk_isp_jpe: clk_isp_jpe_mux {
 633                                                 compatible = "rockchip,rk3188-mux-con";
 634                                                 rockchip,bits = <14 2>;
 635                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
 636                                                 clock-output-names = "clk_isp_jpe";
 637                                                 #clock-cells = <0>;
 638                                                 #clock-init-cells = <1>;
 639                                         };
 640                                 };
 641
 642                                 clk_sel_con7: sel-con@007c {
 643                                         compatible = "rockchip,rk3188-selcon";
 644                                         reg = <0x007c 0x4>;
 645                                         #address-cells = <1>;
 646                                         #size-cells = <1>;
 647
 648                                         uart4_frac: uart4_frac {
 649                                                 compatible = "rockchip,rk3188-frac-con";
 650                                                 clocks = <&clk_uart4_div>;
 651                                                 clock-output-names = "uart4_frac";
 652                                                 /* numerator    denominator */
 653                                                 rockchip,bits = <0 32>;
 654                                                 rockchip,clkops-idx =
 655                                                         <CLKOPS_RATE_FRAC>;
 656                                                 #clock-cells = <0>;
 657                                         };
 658                                 };
 659
 660                                 clk_sel_con8: sel-con@0080 {
 661                                         compatible = "rockchip,rk3188-selcon";
 662                                         reg = <0x0080 0x4>;
 663                                         #address-cells = <1>;
 664                                         #size-cells = <1>;
 665
 666                                         i2s_frac: i2s_frac {
 667                                                 compatible = "rockchip,rk3188-frac-con";
 668                                                 clocks = <&clk_i2s_pll>;
 669                                                 clock-output-names = "i2s_frac";
 670                                                 /* numerator    denominator */
 671                                                 rockchip,bits = <0 32>;
 672                                                 rockchip,clkops-idx =
 673                                                         <CLKOPS_RATE_FRAC>;
 674                                                 #clock-cells = <0>;
 675                                         };
 676                                 };
 677
 678                                 clk_sel_con9: sel-con@0084 {
 679                                         compatible = "rockchip,rk3188-selcon";
 680                                         reg = <0x0084 0x4>;
 681                                         #address-cells = <1>;
 682                                         #size-cells = <1>;
 683
 684                                         spdif_frac: spdif_frac {
 685                                                 compatible = "rockchip,rk3188-frac-con";
 686                                                 clocks = <&spdif_div>;
 687                                                 clock-output-names = "spdif_frac";
 688                                                 /* numerator    denominator */
 689                                                 rockchip,bits = <0 32>;
 690                                                 rockchip,clkops-idx =
 691                                                         <CLKOPS_RATE_FRAC>;
 692                                                 #clock-cells = <0>;
 693                                         };
 694                                 };
 695
 696                                 clk_sel_con10: sel-con@0088 {
 697                                         compatible = "rockchip,rk3188-selcon";
 698                                         reg = <0x0088 0x4>;
 699                                         #address-cells = <1>;
 700                                         #size-cells = <1>;
 701
 702                                         aclk_peri_div: aclk_peri_div {
 703                                                 compatible = "rockchip,rk3188-div-con";
 704                                                 rockchip,bits = <0 5>;
 705                                                 clocks = <&aclk_peri>;
 706                                                 clock-output-names = "aclk_peri";
 707                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 708                                                 #clock-cells = <0>;
 709                                                 rockchip,clkops-idx =
 710                                                         <CLKOPS_RATE_MUX_DIV>;
 711                                                 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
 712                                         };
 713
 714                                         /* reg[7:5]: reserved */
 715
 716                                         hclk_peri: hclk_peri_div {
 717                                                 compatible = "rockchip,rk3188-div-con";
 718                                                 rockchip,bits = <8 2>;
 719                                                 clocks = <&aclk_peri>;
 720                                                 clock-output-names = "hclk_peri";
 721                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 722                                                 rockchip,div-relations =
 723                                                                 <0x0 1
 724                                                                  0x1 2
 725                                                                  0x2 4>;
 726                                                 #clock-cells = <0>;
 727                                                 #clock-init-cells = <1>;
 728                                         };
 729
 730                                         /* reg[11:10]: reserved */
 731
 732                                         pclk_peri: pclk_peri_div {
 733                                                 compatible = "rockchip,rk3188-div-con";
 734                                                 rockchip,bits = <12 2>;
 735                                                 clocks = <&aclk_peri>;
 736                                                 clock-output-names = "pclk_peri";
 737                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
 738                                                 rockchip,div-relations =
 739                                                                 <0x0 1
 740                                                                  0x1 2
 741                                                                  0x2 4
 742                                                                  0x3 8>;
 743                                                 #clock-cells = <0>;
 744                                                 #clock-init-cells = <1>;
 745                                         };
 746
 747                                         /* reg[14]: reserved */
 748
 749                                         aclk_peri: aclk_peri_mux {
 750                                                 compatible = "rockchip,rk3188-mux-con";
 751                                                 rockchip,bits = <15 1>;
 752                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 753                                                 clock-output-names = "aclk_peri";
 754                                                 #clock-cells = <0>;
 755                                                 #clock-init-cells = <1>;
 756                                         };
 757                                 };
 758
 759                                 clk_sel_con11: sel-con@008c {
 760                                         compatible = "rockchip,rk3188-selcon";
 761                                         reg = <0x008c 0x4>;
 762                                         #address-cells = <1>;
 763                                         #size-cells = <1>;
 764
 765                                         clk_sdmmc_div: clk_sdmmc_div {
 766                                                 compatible = "rockchip,rk3188-div-con";
 767                                                 rockchip,bits = <0 6>;
 768                                                 clocks = <&clk_sdmmc>;
 769                                                 clock-output-names = "clk_sdmmc";
 770                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 771                                                 #clock-cells = <0>;
 772                                                 rockchip,clkops-idx =
 773                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 774                                         };
 775
 776                                         clk_sdmmc: clk_sdmmc_mux {
 777                                                 compatible = "rockchip,rk3188-mux-con";
 778                                                 rockchip,bits = <6 2>;
 779                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
 780                                                 clock-output-names = "clk_sdmmc";
 781                                                 #clock-cells = <0>;
 782                                         };
 783
 784                                         hsicphy_12m_div: hsicphy_12m_div {
 785                                                 compatible = "rockchip,rk3188-div-con";
 786                                                 rockchip,bits = <8 6>;
 787                                                 clocks = <&hsicphy_480m>;
 788                                                 clock-output-names = "hsicphy_12m_div";
 789                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 790                                                 #clock-cells = <0>;
 791                                         };
 792
 793                                 };
 794
 795                                 clk_sel_con12: sel-con@0090 {
 796                                         compatible = "rockchip,rk3188-selcon";
 797                                         reg = <0x0090 0x4>;
 798                                         #address-cells = <1>;
 799                                         #size-cells = <1>;
 800
 801                                         clk_sdio0_div: clk_sdio0_div {
 802                                                 compatible = "rockchip,rk3188-div-con";
 803                                                 rockchip,bits = <0 6>;
 804                                                 clocks = <&clk_sdio0>;
 805                                                 clock-output-names = "clk_sdio0";
 806                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 807                                                 #clock-cells = <0>;
 808                                                 rockchip,clkops-idx =
 809                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 810                                         };
 811
 812                                         clk_sdio0: clk_sdio0_mux {
 813                                                 compatible = "rockchip,rk3188-mux-con";
 814                                                 rockchip,bits = <6 2>;
 815                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
 816                                                 clock-output-names = "clk_sdio0";
 817                                                 #clock-cells = <0>;
 818                                         };
 819
 820                                         clk_emmc_div: clk_emmc_div {
 821                                                 compatible = "rockchip,rk3188-div-con";
 822                                                 rockchip,bits = <8 6>;
 823                                                 clocks = <&clk_emmc>;
 824                                                 clock-output-names = "clk_emmc";
 825                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 826                                                 #clock-cells = <0>;
 827                                                 rockchip,clkops-idx =
 828                                                         <CLKOPS_RATE_MUX_EVENDIV>;
 829                                         };
 830
 831                                         clk_emmc: clk_emmc_mux {
 832                                                 compatible = "rockchip,rk3188-mux-con";
 833                                                 rockchip,bits = <14 2>;
 834                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
 835                                                 clock-output-names = "clk_emmc";
 836                                                 #clock-cells = <0>;
 837                                         };
 838                                 };
 839
 840                                 clk_sel_con13: sel-con@0094 {
 841                                         compatible = "rockchip,rk3188-selcon";
 842                                         reg = <0x0094 0x4>;
 843                                         #address-cells = <1>;
 844                                         #size-cells = <1>;
 845
 846                                         clk_uart0_pll_div: clk_uart0_pll_div {
 847                                                 compatible = "rockchip,rk3188-div-con";
 848                                                 rockchip,bits = <0 7>;
 849                                                 clocks = <&clk_uart0_pll>;
 850                                                 clock-output-names = "clk_uart0_pll";
 851                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 852                                                 #clock-cells = <0>;
 853                                                 rockchip,clkops-idx =
 854                                                         <CLKOPS_RATE_MUX_DIV>;
 855                                         };
 856
 857                                         /* reg[7]: reserved */
 858
 859                                         clk_uart0: uart0_mux {
 860                                                 compatible = "rockchip,rk3188-mux-con";
 861                                                 rockchip,bits = <8 2>;
 862                                                 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&dummy>;
 863                                                 clock-output-names = "clk_uart0";
 864                                                 #clock-cells = <0>;
 865                                                 rockchip,clkops-idx =
 866                                                         <CLKOPS_RATE_RK3288_I2S>;
 867                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 868                                         };
 869
 870                                         /* reg[10]: reserved */
 871
 872                                         usbphy_480m: usbphy_480m_mux {
 873                                                 compatible = "rockchip,rk3188-mux-con";
 874                                                 rockchip,bits = <11 2>;
 875                                                 clocks = <&otgphy0_480m>, <&otgphy1_480m>, <&otgphy2_480m>;
 876                                                 clock-output-names = "usbphy_480m";
 877                                                 #clock-cells = <0>;
 878                                         };
 879
 880                                         clk_uart0_pll: clk_uart0_pll_mux {
 881                                                 compatible = "rockchip,rk3188-mux-con";
 882                                                 rockchip,bits = <13 2>;
 883                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>, <&clk_npll>;
 884                                                 clock-output-names = "clk_uart0_pll";
 885                                                 #clock-cells = <0>;
 886                                         };
 887
 888                                         uart_pll_mux: uart_pll_mux {
 889                                                 compatible = "rockchip,rk3188-mux-con";
 890                                                 rockchip,bits = <15 1>;
 891                                                 clocks = <&clk_cpll>, <&clk_gpll>;
 892                                                 clock-output-names = "uart_pll_mux";
 893                                                 #clock-cells = <0>;
 894                                                 #clock-init-cells = <1>;
 895                                         };
 896                                 };
 897
 898                                 clk_sel_con14: sel-con@0098 {
 899                                         compatible = "rockchip,rk3188-selcon";
 900                                         reg = <0x0098 0x4>;
 901                                         #address-cells = <1>;
 902                                         #size-cells = <1>;
 903
 904                                         clk_uart1_div: clk_uart1_div {
 905                                                 compatible = "rockchip,rk3188-div-con";
 906                                                 rockchip,bits = <0 7>;
 907                                                 clocks = <&uart_pll_mux>;
 908                                                 clock-output-names = "clk_uart1_div";
 909                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 910                                                 #clock-cells = <0>;
 911                                         };
 912
 913                                         /* reg[7]: reserved */
 914
 915                                         clk_uart1: uart1_mux {
 916                                                 compatible = "rockchip,rk3188-mux-con";
 917                                                 rockchip,bits = <8 2>;
 918                                                 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>, <&dummy>;
 919                                                 clock-output-names = "clk_uart1";
 920                                                 #clock-cells = <0>;
 921                                                 rockchip,clkops-idx =
 922                                                         <CLKOPS_RATE_RK3288_I2S>;
 923                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 924                                         };
 925
 926                                         /* reg[15:10]: reserved */
 927                                 };
 928
 929                                 clk_sel_con15: sel-con@009c {
 930                                         compatible = "rockchip,rk3188-selcon";
 931                                         reg = <0x009c 0x4>;
 932                                         #address-cells = <1>;
 933                                         #size-cells = <1>;
 934
 935                                         clk_uart2_div: clk_uart2_div {
 936                                                 compatible = "rockchip,rk3188-div-con";
 937                                                 rockchip,bits = <0 7>;
 938                                                 clocks = <&uart_pll_mux>;
 939                                                 clock-output-names = "clk_uart2_div";
 940                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 941                                                 #clock-cells = <0>;
 942                                         };
 943
 944                                         /* reg[7]: reserved */
 945
 946                                         clk_uart2: uart2_mux {
 947                                                 compatible = "rockchip,rk3188-mux-con";
 948                                                 rockchip,bits = <8 2>;
 949                                                 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>, <&dummy>;
 950                                                 clock-output-names = "clk_uart2";
 951                                                 #clock-cells = <0>;
 952                                                 rockchip,clkops-idx =
 953                                                         <CLKOPS_RATE_RK3288_I2S>;
 954                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 955                                         };
 956
 957                                         /* reg[15:10]: reserved */
 958                                 };
 959
 960                                 clk_sel_con16: sel-con@00a0 {
 961                                         compatible = "rockchip,rk3188-selcon";
 962                                         reg = <0x00a0 0x4>;
 963                                         #address-cells = <1>;
 964                                         #size-cells = <1>;
 965
 966                                         clk_uart3_div: clk_uart3_div {
 967                                                 compatible = "rockchip,rk3188-div-con";
 968                                                 rockchip,bits = <0 7>;
 969                                                 clocks = <&uart_pll_mux>;
 970                                                 clock-output-names = "clk_uart3_div";
 971                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
 972                                                 #clock-cells = <0>;
 973                                         };
 974
 975                                         /* reg[7]: reserved */
 976
 977                                         clk_uart3: uart3_mux {
 978                                                 compatible = "rockchip,rk3188-mux-con";
 979                                                 rockchip,bits = <8 2>;
 980                                                 clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>, <&dummy>;
 981                                                 clock-output-names = "clk_uart3";
 982                                                 #clock-cells = <0>;
 983                                                 rockchip,clkops-idx =
 984                                                         <CLKOPS_RATE_RK3288_I2S>;
 985                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
 986                                         };
 987
 988                                         /* reg[15:10]: reserved */
 989                                 };
 990
 991                                 clk_sel_con17: sel-con@00a4 {
 992                                         compatible = "rockchip,rk3188-selcon";
 993                                         reg = <0x00a4 0x4>;
 994                                         #address-cells = <1>;
 995                                         #size-cells = <1>;
 996
 997                                         uart0_frac: uart0_frac {
 998                                                 compatible = "rockchip,rk3188-frac-con";
 999                                                 clocks = <&clk_uart0_pll>;
1000                                                 clock-output-names = "uart0_frac";
1001                                                 /* numerator    denominator */
1002                                                 rockchip,bits = <0 32>;
1003                                                 rockchip,clkops-idx =
1004                                                         <CLKOPS_RATE_FRAC>;
1005                                                 #clock-cells = <0>;
1006                                         };
1007                                 };
1008
1009                                 clk_sel_con18: sel-con@00a8 {
1010                                         compatible = "rockchip,rk3188-selcon";
1011                                         reg = <0x00a8 0x4>;
1012                                         #address-cells = <1>;
1013                                         #size-cells = <1>;
1014
1015                                         uart1_frac: uart1_frac {
1016                                                 compatible = "rockchip,rk3188-frac-con";
1017                                                 clocks = <&clk_uart1_div>;
1018                                                 clock-output-names = "uart1_frac";
1019                                                 /* numerator    denominator */
1020                                                 rockchip,bits = <0 32>;
1021                                                 rockchip,clkops-idx =
1022                                                         <CLKOPS_RATE_FRAC>;
1023                                                 #clock-cells = <0>;
1024                                         };
1025                                 };
1026
1027                                 clk_sel_con19: sel-con@00ac {
1028                                         compatible = "rockchip,rk3188-selcon";
1029                                         reg = <0x00ac 0x4>;
1030                                         #address-cells = <1>;
1031                                         #size-cells = <1>;
1032
1033                                         uart2_frac: uart2_frac {
1034                                                 compatible = "rockchip,rk3188-frac-con";
1035                                                 clocks = <&clk_uart2_div>;
1036                                                 clock-output-names = "uart2_frac";
1037                                                 /* numerator    denominator */
1038                                                 rockchip,bits = <0 32>;
1039                                                 rockchip,clkops-idx =
1040                                                         <CLKOPS_RATE_FRAC>;
1041                                                 #clock-cells = <0>;
1042                                         };
1043
1044                                 };
1045
1046                                 clk_sel_con20: sel-con@00b0 {
1047                                         compatible = "rockchip,rk3188-selcon";
1048                                         reg = <0x00b0 0x4>;
1049                                         #address-cells = <1>;
1050                                         #size-cells = <1>;
1051
1052                                         uart3_frac: uart3_frac {
1053                                                 compatible = "rockchip,rk3188-frac-con";
1054                                                 clocks = <&clk_uart3_div>;
1055                                                 clock-output-names = "uart3_frac";
1056                                                 /* numerator    denominator */
1057                                                 rockchip,bits = <0 32>;
1058                                                 rockchip,clkops-idx =
1059                                                         <CLKOPS_RATE_FRAC>;
1060                                                 #clock-cells = <0>;
1061                                         };
1062                                 };
1063
1064                                 clk_sel_con21: sel-con@00b4 {
1065                                         compatible = "rockchip,rk3188-selcon";
1066                                         reg = <0x00b4 0x4>;
1067                                         #address-cells = <1>;
1068                                         #size-cells = <1>;
1069
1070                                         clk_mac_pll: clk_mac_pll_mux {
1071                                                 compatible = "rockchip,rk3188-mux-con";
1072                                                 rockchip,bits = <0 2>;
1073                                                 clocks = <&clk_npll>, <&clk_cpll>, <&clk_gpll>;
1074                                                 clock-output-names = "clk_mac_pll";
1075                                                 #clock-cells = <0>;
1076                                         };
1077
1078                                         /* reg[3:2]: reserved */
1079
1080                                         clk_mac: clk_mac_mux {
1081                                                 compatible = "rockchip,rk3188-mux-con";
1082                                                 rockchip,bits = <4 1>;
1083                                                 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1084                                                 clock-output-names = "clk_mac";
1085                                                 #clock-cells = <0>;
1086                                                 rockchip,clkops-idx =
1087                                                         <CLKOPS_RATE_MAC_REF>;
1088                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1089                                                 #clock-init-cells = <1>;
1090                                         };
1091
1092                                         /* reg[7:5]: reserved */
1093
1094                                         clk_mac_pll_div: clk_mac_pll_div {
1095                                                 compatible = "rockchip,rk3188-div-con";
1096                                                 rockchip,bits = <8 5>;
1097                                                 clocks = <&clk_mac_pll>;
1098                                                 clock-output-names = "clk_mac_pll";
1099                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1100                                                 #clock-cells = <0>;
1101                                                 rockchip,clkops-idx =
1102                                                         <CLKOPS_RATE_MUX_DIV>;
1103                                         };
1104
1105                                         /* reg[15:13]: reserved */
1106                                 };
1107
1108                                 clk_sel_con22: sel-con@00b8 {
1109                                         compatible = "rockchip,rk3188-selcon";
1110                                         reg = <0x00b8 0x4>;
1111                                         #address-cells = <1>;
1112                                         #size-cells = <1>;
1113
1114                                         clk_hsadc_pll: clk_hsadc_pll_mux {
1115                                                 compatible = "rockchip,rk3188-mux-con";
1116                                                 rockchip,bits = <0 1>;
1117                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1118                                                 clock-output-names = "clk_hsadc_pll";
1119                                                 #clock-cells = <0>;
1120                                         };
1121 /*
1122                                         wifi_pll_mux: wifi_pll_mux {
1123                                                 compatible = "rockchip,rk3188-mux-con";
1124                                                 rockchip,bits = <1 1>;
1125                                                 clocks = <&>, <&>;
1126                                                 clock-output-names = "wifi_pll_mux";
1127                                                 #clock-cells = <0>;
1128                                         };
1129 */
1130
1131                                         /* reg[3:2]: reserved */
1132
1133                                         clk_hsadc_out: clk_hsadc_out {
1134                                                 compatible = "rockchip,rk3188-mux-con";
1135                                                 rockchip,bits = <4 1>;
1136                                                 clocks = <&clk_hsadc_pll>, <&clk_hsadc_ext>;
1137                                                 clock-output-names = "clk_hsadc_out";
1138                                                 #clock-cells = <0>;
1139                                                 rockchip,clkops-idx =
1140                                                         <CLKOPS_RATE_HSADC>;
1141                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1142                                         };
1143
1144                                         /* reg[6:5]: reserved */
1145
1146                                         clk_hsadc: clk_hsadc {
1147                                                 compatible = "rockchip,rk3188-mux-con";
1148                                                 rockchip,bits = <7 1>;
1149                                                 clocks = <&clk_hsadc_out>, <&clk_hsadc_inv>;
1150                                                 clock-output-names = "clk_hsadc";
1151                                                 #clock-cells = <0>;
1152                                         };
1153
1154                                         clk_hsadc_pll_div: clk_hsadc_pll_div {
1155                                                 compatible = "rockchip,rk3188-div-con";
1156                                                 rockchip,bits = <8 8>;
1157                                                 clocks = <&clk_hsadc_pll>;
1158                                                 clock-output-names = "clk_hsadc_pll";
1159                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1160                                                 #clock-cells = <0>;
1161                                                 rockchip,clkops-idx =
1162                                                         <CLKOPS_RATE_MUX_DIV>;
1163                                         };
1164                                 };
1165 /*
1166                                 clk_sel_con23: sel-con@00bc {
1167                                         compatible = "rockchip,rk3188-selcon";
1168                                         reg = <0x00bc 0x4>;
1169                                         #address-cells = <1>;
1170                                         #size-cells = <1>;
1171
1172                                         wifi_frac: wifi_frac {
1173                                                 compatible = "rockchip,rk3188-frac-con";
1174                                                 clocks = <&>;
1175                                                 clock-output-names = "wifi_frac";
1176                                                 / numerator     denominator /
1177                                                 rockchip,bits = <0 32>;
1178                                                 rockchip,clkops-idx =
1179                                                         <>;
1180                                                 #clock-cells = <0>;
1181                                         };
1182                                 };
1183 */
1184
1185                                 clk_sel_con24: sel-con@00c0 {
1186                                         compatible = "rockchip,rk3188-selcon";
1187                                         reg = <0x00c0 0x4>;
1188                                         #address-cells = <1>;
1189                                         #size-cells = <1>;
1190
1191                                         /* reg[7:0]: reserved */
1192
1193                                         clk_saradc: clk_saradc_div {
1194                                                 compatible = "rockchip,rk3188-div-con";
1195                                                 rockchip,bits = <8 8>;
1196                                                 clocks = <&xin24m>;
1197                                                 clock-output-names = "clk_saradc";
1198                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1199                                                 #clock-cells = <0>;
1200                                         };
1201                                 };
1202
1203                                 clk_sel_con25: sel-con@00c4 {
1204                                         compatible = "rockchip,rk3188-selcon";
1205                                         reg = <0x00c4 0x4>;
1206                                         #address-cells = <1>;
1207                                         #size-cells = <1>;
1208
1209                                         clk_spi0_div: clk_spi0_div {
1210                                                 compatible = "rockchip,rk3188-div-con";
1211                                                 rockchip,bits = <0 7>;
1212                                                 clocks = <&clk_spi0>;
1213                                                 clock-output-names = "clk_spi0";
1214                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1215                                                 #clock-cells = <0>;
1216                                                 rockchip,clkops-idx =
1217                                                         <CLKOPS_RATE_MUX_DIV>;
1218                                         };
1219
1220                                         clk_spi0: clk_spi0_mux {
1221                                                 compatible = "rockchip,rk3188-mux-con";
1222                                                 rockchip,bits = <7 1>;
1223                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1224                                                 clock-output-names = "clk_spi0";
1225                                                 #clock-cells = <0>;
1226                                         };
1227
1228                                         clk_spi1_div: clk_spi1_div {
1229                                                 compatible = "rockchip,rk3188-div-con";
1230                                                 rockchip,bits = <8 7>;
1231                                                 clocks = <&clk_spi1>;
1232                                                 clock-output-names = "clk_spi1";
1233                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1234                                                 #clock-cells = <0>;
1235                                                 rockchip,clkops-idx =
1236                                                         <CLKOPS_RATE_MUX_DIV>;
1237                                         };
1238
1239                                         clk_spi1: clk_spi1_mux {
1240                                                 compatible = "rockchip,rk3188-mux-con";
1241                                                 rockchip,bits = <15 1>;
1242                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1243                                                 clock-output-names = "clk_spi1";
1244                                                 #clock-cells = <0>;
1245                                         };
1246                                 };
1247
1248                                 clk_sel_con26: sel-con@00c8 {
1249                                         compatible = "rockchip,rk3188-selcon";
1250                                         reg = <0x00c8 0x4>;
1251                                         #address-cells = <1>;
1252                                         #size-cells = <1>;
1253
1254                                         ddr_div: ddr_div {
1255                                                 compatible = "rockchip,rk3188-div-con";
1256                                                 rockchip,bits = <0 2>;
1257                                                 clocks = <&clk_ddr>;
1258                                                 clock-output-names = "clk_ddr";
1259                                                 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1260                                                 rockchip,div-relations =
1261                                                                 <0x0 1
1262                                                                  0x1 2
1263                                                                  0x3 4>;
1264                                                 #clock-cells = <0>;
1265                                                 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1266                                                                         CLK_SET_RATE_NO_REPARENT)>;
1267                                                 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
1268                                         };
1269
1270                                         clk_ddr: ddr_clk_pll_mux {
1271                                                 compatible = "rockchip,rk3188-mux-con";
1272                                                 rockchip,bits = <2 1>;
1273                                                 clocks = <&clk_dpll>, <&clk_gpll>;
1274                                                 clock-output-names = "clk_ddr";
1275                                                 #clock-cells = <0>;
1276                                         };
1277
1278                                         /* reg[5:3]: reserved */
1279
1280                                         clk_crypto: crypto_div {
1281                                                 compatible = "rockchip,rk3188-div-con";
1282                                                 rockchip,bits = <6 2>;
1283                                                 clocks = <&aclk_bus>;
1284                                                 clock-output-names = "clk_crypto";
1285                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1286                                                 #clock-cells = <0>;
1287                                                 #clock-init-cells = <1>;
1288                                         };
1289
1290                                         clk_cif_pll: clk_cif_pll_mux {
1291                                                 compatible = "rockchip,rk3188-mux-con";
1292                                                 rockchip,bits = <8 1>;
1293                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1294                                                 clock-output-names = "clk_cif_pll";
1295                                                 #clock-cells = <0>;
1296                                         };
1297
1298                                         clk_cif_out_div: clk_cif_out_div {
1299                                                 compatible = "rockchip,rk3188-div-con";
1300                                                 rockchip,bits = <9 5>;
1301                                                 clocks = <&clk_cif_out>;
1302                                                 clock-output-names = "clk_cif_out";
1303                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1304                                                 #clock-cells = <0>;
1305                                                 rockchip,clkops-idx =
1306                                                         <CLKOPS_RATE_MUX_DIV>;
1307                                         };
1308
1309                                         /* reg[14]: reserved */
1310
1311                                         clk_cif_out: clk_cif_out_mux {
1312                                                 compatible = "rockchip,rk3188-mux-con";
1313                                                 rockchip,bits = <15 1>;
1314                                                 clocks = <&clk_cif_pll>, <&xin24m>;
1315                                                 clock-output-names = "clk_cif_out";
1316                                                 #clock-cells = <0>;
1317                                         };
1318                                 };
1319
1320                                 clk_sel_con27: sel-con@00cc {
1321                                         compatible = "rockchip,rk3188-selcon";
1322                                         reg = <0x00cc 0x4>;
1323                                         #address-cells = <1>;
1324                                         #size-cells = <1>;
1325
1326                                         dclk_lcdc0: dclk_lcdc0_mux {
1327                                                 compatible = "rockchip,rk3188-mux-con";
1328                                                 rockchip,bits = <0 2>;
1329                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1330                                                 clock-output-names = "dclk_lcdc0";
1331                                                 #clock-cells = <0>;
1332                                         };
1333
1334                                         /* reg[7:2]: reserved */
1335
1336                                         dclk_lcdc0_div: dclk_lcdc0_div {
1337                                                 compatible = "rockchip,rk3188-div-con";
1338                                                 rockchip,bits = <8 8>;
1339                                                 clocks = <&dclk_lcdc0>;
1340                                                 clock-output-names = "dclk_lcdc0";
1341                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1342                                                 #clock-cells = <0>;
1343                                                 rockchip,clkops-idx =
1344                                                         <CLKOPS_RATE_MUX_EVENDIV>;
1345                                         };
1346                                 };
1347
1348                                 clk_sel_con28: sel-con@00d0 {
1349                                         compatible = "rockchip,rk3188-selcon";
1350                                         reg = <0x00d0 0x4>;
1351                                         #address-cells = <1>;
1352                                         #size-cells = <1>;
1353
1354                                         clk_edp_div: clk_edp_div {
1355                                                 compatible = "rockchip,rk3188-div-con";
1356                                                 rockchip,bits = <0 6>;
1357                                                 clocks = <&clk_edp>;
1358                                                 clock-output-names = "clk_edp";
1359                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1360                                                 #clock-cells = <0>;
1361                                                 rockchip,clkops-idx =
1362                                                         <CLKOPS_RATE_MUX_DIV>;
1363                                         };
1364
1365                                         clk_edp: clk_edp_mux {
1366                                                 compatible = "rockchip,rk3188-mux-con";
1367                                                 rockchip,bits = <6 2>;
1368                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1369                                                 clock-output-names = "clk_edp";
1370                                                 #clock-cells = <0>;
1371                                                 #clock-init-cells = <1>;
1372                                         };
1373
1374                                         hclk_vio: hclk_vio_div {
1375                                                 compatible = "rockchip,rk3188-div-con";
1376                                                 rockchip,bits = <8 5>;
1377                                                 clocks = <&aclk_vio0>;
1378                                                 clock-output-names = "hclk_vio";
1379                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1380                                                 #clock-cells = <0>;
1381                                                 #clock-init-cells = <1>;
1382                                         };
1383
1384                                         /* reg[14:13]: reserved */
1385
1386                                         clk_edp_24m: edp_24m_mux {
1387                                                 compatible = "rockchip,rk3188-mux-con";
1388                                                 rockchip,bits = <15 1>;
1389                                                 clocks = <&edp_24m_clkin>, <&xin24m>;
1390                                                 clock-output-names = "clk_edp_24m";
1391                                                 #clock-cells = <0>;
1392                                         };
1393                                 };
1394
1395                                 clk_sel_con29: sel-con@00d4 {
1396                                         compatible = "rockchip,rk3188-selcon";
1397                                         reg = <0x00d4 0x4>;
1398                                         #address-cells = <1>;
1399                                         #size-cells = <1>;
1400
1401                                         hsicphy_480m: hsicphy_480m_mux {
1402                                                 compatible = "rockchip,rk3188-mux-con";
1403                                                 rockchip,bits = <0 2>;
1404                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1405                                                 clock-output-names = "hsicphy_480m";
1406                                                 #clock-cells = <0>;
1407                                         };
1408
1409                                         hsicphy_12m: hsicphy_12m_mux {
1410                                                 compatible = "rockchip,rk3188-mux-con";
1411                                                 rockchip,bits = <2 1>;
1412                                                 clocks = <&clk_gates13 9>, <&hsicphy_12m_div>;
1413                                                 clock-output-names = "hsicphy_12m";
1414                                                 #clock-cells = <0>;
1415                                         };
1416
1417                                         clkin_isp: clkin_isp {
1418                                                 compatible = "rockchip,rk3188-mux-con";
1419                                                 rockchip,bits = <3 1>;
1420                                                 clocks = <&clk_gates16 3>, <&pclkin_isp_inv>;
1421                                                 clock-output-names = "clkin_isp";
1422                                                 #clock-cells = <0>;
1423                                         };
1424
1425                                         clkin_cif: clkin_cif {
1426                                                 compatible = "rockchip,rk3188-mux-con";
1427                                                 rockchip,bits = <4 1>;
1428                                                 clocks = <&clk_gates16 0>, <&pclkin_cif_inv>;
1429                                                 clock-output-names = "clkin_cif";
1430                                                 #clock-cells = <0>;
1431                                         };
1432
1433                                         /* reg[5]: reserved */
1434
1435                                         dclk_lcdc1: dclk_lcdc1_mux {
1436                                                 compatible = "rockchip,rk3188-mux-con";
1437                                                 rockchip,bits = <6 2>;
1438                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1439                                                 clock-output-names = "dclk_lcdc1";
1440                                                 #clock-cells = <0>;
1441                                         };
1442
1443                                         dclk_lcdc1_div: dclk_lcdc1_div {
1444                                                 compatible = "rockchip,rk3188-div-con";
1445                                                 rockchip,bits = <8 8>;
1446                                                 clocks = <&dclk_lcdc1>;
1447                                                 clock-output-names = "dclk_lcdc1";
1448                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1449                                                 #clock-cells = <0>;
1450                                                 rockchip,clkops-idx =
1451                                                         <CLKOPS_RATE_MUX_DIV>;
1452                                         };
1453                                 };
1454
1455                                 clk_sel_con30: sel-con@00d8 {
1456                                         compatible = "rockchip,rk3188-selcon";
1457                                         reg = <0x00d8 0x4>;
1458                                         #address-cells = <1>;
1459                                         #size-cells = <1>;
1460
1461                                         aclk_rga_div: aclk_rga_div {
1462                                                 compatible = "rockchip,rk3188-div-con";
1463                                                 rockchip,bits = <0 5>;
1464                                                 clocks = <&aclk_rga>;
1465                                                 clock-output-names = "aclk_rga";
1466                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1467                                                 #clock-cells = <0>;
1468                                                 rockchip,clkops-idx =
1469                                                         <CLKOPS_RATE_MUX_DIV>;
1470                                         };
1471
1472                                         /* reg[5]: reserved */
1473
1474                                         aclk_rga: aclk_rga_mux {
1475                                                 compatible = "rockchip,rk3188-mux-con";
1476                                                 rockchip,bits = <6 2>;
1477                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
1478                                                 clock-output-names = "aclk_rga";
1479                                                 #clock-cells = <0>;
1480                                                 #clock-init-cells = <1>;
1481                                         };
1482
1483                                         clk_rga_div: clk_rga_div {
1484                                                 compatible = "rockchip,rk3188-div-con";
1485                                                 rockchip,bits = <8 5>;
1486                                                 clocks = <&clk_rga>;
1487                                                 clock-output-names = "clk_rga";
1488                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1489                                                 #clock-cells = <0>;
1490                                                 rockchip,clkops-idx =
1491                                                         <CLKOPS_RATE_MUX_DIV>;
1492                                         };
1493
1494                                         /* reg[13]: reserved */
1495
1496                                         clk_rga: clk_rga_mux {
1497                                                 compatible = "rockchip,rk3188-mux-con";
1498                                                 rockchip,bits = <14 2>;
1499                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
1500                                                 clock-output-names = "clk_rga";
1501                                                 #clock-cells = <0>;
1502                                                 #clock-init-cells = <1>;
1503                                         };
1504                                 };
1505
1506                                 clk_sel_con31: sel-con@00dc {
1507                                         compatible = "rockchip,rk3188-selcon";
1508                                         reg = <0x00dc 0x4>;
1509                                         #address-cells = <1>;
1510                                         #size-cells = <1>;
1511
1512                                         aclk_vio0_div: aclk_vio0_div {
1513                                                 compatible = "rockchip,rk3188-div-con";
1514                                                 rockchip,bits = <0 5>;
1515                                                 clocks = <&aclk_vio0>;
1516                                                 clock-output-names = "aclk_vio0";
1517                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1518                                                 #clock-cells = <0>;
1519                                                 rockchip,clkops-idx =
1520                                                         <CLKOPS_RATE_MUX_DIV>;
1521                                         };
1522
1523                                         /* reg[5]: reserved */
1524
1525                                         aclk_vio0: aclk_vio0_mux {
1526                                                 compatible = "rockchip,rk3188-mux-con";
1527                                                 rockchip,bits = <6 2>;
1528                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
1529                                                 clock-output-names = "aclk_vio0";
1530                                                 #clock-cells = <0>;
1531                                                 #clock-init-cells = <1>;
1532                                         };
1533
1534                                         aclk_vio1_div: aclk_vio1_div {
1535                                                 compatible = "rockchip,rk3188-div-con";
1536                                                 rockchip,bits = <8 5>;
1537                                                 clocks = <&aclk_vio1>;
1538                                                 clock-output-names = "aclk_vio1";
1539                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1540                                                 #clock-cells = <0>;
1541                                                 rockchip,clkops-idx =
1542                                                         <CLKOPS_RATE_MUX_DIV>;
1543                                         };
1544
1545                                         /* reg[13]: reserved */
1546
1547                                         aclk_vio1: aclk_vio1_mux {
1548                                                 compatible = "rockchip,rk3188-mux-con";
1549                                                 rockchip,bits = <14 2>;
1550                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
1551                                                 clock-output-names = "aclk_vio1";
1552                                                 #clock-cells = <0>;
1553                                                 #clock-init-cells = <1>;
1554                                         };
1555                                 };
1556
1557                                 clk_sel_con32: sel-con@00e0 {
1558                                         compatible = "rockchip,rk3188-selcon";
1559                                         reg = <0x00e0 0x4>;
1560                                         #address-cells = <1>;
1561                                         #size-cells = <1>;
1562
1563                                         clk_vepu_div: clk_vepu_div {
1564                                                 compatible = "rockchip,rk3188-div-con";
1565                                                 rockchip,bits = <0 5>;
1566                                                 clocks = <&clk_vepu>;
1567                                                 clock-output-names = "clk_vepu";
1568                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1569                                                 #clock-cells = <0>;
1570                                                 rockchip,clkops-idx =
1571                                                         <CLKOPS_RATE_MUX_DIV>;
1572                                         };
1573
1574                                         /* reg[5]: reserved */
1575
1576                                         clk_vepu: clk_vepu_mux {
1577                                                 compatible = "rockchip,rk3188-mux-con";
1578                                                 rockchip,bits = <6 2>;
1579                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
1580                                                 clock-output-names = "clk_vepu";
1581                                                 #clock-cells = <0>;
1582                                                 #clock-init-cells = <1>;
1583                                         };
1584
1585                                         clk_vdpu_div: clk_vdpu_div {
1586                                                 compatible = "rockchip,rk3188-div-con";
1587                                                 rockchip,bits = <8 5>;
1588                                                 clocks = <&clk_vdpu>;
1589                                                 clock-output-names = "clk_vdpu";
1590                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1591                                                 #clock-cells = <0>;
1592                                                 rockchip,clkops-idx =
1593                                                         <CLKOPS_RATE_MUX_DIV>;
1594                                         };
1595
1596                                         /* reg[13]: reserved */
1597
1598                                         clk_vdpu: clk_vdpu_mux {
1599                                                 compatible = "rockchip,rk3188-mux-con";
1600                                                 rockchip,bits = <14 2>;
1601                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>;
1602                                                 clock-output-names = "clk_vdpu";
1603                                                 #clock-cells = <0>;
1604                                                 #clock-init-cells = <1>;
1605                                         };
1606                                 };
1607
1608                                 clk_sel_con33: sel-con@00e4 {
1609                                         compatible = "rockchip,rk3188-selcon";
1610                                         reg = <0x00e4 0x4>;
1611                                         #address-cells = <1>;
1612                                         #size-cells = <1>;
1613
1614                                         pclk_pd_pmu: pclk_pd_pmu_div {
1615                                                 compatible = "rockchip,rk3188-div-con";
1616                                                 rockchip,bits = <0 5>;
1617                                                 clocks = <&clk_gpll>;
1618                                                 clock-output-names = "pclk_pd_pmu";
1619                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1620                                                 #clock-cells = <0>;
1621                                                 #clock-init-cells = <1>;
1622                                         };
1623
1624                                         /* reg[7:5]: reserved */
1625
1626                                         pclk_pd_alive: pclk_pd_alive {
1627                                                 compatible = "rockchip,rk3188-div-con";
1628                                                 rockchip,bits = <8 5>;
1629                                                 clocks = <&clk_gpll>;
1630                                                 clock-output-names = "pclk_pd_alive";
1631                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1632                                                 #clock-cells = <0>;
1633                                                 #clock-init-cells = <1>;
1634                                         };
1635
1636                                         /* reg[15:13]: reserved */
1637                                 };
1638
1639                                 clk_sel_con34: sel-con@00e8 {
1640                                         compatible = "rockchip,rk3188-selcon";
1641                                         reg = <0x00e8 0x4>;
1642                                         #address-cells = <1>;
1643                                         #size-cells = <1>;
1644
1645                                         clk_gpu_div: clk_gpu_div {
1646                                                 compatible = "rockchip,rk3188-div-con";
1647                                                 rockchip,bits = <0 5>;
1648                                                 clocks = <&clk_gpu>;
1649                                                 clock-output-names = "clk_gpu";
1650                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1651                                                 #clock-cells = <0>;
1652                                                 rockchip,clkops-idx =
1653                                                         <CLKOPS_RATE_MUX_DIV>;
1654                                         };
1655
1656                                         /* reg[5]: reserved */
1657
1658                                         clk_gpu: clk_gpu_mux {
1659                                                 compatible = "rockchip,rk3188-mux-con";
1660                                                 rockchip,bits = <6 2>;
1661                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&dummy_480m>, <&clk_npll>;
1662                                                 clock-output-names = "clk_gpu";
1663                                                 #clock-cells = <0>;
1664                                                 #clock-init-cells = <1>;
1665                                         };
1666
1667                                         clk_sdio1_div: clk_sdio1_div {
1668                                                 compatible = "rockchip,rk3188-div-con";
1669                                                 rockchip,bits = <8 6>;
1670                                                 clocks = <&clk_sdio1>;
1671                                                 clock-output-names = "clk_sdio1";
1672                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1673                                                 #clock-cells = <0>;
1674                                                 rockchip,clkops-idx =
1675                                                         <CLKOPS_RATE_MUX_EVENDIV>;
1676                                         };
1677
1678                                         clk_sdio1: clk_sdio1_mux {
1679                                                 compatible = "rockchip,rk3188-mux-con";
1680                                                 rockchip,bits = <14 2>;
1681                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&xin24m>;
1682                                                 clock-output-names = "clk_sdio1";
1683                                                 #clock-cells = <0>;
1684                                         };
1685                                 };
1686
1687                                 clk_sel_con35: sel-con@00ec {
1688                                         compatible = "rockchip,rk3188-selcon";
1689                                         reg = <0x00ec 0x4>;
1690                                         #address-cells = <1>;
1691                                         #size-cells = <1>;
1692
1693                                         clk_tsp_div: clk_tsp_div {
1694                                                 compatible = "rockchip,rk3188-div-con";
1695                                                 rockchip,bits = <0 5>;
1696                                                 clocks = <&clk_tsp>;
1697                                                 clock-output-names = "clk_tsp";
1698                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1699                                                 #clock-cells = <0>;
1700                                                 rockchip,clkops-idx =
1701                                                         <CLKOPS_RATE_MUX_DIV>;
1702                                         };
1703
1704                                         /* reg[5]: reserved */
1705
1706                                         clk_tsp: clk_tsp_mux {
1707                                                 compatible = "rockchip,rk3188-mux-con";
1708                                                 rockchip,bits = <6 2>;
1709                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1710                                                 clock-output-names = "clk_tsp";
1711                                                 #clock-cells = <0>;
1712                                                 #clock-init-cells = <1>;
1713                                         };
1714
1715                                         clk_tspout_div: clk_tspout_div {
1716                                                 compatible = "rockchip,rk3188-div-con";
1717                                                 rockchip,bits = <8 5>;
1718                                                 clocks = <&clk_tspout>;
1719                                                 clock-output-names = "clk_tspout";
1720                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1721                                                 #clock-cells = <0>;
1722                                                 rockchip,clkops-idx =
1723                                                         <CLKOPS_RATE_MUX_DIV>;
1724                                         };
1725
1726                                         /* reg[13]: reserved */
1727
1728                                         clk_tspout: clk_tspout_mux {
1729                                                 compatible = "rockchip,rk3188-mux-con";
1730                                                 rockchip,bits = <14 2>;
1731                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
1732                                                 clock-output-names = "clk_tspout";
1733                                                 #clock-cells = <0>;
1734                                                 #clock-init-cells = <1>;
1735                                         };
1736                                 };
1737
1738                                 clk_sel_con36: sel-con@00f0 {
1739                                         compatible = "rockchip,rk3188-selcon";
1740                                         reg = <0x00f0 0x4>;
1741                                         #address-cells = <1>;
1742                                         #size-cells = <1>;
1743
1744                                         clk_core0: clk_core0_div {
1745                                                 compatible = "rockchip,rk3188-div-con";
1746                                                 rockchip,bits = <0 3>;
1747                                                 clocks = <&clk_core>;
1748                                                 clock-output-names = "clk_core0";
1749                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1750                                                 #clock-cells = <0>;
1751                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1752                                         };
1753
1754                                         /* reg[3]: reserved */
1755
1756                                         clk_core1: clk_core1_div {
1757                                                 compatible = "rockchip,rk3188-div-con";
1758                                                 rockchip,bits = <4 3>;
1759                                                 clocks = <&clk_core>;
1760                                                 clock-output-names = "clk_core1";
1761                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1762                                                 #clock-cells = <0>;
1763                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1764                                         };
1765
1766                                         /* reg[7]: reserved */
1767
1768                                         clk_core2: clk_core2_div {
1769                                                 compatible = "rockchip,rk3188-div-con";
1770                                                 rockchip,bits = <8 3>;
1771                                                 clocks = <&clk_core>;
1772                                                 clock-output-names = "clk_core2";
1773                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1774                                                 #clock-cells = <0>;
1775                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1776                                         };
1777
1778                                         /* reg[11]: reserved */
1779
1780                                         clk_core3: clk_core3_div {
1781                                                 compatible = "rockchip,rk3188-div-con";
1782                                                 rockchip,bits = <12 3>;
1783                                                 clocks = <&clk_core>;
1784                                                 clock-output-names = "clk_core3";
1785                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1786                                                 #clock-cells = <0>;
1787                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1788                                         };
1789
1790                                         /* reg[15]: reserved */
1791                                 };
1792
1793                                 clk_sel_con37: sel-con@00f4 {
1794                                         compatible = "rockchip,rk3188-selcon";
1795                                         reg = <0x00f4 0x4>;
1796                                         #address-cells = <1>;
1797                                         #size-cells = <1>;
1798
1799                                         clk_l2ram: clk_l2ram_div {
1800                                                 compatible = "rockchip,rk3188-div-con";
1801                                                 rockchip,bits = <0 3>;
1802                                                 clocks = <&clk_core>;
1803                                                 clock-output-names = "clk_l2ram";
1804                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1805                                                 #clock-cells = <0>;
1806                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1807                                         };
1808
1809                                         /* reg[3]: reserved */
1810
1811                                         atclk_core: atclk_core_div {
1812                                                 compatible = "rockchip,rk3188-div-con";
1813                                                 rockchip,bits = <4 5>;
1814                                                 clocks = <&clk_core>;
1815                                                 clock-output-names = "atclk_core";
1816                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1817                                                 #clock-cells = <0>;
1818                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1819                                         };
1820
1821                                         pclk_dbg_src: pclk_core_dbg_div {
1822                                                 compatible = "rockchip,rk3188-div-con";
1823                                                 rockchip,bits = <9 5>;
1824                                                 clocks = <&clk_core>;
1825                                                 clock-output-names = "pclk_dbg_src";
1826                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1827                                                 #clock-cells = <0>;
1828                                                 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1829                                         };
1830
1831                                         /* reg[15:14]: reserved */
1832                                 };
1833
1834                                 clk_sel_con38: sel-con@00f8 {
1835                                         compatible = "rockchip,rk3188-selcon";
1836                                         reg = <0x00f8 0x4>;
1837                                         #address-cells = <1>;
1838                                         #size-cells = <1>;
1839
1840                                         clk_nandc0_div: clk_nandc0_div {
1841                                                 compatible = "rockchip,rk3188-div-con";
1842                                                 rockchip,bits = <0 5>;
1843                                                 clocks = <&clk_nandc0>;
1844                                                 clock-output-names = "clk_nandc0";
1845                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1846                                                 #clock-cells = <0>;
1847                                                 rockchip,clkops-idx =
1848                                                         <CLKOPS_RATE_MUX_DIV>;
1849                                         };
1850
1851                                         /* reg[6:5]: reserved */
1852
1853                                         clk_nandc0: clk_nandc0_mux {
1854                                                 compatible = "rockchip,rk3188-mux-con";
1855                                                 rockchip,bits = <7 1>;
1856                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1857                                                 clock-output-names = "clk_nandc0";
1858                                                 #clock-cells = <0>;
1859                                         };
1860
1861                                         clk_nandc1_div: clk_nandc1_div {
1862                                                 compatible = "rockchip,rk3188-div-con";
1863                                                 rockchip,bits = <8 5>;
1864                                                 clocks = <&clk_nandc1>;
1865                                                 clock-output-names = "clk_nandc1";
1866                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1867                                                 #clock-cells = <0>;
1868                                                 rockchip,clkops-idx =
1869                                                         <CLKOPS_RATE_MUX_DIV>;
1870                                         };
1871
1872                                         /* reg[14:13]: reserved */
1873
1874                                         clk_nandc1: clk_nandc1_mux {
1875                                                 compatible = "rockchip,rk3188-mux-con";
1876                                                 rockchip,bits = <15 1>;
1877                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1878                                                 clock-output-names = "clk_nandc1";
1879                                                 #clock-cells = <0>;
1880                                         };
1881                                 };
1882
1883                                 clk_sel_con39: sel-con@00fc {
1884                                         compatible = "rockchip,rk3188-selcon";
1885                                         reg = <0x00fc 0x4>;
1886                                         #address-cells = <1>;
1887                                         #size-cells = <1>;
1888
1889                                         clk_spi2_div: clk_spi2_div {
1890                                                 compatible = "rockchip,rk3188-div-con";
1891                                                 rockchip,bits = <0 7>;
1892                                                 clocks = <&clk_spi2>;
1893                                                 clock-output-names = "clk_spi2";
1894                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1895                                                 #clock-cells = <0>;
1896                                                 rockchip,clkops-idx =
1897                                                         <CLKOPS_RATE_MUX_DIV>;
1898                                         };
1899
1900                                         clk_spi2: clk_spi2_mux {
1901                                                 compatible = "rockchip,rk3188-mux-con";
1902                                                 rockchip,bits = <7 1>;
1903                                                 clocks = <&clk_cpll>, <&clk_gpll>;
1904                                                 clock-output-names = "clk_spi2";
1905                                                 #clock-cells = <0>;
1906                                         };
1907
1908                                         aclk_hevc_div: aclk_hevc_div {
1909                                                 compatible = "rockchip,rk3188-div-con";
1910                                                 rockchip,bits = <8 5>;
1911                                                 clocks = <&aclk_hevc>;
1912                                                 clock-output-names = "aclk_hevc";
1913                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1914                                                 #clock-cells = <0>;
1915                                                 rockchip,clkops-idx =
1916                                                         <CLKOPS_RATE_MUX_DIV>;
1917                                         };
1918
1919                                         /* reg[13]: reserved */
1920
1921                                         aclk_hevc: aclk_hevc_mux {
1922                                                 compatible = "rockchip,rk3188-mux-con";
1923                                                 rockchip,bits = <14 2>;
1924                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1925                                                 clock-output-names = "aclk_hevc";
1926                                                 #clock-cells = <0>;
1927                                                 #clock-init-cells = <1>;
1928                                         };
1929                                 };
1930
1931                                 clk_sel_con40: sel-con@0100 {
1932                                         compatible = "rockchip,rk3188-selcon";
1933                                         reg = <0x0100 0x4>;
1934                                         #address-cells = <1>;
1935                                         #size-cells = <1>;
1936
1937                                         spdif_8ch_div: spdif_8ch_div {
1938                                                 compatible = "rockchip,rk3188-div-con";
1939                                                 rockchip,bits = <0 7>;
1940                                                 clocks = <&clk_spdif_pll>;
1941                                                 clock-output-names = "spdif_8ch_div";
1942                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1943                                                 #clock-cells = <0>;
1944                                         };
1945
1946                                         /* reg[7]: reserved */
1947
1948                                         clk_spdif_8ch: spdif_8ch_clk_mux {
1949                                                 compatible = "rockchip,rk3188-mux-con";
1950                                                 rockchip,bits = <8 2>;
1951                                                 clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>;
1952                                                 clock-output-names = "clk_spdif_8ch";
1953                                                 #clock-cells = <0>;
1954                                                 rockchip,clkops-idx =
1955                                                         <CLKOPS_RATE_RK3288_I2S>;
1956                                                 rockchip,flags = <CLK_SET_RATE_PARENT>;
1957                                         };
1958
1959                                         /* reg[11:10]: reserved */
1960
1961                                         hclk_hevc: hclk_hevc_div {
1962                                                 compatible = "rockchip,rk3188-div-con";
1963                                                 rockchip,bits = <12 2>;
1964                                                 clocks = <&aclk_hevc>;
1965                                                 clock-output-names = "hclk_hevc";
1966                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1967                                                 #clock-cells = <0>;
1968                                                 #clock-init-cells = <1>;
1969                                         };
1970
1971                                         /* reg[15:14]: reserved */
1972                                 };
1973
1974                                 clk_sel_con41: sel-con@0104 {
1975                                         compatible = "rockchip,rk3188-selcon";
1976                                         reg = <0x0104 0x4>;
1977                                         #address-cells = <1>;
1978                                         #size-cells = <1>;
1979
1980                                         spdif_8ch_frac: spdif_8ch_frac {
1981                                                 compatible = "rockchip,rk3188-frac-con";
1982                                                 clocks = <&spdif_8ch_div>;
1983                                                 clock-output-names = "spdif_8ch_frac";
1984                                                 /* numerator    denominator */
1985                                                 rockchip,bits = <0 32>;
1986                                                 rockchip,clkops-idx =
1987                                                         <CLKOPS_RATE_FRAC>;
1988                                                 #clock-cells = <0>;
1989                                         };
1990                                 };
1991
1992                                 clk_sel_con42: sel-con@0108 {
1993                                         compatible = "rockchip,rk3188-selcon";
1994                                         reg = <0x0108 0x4>;
1995                                         #address-cells = <1>;
1996                                         #size-cells = <1>;
1997
1998                                         clk_hevc_cabac_div: clk_hevc_cabac_div {
1999                                                 compatible = "rockchip,rk3188-div-con";
2000                                                 rockchip,bits = <0 5>;
2001                                                 clocks = <&clk_hevc_cabac>;
2002                                                 clock-output-names = "clk_hevc_cabac";
2003                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2004                                                 #clock-cells = <0>;
2005                                                 rockchip,clkops-idx =
2006                                                         <CLKOPS_RATE_MUX_DIV>;
2007                                         };
2008
2009                                         /* reg[5]: reserved */
2010
2011                                         clk_hevc_cabac: clk_hevc_cabac_mux {
2012                                                 compatible = "rockchip,rk3188-mux-con";
2013                                                 rockchip,bits = <6 2>;
2014                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
2015                                                 clock-output-names = "clk_hevc_cabac";
2016                                                 #clock-cells = <0>;
2017                                                 #clock-init-cells = <1>;
2018                                         };
2019
2020                                         clk_hevc_core_div: clk_hevc_core_div {
2021                                                 compatible = "rockchip,rk3188-div-con";
2022                                                 rockchip,bits = <8 5>;
2023                                                 clocks = <&clk_hevc_core>;
2024                                                 clock-output-names = "clk_hevc_core";
2025                                                 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2026                                                 #clock-cells = <0>;
2027                                                 rockchip,clkops-idx =
2028                                                         <CLKOPS_RATE_MUX_DIV>;
2029                                         };
2030
2031                                         /* reg[13]: reserved */
2032
2033                                         clk_hevc_core: clk_hevc_core_mux {
2034                                                 compatible = "rockchip,rk3188-mux-con";
2035                                                 rockchip,bits = <14 2>;
2036                                                 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
2037                                                 clock-output-names = "clk_hevc_core";
2038                                                 #clock-cells = <0>;
2039                                                 #clock-init-cells = <1>;
2040                                         };
2041                                 };
2042
2043                         };
2044
2045
2046                         /* Gate control regs */
2047                         clk_gate_cons {
2048                                 compatible = "rockchip,rk-gate-cons";
2049                                 #address-cells = <1>;
2050                                 #size-cells = <1>;
2051                                 ranges ;
2052
2053                                 clk_gates0: gate-clk@0160 {
2054                                         compatible = "rockchip,rk3188-gate-clk";
2055                                         reg = <0x0160 0x4>;
2056                                         clocks =
2057                                                 <&dummy>,               <&clk_apll>,
2058                                                 <&clk_gpll>,    <&aclk_bus>,
2059
2060                                                 <&hclk_bus>,    <&pclk_bus>,
2061                                                 <&dummy>,               <&aclk_bus>,
2062
2063                                                 <&clk_dpll>,    <&clk_gpll>,
2064                                                 <&clk_gpll>,    <&clk_cpll>,
2065
2066                                                 <&xin24m>,              <&dummy>,
2067                                                 <&dummy>,               <&dummy>;
2068
2069                                         clock-output-names =
2070                                                 "reserved",                     "reserved",      /* do not use bit1 = "core_apll" */
2071                                                 "clk_arm_gpll",         "g_aclk_bus",
2072
2073                                                 "hclk_bus",             "pclk_bus",
2074                                                 "reserved",             "aclk_bus_2pmu",
2075
2076                                                 "reserved",             "reserved",             /*"clk_ddr_dpll",       "clk_ddr_gpll",*/
2077                                                 "reserved",             "reserved",             /*"clk_bus_gpll",       "clk_bus_cpll",*/
2078
2079                                                 "clk_acc_efuse",                "reserved",
2080                                                 "reserved",             "reserved";
2081                                         rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>;
2082
2083                                         #clock-cells = <1>;
2084                                 };
2085
2086                                 clk_gates1: gate-clk@0164 {
2087                                         compatible = "rockchip,rk3188-gate-clk";
2088                                         reg = <0x0164 0x4>;
2089                                         clocks =
2090                                                 <&xin24m>,              <&xin24m>,
2091                                                 <&xin24m>,              <&xin24m>,
2092
2093                                                 <&xin24m>,              <&xin24m>,
2094                                                 <&dummy>,               <&dummy>,
2095
2096                                                 <&clk_uart0_pll>,               <&uart0_frac>,
2097                                                 <&clk_uart1_div>,               <&uart1_frac>,
2098
2099                                                 <&clk_uart2_div>,               <&uart2_frac>,
2100                                                 <&clk_uart3_div>,               <&uart3_frac>;
2101
2102                                         clock-output-names =
2103                                                 "clk_timer0",           "clk_timer1",
2104                                                 "clk_timer2",           "clk_timer3",
2105
2106                                                 "clk_timer4",           "clk_timer5",
2107                                                 "reserved",                     "reserved",
2108
2109                                                 "clk_uart0_pll",        "uart0_frac",
2110                                                 "clk_uart1_div",        "uart1_frac",
2111
2112                                                 "clk_uart2_div",        "uart2_frac",
2113                                                 "clk_uart3_div",        "uart3_frac";
2114
2115                                          rockchip,suspend-clkgating-setting=<0x0 0x0>;
2116                                         #clock-cells = <1>;
2117                                 };
2118
2119                                 clk_gates2: gate-clk@0168 {
2120                                         compatible = "rockchip,rk3188-gate-clk";
2121                                         reg = <0x0168 0x4>;
2122                                         clocks =
2123                                                 <&aclk_peri>,           <&aclk_peri>,
2124                                                 <&hclk_peri>,           <&pclk_peri>,
2125
2126                                                 <&dummy>,               <&clk_mac_pll>,
2127                                                 <&clk_hsadc_pll>,               <&clk_tsadc>,
2128
2129                                                 <&clk_saradc>,          <&clk_spi0>,
2130                                                 <&clk_spi1>,            <&clk_spi2>,
2131
2132                                                 <&clk_uart4_div>,               <&uart4_frac>,
2133                                                 <&dummy>,               <&dummy>;
2134
2135                                         clock-output-names =
2136                                                 "aclk_peri",            "reserved", /*"g_aclk_periph",*/
2137                                                 "hclk_peri",            "pclk_peri",
2138
2139                                                 "reserved",             "clk_mac_pll",
2140                                                 "clk_hsadc_pll",                "clk_tsadc",
2141
2142                                                 "clk_saradc",           "clk_spi0",
2143                                                 "clk_spi1",             "clk_spi2",
2144
2145                                                 "clk_uart4_div",                "uart4_frac",
2146                                                 "reserved",             "reserved";
2147                                             rockchip,suspend-clkgating-setting=<0x000f 0x000f>;
2148
2149                                         #clock-cells = <1>;
2150                                 };
2151
2152                                 clk_gates3: gate-clk@016c {
2153                                         compatible = "rockchip,rk3188-gate-clk";
2154                                         reg = <0x016c 0x4>;
2155                                         clocks =
2156                                                 <&aclk_vio0>,           <&dclk_lcdc0>,
2157                                                 <&aclk_vio1>,           <&dclk_lcdc1>,
2158
2159                                                 <&clk_rga>,                     <&aclk_rga>,
2160                                                 <&hsicphy_480m>,                <&clk_cif_pll>,
2161
2162                                                 <&dummy>,               <&clk_vepu>,
2163                                                 <&dummy>,               <&clk_vdpu>,
2164
2165                                                 <&clk_edp_24m>,         <&clk_edp>,
2166                                                 <&clk_isp>,             <&clk_isp_jpe>;
2167
2168                                         clock-output-names =
2169                                                 "aclk_vio0",            "dclk_lcdc0",
2170                                                 "aclk_vio1",            "dclk_lcdc1",
2171
2172                                                 "clk_rga",              "aclk_rga",
2173                                                 "hsicphy_480m",         "clk_cif_pll",
2174
2175                                                 /*Not use hclk_vpu_gate tmp, fixme*/
2176                                                 "reserved",             "clk_vepu",
2177                                                 "reserved",             "clk_vdpu",
2178
2179                                                 "clk_edp_24m",          "clk_edp",
2180                                                 "clk_isp",              "clk_isp_jpe";
2181                                                 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
2182
2183                                         #clock-cells = <1>;
2184                                 };
2185
2186                                 clk_gates4: gate-clk@0170 {
2187                                         compatible = "rockchip,rk3188-gate-clk";
2188                                         reg = <0x0170 0x4>;
2189                                         clocks =
2190                                                 <&clk_i2s_out>,         <&clk_i2s_pll>,
2191                                                 <&i2s_frac>,            <&clk_i2s>,
2192
2193                                                 <&spdif_div>,           <&spdif_frac>,
2194                                                 <&clk_spdif>,           <&spdif_8ch_div>,
2195
2196                                                 <&spdif_8ch_frac>,              <&clk_spdif_8ch>,
2197                                                 <&clk_tsp>,             <&clk_tspout>,
2198
2199                                                 <&clk_ddr>,             <&clk_ddr>,
2200                                                 <&jtag_clkin>,          <&dummy>;
2201
2202                                         clock-output-names =
2203                                                 "clk_i2s_out",          "clk_i2s_pll",
2204                                                 "i2s_frac",             "clk_i2s",
2205
2206                                                 "spdif_div",            "spdif_frac",
2207                                                 "clk_spdif",            "spdif_8ch_div",
2208
2209                                                 "spdif_8ch_frac",               "clk_spdif_8ch",
2210                                                 "clk_tsp",              "clk_tspout",
2211
2212                                                 /* Not use these ddr gates */
2213                                                 "reserved",             "reserved",        /*"g_clk_ddrphy0",           "g_clk_ddrphy1",*/
2214                                                 "clk_jtag",             "reserved";             /*"testclk_gate_en";*/
2215
2216                                             rockchip,suspend-clkgating-setting=<0xf000 0xf000>;
2217                                         #clock-cells = <1>;
2218                                 };
2219
2220                                 clk_gates5: gate-clk@0174 {
2221                                         compatible = "rockchip,rk3188-gate-clk";
2222                                         reg = <0x0174 0x4>;
2223                                         clocks =
2224                                                 <&clk_mac>,             <&clk_mac>,
2225                                                 <&clk_mac>,             <&clk_mac>,
2226
2227                                                 <&clk_crypto>,          <&clk_nandc0>,
2228                                                 <&clk_nandc1>,          <&clk_gpu>,
2229
2230                                                 <&pclk_pd_pmu>,         <&xin24m>,
2231                                                 <&xin24m>,              <&xin32k>,
2232
2233                                                 <&xin24m>,              <&xin24m>,
2234                                                 <&usbphy_480m>,         <&xin24m>;
2235
2236                                         clock-output-names =
2237                                                 "g_clk_mac_rx",         "g_clk_mac_tx",
2238                                                 "g_clk_mac_ref",        "g_mac_refout",
2239
2240                                                 "clk_crypto",           "clk_nandc0",
2241                                                 "clk_nandc1",           "clk_gpu",
2242
2243                                                 "pclk_pd_pmu",          "g_clk_pvtm_core",
2244                                                 "g_clk_pvtm_gpu",               "g_hdmi_cec_clk",
2245
2246                                                 "g_hdmi_hdcp_clk",              "g_ps2c_clk",
2247                                                 "usbphy_480m",          "g_mipidsi_24m";
2248                                                 rockchip,suspend-clkgating-setting=<0x0100 0x0100>;
2249
2250                                         #clock-cells = <1>;
2251                                 };
2252
2253                                 clk_gates6: gate-clk@0178 {
2254                                         compatible = "rockchip,rk3188-gate-clk";
2255                                         reg = <0x0178 0x4>;
2256                                         clocks =
2257                                                 <&hclk_peri>,           <&pclk_peri>,
2258                                                 <&aclk_peri>,           <&aclk_peri>,
2259
2260                                                 <&pclk_peri>,           <&pclk_peri>,
2261                                                 <&pclk_peri>,           <&pclk_peri>,
2262
2263                                                 <&pclk_peri>,           <&pclk_peri>,
2264                                                 <&dummy>,                       <&pclk_peri>,
2265
2266                                                 <&pclk_peri>,           <&pclk_peri>,
2267                                                 <&pclk_peri>,           <&pclk_peri>;
2268
2269                                         clock-output-names =
2270                                                 "g_hp_matrix",          "g_pp_axi_matrix",
2271                                                 "g_ap_axi_matrix",              "g_aclk_dmac2",
2272
2273                                                 "g_pclk_spi0",          "g_pclk_spi1",
2274                                                 "g_pclk_spi2",          "g_pclk_ps2c",
2275
2276                                                 "g_pclk_uart0",         "g_pclk_uart1",
2277                                                 "reserved",             "g_pclk_uart3",
2278
2279                                                 "g_pclk_uart4",         "g_pclk_i2c2",
2280                                                 "g_pclk_i2c3",          "g_pclk_i2c4";
2281                                             rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
2282
2283                                         #clock-cells = <1>;
2284                                 };
2285
2286                                 clk_gates7: gate-clk@017c {
2287                                         compatible = "rockchip,rk3188-gate-clk";
2288                                         reg = <0x017c 0x4>;
2289                                         clocks =
2290                                                 <&pclk_peri>,           <&pclk_peri>,
2291                                                 <&pclk_peri>,           <&pclk_peri>,
2292
2293                                                 <&hclk_peri>,           <&hclk_peri>,
2294                                                 <&hclk_peri>,           <&hclk_peri>,
2295
2296                                                 <&hclk_peri>,           <&hclk_peri>,
2297                                                 <&hclk_peri>,           <&aclk_peri>,
2298
2299                                                 <&hclk_peri>,           <&hclk_peri>,
2300                                                 <&hclk_peri>,           <&hclk_peri>;
2301
2302                                         clock-output-names =
2303                                                 "g_pclk_i2c5",          "g_pclk_saradc",
2304                                                 "g_pclk_tsadc",         "g_pclk_sim",
2305
2306                                                 "g_hclk_otg0",          "g_pmu_hclk_otg0",
2307                                                 "g_hclk_host0",         "g_hclk_host1",
2308
2309                                                 "g_hclk_hsic",          "g_hclk_usb_peri",
2310                                                 "g_hp_ahb_arbi",                "g_aclk_peri_niu",
2311
2312                                                 "g_h_emem_peri",                "g_hclk_mem_peri",
2313                                                 "g_hclk_nandc0",                "g_hclk_nandc1";
2314                                                 rockchip,suspend-clkgating-setting=<0x0c00 0xc000>;
2315
2316                                         #clock-cells = <1>;
2317                                 };
2318
2319                                 clk_gates8: gate-clk@0180 {
2320                                         compatible = "rockchip,rk3188-gate-clk";
2321                                         reg = <0x0180 0x4>;
2322                                         clocks =
2323                                                 <&aclk_peri>,           <&pclk_peri>,
2324                                                 <&aclk_peri>,           <&hclk_peri>,
2325
2326                                                 <&hclk_peri>,           <&hclk_peri>,
2327                                                 <&hclk_peri>,           <&hclk_peri>,
2328
2329                                                 <&hclk_peri>,           <&hsadc_0_tsp>,
2330                                                 <&hsadc_1_tsp>,         <&io_27m_in>,
2331
2332                                                 <&aclk_peri>,           <&dummy>,
2333                                                 <&dummy>,               <&dummy>;
2334
2335                                         clock-output-names =
2336                                                 "g_aclk_gmac",          "g_pclk_gmac",
2337                                                 "g_hclk_gps",           "g_hclk_sdmmc",
2338
2339                                                 "g_hclk_sdio0",         "g_hclk_sdio1",
2340                                                 "g_hclk_emmc",          "g_hclk_hsadc",
2341
2342                                                 "g_hclk_tsp",           "g_hsadc_0_tsp",
2343                                                 "g_hsadc_1_tsp",                "g_clk_27m_tsp",
2344
2345                                                 "g_aclk_peri_mmu",              "reserved",
2346                                                 "reserved",             "reserved";
2347
2348                                         rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
2349                                         #clock-cells = <1>;
2350                                 };
2351
2352                                 clk_gates9: gate-clk@0184 {
2353                                         compatible = "rockchip,rk3188-gate-clk";
2354                                         reg = <0x0184 0x4>;
2355                                         clocks =
2356                                                 <&dummy>,               <&dummy>,
2357                                                 <&dummy>,               <&dummy>,
2358
2359                                                 <&dummy>,               <&dummy>,
2360                                                 <&dummy>,               <&dummy>,
2361
2362                                                 <&dummy>,               <&dummy>,
2363                                                 <&dummy>,               <&dummy>,
2364
2365                                                 <&dummy>,               <&dummy>,
2366                                                 <&dummy>,               <&dummy>;
2367
2368                                         clock-output-names =
2369                                                 "reserved",             "reserved",             /*"aclk_video_gate_en", "hclk_video_clock_en",*/
2370                                                 "reserved",             "reserved",
2371
2372                                                 "reserved",             "reserved",
2373                                                 "reserved",             "reserved",
2374
2375                                                 "reserved",             "reserved",
2376                                                 "reserved",             "reserved",
2377
2378                                                 "reserved",             "reserved",
2379                                                 "reserved",             "reserved";
2380                                     rockchip,suspend-clkgating-setting=<0x0 0x0>;
2381
2382                                         #clock-cells = <1>;
2383                                 };
2384
2385                                 clk_gates10: gate-clk@0188 {
2386                                         compatible = "rockchip,rk3188-gate-clk";
2387                                         reg = <0x0188 0x4>;
2388                                         clocks =
2389                                                 <&pclk_bus>,            <&pclk_bus>,
2390                                                 <&pclk_bus>,            <&pclk_bus>,
2391
2392                                                 <&aclk_bus>,            <&aclk_bus>,
2393                                                 <&aclk_bus>,            <&aclk_bus>,
2394
2395                                                 <&hclk_bus>,            <&hclk_bus>,
2396                                                 <&hclk_bus>,            <&hclk_bus>,
2397
2398                                                 <&aclk_bus>,            <&aclk_bus>,
2399                                                 <&pclk_bus>,            <&pclk_bus>;
2400
2401                                         clock-output-names =
2402                                                 "g_pclk_pwm",           "g_pclk_timer",
2403                                                 "g_pclk_i2c0",          "g_pclk_i2c1",
2404
2405                                                 "g_aclk_intmem",                "g_clk_intmem0",
2406                                                 "g_clk_intmem1",                "g_clk_intmem2",
2407
2408                                                 "g_hclk_i2s",           "g_hclk_rom",
2409                                                 "g_hclk_spdif",         "g_h_spdif_8ch",
2410
2411                                                 "g_aclk_dmac1",         "g_aclk_strc_sys",
2412                                                 "reserved",             "reserved";     /*"g_p_ddrupctl0",      "g_pclk_publ0";*/
2413
2414                                                 //rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>;          // use sram  mem no gating
2415                                                 rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>;       // pwm logic vol
2416
2417                                         #clock-cells = <1>;
2418                                 };
2419
2420                                 clk_gates11: gate-clk@018c {
2421                                         compatible = "rockchip,rk3188-gate-clk";
2422                                         reg = <0x018c 0x4>;
2423                                         clocks =
2424                                                 <&pclk_bus>,            <&pclk_bus>,
2425                                                 <&pclk_bus>,            <&pclk_bus>,
2426
2427                                                 <&dummy>,               <&dummy>,
2428                                                 <&aclk_bus>,            <&hclk_bus>,
2429
2430                                                 <&aclk_bus>,            <&pclk_bus>,
2431                                                 <&pclk_bus>,            <&pclk_bus>,
2432
2433                                                 <&dummy>,               <&dummy>,
2434                                                 <&dummy>,               <&dummy>;
2435
2436                                         clock-output-names =
2437                                                 "reserved",     "reserved",     /*"g_p_ddrupctl1",      "g_pclk_publ1",*/
2438                                                 "g_p_efuse_1024",       "g_pclk_tzpc",
2439
2440                                                 "reserved",             "reserved",             /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
2441                                                 "g_aclk_crypto",        "g_hclk_crypto",
2442
2443                                                 "g_aclk_ccp",   "g_pclk_uart2",
2444                                                 "g_p_efuse_256",        "g_pclk_rkpwm",
2445
2446                                                 "reserved",             "reserved",
2447                                                 "reserved",             "reserved";
2448                                                rockchip,suspend-clkgating-setting=<0x0033 0x0033>;
2449
2450                                         #clock-cells = <1>;
2451                                 };
2452
2453                                 clk_gates12: gate-clk@0190 {
2454                                         compatible = "rockchip,rk3188-gate-clk";
2455                                         reg = <0x0190 0x4>;
2456                                         clocks =
2457                                                 <&clk_core0>,           <&clk_core1>,
2458                                                 <&clk_core2>,           <&clk_core3>,
2459
2460                                                 <&clk_l2ram>,           <&aclk_core_m0>,
2461                                                 <&aclk_core_mp>,                <&atclk_core>,
2462
2463                                                 <&pclk_dbg_src>,                <&clk_gates12 8>,
2464                                                 <&clk_gates12 8>,               <&clk_gates12 8>,
2465
2466                                                 <&dummy>,               <&dummy>,
2467                                                 <&dummy>,               <&dummy>;
2468
2469                                         clock-output-names =
2470                                                 "clk_core0",            "clk_core1",
2471                                                 "clk_core2",            "clk_core3",
2472
2473                                                 "clk_l2ram",            "aclk_core_m0",
2474                                                 "aclk_core_mp",         "atclk_core",
2475
2476                                                 "pclk_dbg_src",         "reserved",     /*"g_dbg_core_clk",*/
2477                                                 "reserved",             "reserved",             /*"g_cs_dbg_clk",       "g_pclk_core_niu",*/
2478
2479                                                 "reserved",             "reserved",
2480                                                 "reserved",             "reserved";
2481                                             rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>;
2482
2483                                         #clock-cells = <1>;
2484                                 };
2485
2486                                 clk_gates13: gate-clk@0194 {
2487                                         compatible = "rockchip,rk3188-gate-clk";
2488                                         reg = <0x0194 0x4>;
2489                                         clocks =
2490                                                 <&clk_sdmmc>,           <&clk_sdio0>,
2491                                                 <&clk_sdio1>,           <&clk_emmc>,
2492
2493                                                 <&xin24m>,              <&xin24m>,
2494                                                 <&xin24m>,              <&xin32k>,
2495
2496                                                 <&aclk_bus_src>,                <&xin12m>,
2497                                                 <&xin24m>,              <&xin24m>,
2498
2499                                                 <&dummy>,               <&aclk_hevc>,
2500                                                 <&clk_hevc_cabac>,              <&clk_hevc_core>;
2501
2502                                         clock-output-names =
2503                                                 "clk_sdmmc",            "clk_sdio0",
2504                                                 "clk_sdio1",            "clk_emmc",
2505
2506                                                 "clk_otgphy0",          "clk_otgphy1",
2507                                                 "clk_otgphy2",          "clk_otg_adp",
2508
2509                                                 "g_clk_c2c_host",               "g_clk_hsic_12m",
2510                                                 "g_clk_lcdc_pwm0",              "g_clk_lcdc_pwm1",
2511
2512                                                 "g_clk_wifi",           "aclk_hevc",
2513                                                 "clk_hevc_cabac",               "clk_hevc_core";
2514                                                 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2515
2516                                         #clock-cells = <1>;
2517                                 };
2518
2519                                 clk_gates14: gate-clk@0198 {
2520                                         compatible = "rockchip,rk3188-gate-clk";
2521                                         reg = <0x0198 0x4>;
2522                                         clocks =
2523                                                 <&dummy>,               <&pclk_pd_alive>,
2524                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2525
2526                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2527                                                 <&pclk_pd_alive>,               <&pclk_pd_alive>,
2528
2529                                                 <&pclk_pd_alive>,               <&dummy>,
2530                                                 <&dummy>,               <&pclk_pd_alive>,
2531
2532                                                 <&pclk_pd_alive>,               <&dummy>,
2533                                                 <&dummy>,               <&dummy>;
2534
2535                                         clock-output-names =
2536                                                 "reserved",             "g_pclk_gpio1",
2537                                                 "g_pclk_gpio2",         "g_pclk_gpio3",
2538
2539                                                 "g_pclk_gpio4",         "g_pclk_gpio5",
2540                                                 "g_pclk_gpio6",         "g_pclk_gpio7",
2541
2542                                                 "g_pclk_gpio8",         "reserved",
2543                                                 "reserved",             "g_pclk_grf",
2544
2545                                                 "g_p_alive_niu",                "reserved",
2546                                                 "reserved",             "reserved";
2547                                                 //rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
2548
2549                                                 rockchip,suspend-clkgating-setting=<0x1801 0x1801>;
2550
2551                                         #clock-cells = <1>;
2552                                 };
2553
2554                                 clk_gates15: gate-clk@019c {
2555                                         compatible = "rockchip,rk3188-gate-clk";
2556                                         reg = <0x019c 0x4>;
2557                                         clocks =
2558                                                 <&aclk_rga>,            <&hclk_vio>,
2559                                                 <&aclk_vio0>,           <&hclk_vio>,
2560
2561                                                 <&dummy>,               <&aclk_vio0>,
2562                                                 <&hclk_vio>,            <&aclk_vio1>,
2563
2564                                                 <&hclk_vio>,            <&hclk_vio>,
2565                                                 <&hclk_vio>,            <&aclk_vio0>,
2566
2567                                                 <&aclk_vio1>,           <&aclk_rga>,
2568                                                 <&aclk_vio0>,           <&hclk_vio>;
2569
2570                                         clock-output-names =
2571                                                 "reserved", /*"g_aclk_rga",*/   "g_hclk_rga",
2572                                                 "g_aclk_iep",           "g_hclk_iep",
2573
2574                                                 "g_aclk_lcdc_iep",              "g_aclk_lcdc0",
2575                                                 "g_hclk_lcdc0",         "g_aclk_lcdc1",
2576
2577                                                 "g_hclk_lcdc1",         "g_h_vio_ahb",
2578                                                 "g_hclk_vio_niu",               "g_aclk_vio0_niu",
2579
2580                                                 "g_aclk_vio1_niu",              "reserved",/*"g_aclk_rga_niu",*/
2581                                                 "g_aclk_vip",           "g_hclk_vip";
2582                                                 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2583
2584                                         #clock-cells = <1>;
2585                                 };
2586
2587                                 clk_gates16: gate-clk@01a0 {
2588                                         compatible = "rockchip,rk3188-gate-clk";
2589                                         reg = <0x01a0 0x4>;
2590                                         clocks =
2591                                                 <&pclkin_cif>,          <&hclk_vio>,
2592                                                 <&aclk_vio1>,           <&pclkin_isp>,
2593
2594                                                 <&hclk_vio>,            <&hclk_vio>,
2595                                                 <&hclk_vio>,            <&hclk_vio>,
2596
2597                                                 <&hclk_vio>,            <&hclk_vio>,
2598                                                 <&hclk_vio>,            <&hclk_vio>,
2599
2600                                                 <&dummy>,               <&dummy>,
2601                                                 <&dummy>,               <&dummy>;
2602
2603                                         clock-output-names =
2604                                                 "g_pclkin_cif",         "g_hclk_isp",
2605                                                 "g_aclk_isp",           "g_pclkin_isp",
2606
2607                                                 "g_p_mipi_dsi0",                "g_p_mipi_dsi1",
2608                                                 "g_p_mipi_csi",         "g_pclk_lvds_phy",
2609
2610                                                 "g_pclk_edp_ctrl",              "g_p_hdmi_ctrl",
2611                                                 "g_hclk_vio2_h2p",              "g_pclk_vio2_h2p",
2612
2613                                                 "reserved",             "reserved",
2614                                                 "reserved",             "reserved";
2615                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
2616
2617                                         #clock-cells = <1>;
2618                                 };
2619
2620                                 clk_gates17: gate-clk@01a4 {
2621                                         compatible = "rockchip,rk3188-gate-clk";
2622                                         reg = <0x01a4 0x4>;
2623                                         clocks =
2624                                                 <&pclk_pd_pmu>,         <&pclk_pd_pmu>,
2625                                                 <&pclk_pd_pmu>,         <&pclk_pd_pmu>,
2626
2627                                                 <&pclk_pd_pmu>,         <&dummy>,
2628                                                 <&dummy>,               <&dummy>,
2629
2630                                                 <&dummy>,               <&dummy>,
2631                                                 <&dummy>,               <&dummy>,
2632
2633                                                 <&dummy>,               <&dummy>,
2634                                                 <&dummy>,               <&dummy>;
2635
2636                                         clock-output-names =
2637                                                 "g_pclk_pmu",           "g_pclk_intmem1",
2638                                                 "g_pclk_pmu_niu",               "g_pclk_sgrf",
2639
2640                                                 "g_pclk_gpio0",         "reserved",
2641                                                 "reserved",             "reserved",
2642
2643                                                 "reserved",             "reserved",
2644                                                 "reserved",             "reserved",
2645
2646                                                 "reserved",             "reserved",
2647                                                 "reserved",             "reserved";
2648                                              rockchip,suspend-clkgating-setting=<0x01f 0x01f>;
2649
2650                                         #clock-cells = <1>;
2651                                 };
2652
2653                                 clk_gates18: gate-clk@01a8 {
2654                                         compatible = "rockchip,rk3188-gate-clk";
2655                                         reg = <0x01a8 0x4>;
2656                                         clocks =
2657                                                 <&clk_gpu>,             <&dummy>,
2658                                                 <&dummy>,               <&dummy>,
2659
2660                                                 <&dummy>,               <&dummy>,
2661                                                 <&dummy>,               <&dummy>,
2662
2663                                                 <&dummy>,               <&dummy>,
2664                                                 <&dummy>,               <&dummy>,
2665
2666                                                 <&dummy>,               <&dummy>,
2667                                                 <&dummy>,               <&dummy>;
2668
2669                                         clock-output-names =
2670                                                 "reserved", /*"g_aclk_gpu",*/   "reserved",
2671                                                 "reserved",             "reserved",
2672
2673                                                 "reserved",             "reserved",
2674                                                 "reserved",             "reserved",
2675
2676                                                 "reserved",             "reserved",
2677                                                 "reserved",             "reserved",
2678
2679                                                 "reserved",             "reserved",
2680                                                 "reserved",             "reserved";
2681
2682                                             rockchip,suspend-clkgating-setting=<0x0 0x0>;
2683                                         #clock-cells = <1>;
2684                                 };
2685
2686                         };
2687                 };
2688         };
2689 };