2 * Copyright (C) 2014 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk3288.h>
18 compatible = "rockchip,rk-clocks";
21 ranges = <0x0 0xFF760000 0x01b0>;
24 compatible = "rockchip,rk-fixed-rate-cons";
27 compatible = "rockchip,rk-fixed-clock";
28 clock-output-names = "xin24m";
29 clock-frequency = <24000000>;
34 compatible = "rockchip,rk-fixed-clock";
36 clock-output-names = "xin12m";
37 clock-frequency = <12000000>;
42 compatible = "rockchip,rk-fixed-clock";
43 clock-output-names = "xin32k";
44 clock-frequency = <32000>;
48 io_27m_in: io_27m_in {
49 compatible = "rockchip,rk-fixed-clock";
50 clock-output-names = "io_27m_in";
51 clock-frequency = <27000000>;
56 compatible = "rockchip,rk-fixed-clock";
57 clock-output-names = "dummy";
58 clock-frequency = <0>;
62 dummy_cpll: dummy_cpll {
63 compatible = "rockchip,rk-fixed-clock";
64 clock-output-names = "dummy_cpll";
65 clock-frequency = <0>;
69 i2s_clkin: i2s_clkin {
70 compatible = "rockchip,rk-fixed-clock";
71 clock-output-names = "i2s_clkin";
72 clock-frequency = <0>;
76 edp_24m_clkin: edp_24m_clkin {
77 compatible = "rockchip,rk-fixed-clock";
79 clock-output-names = "edp_24m_clkin";
80 clock-frequency = <0>;
83 gmac_clkin: gmac_clkin {
84 compatible = "rockchip,rk-fixed-clock";
86 clock-output-names = "gmac_clkin";
87 clock-frequency = <125000000>;
90 clk_hsadc_ext: clk_hsadc_ext {
91 compatible = "rockchip,rk-fixed-clock";
93 clock-output-names = "clk_hsadc_ext";
94 clock-frequency = <0>;
97 jtag_clkin: jtag_clkin {
98 compatible = "rockchip,rk-fixed-clock";
100 clock-output-names = "jtag_clkin";
101 clock-frequency = <0>;
104 pclkin_cif: pclkin_cif {
105 compatible = "rockchip,rk-fixed-clock";
107 clock-output-names = "pclkin_cif";
108 clock-frequency = <0>;
111 pclkin_isp: pclkin_isp {
112 compatible = "rockchip,rk-fixed-clock";
114 clock-output-names = "pclkin_isp";
115 clock-frequency = <0>;
118 hsadc_0_tsp: hsadc_0_tsp {
119 compatible = "rockchip,rk-fixed-clock";
121 clock-output-names = "hsadc_0_tsp";
122 clock-frequency = <0>;
125 hsadc_1_tsp: hsadc_1_tsp {
126 compatible = "rockchip,rk-fixed-clock";
128 clock-output-names = "hsadc_1_tsp";
129 clock-frequency = <0>;
135 compatible = "rockchip,rk-fixed-factor-cons";
137 otgphy0_480m: otgphy0_480m {
138 compatible = "rockchip,rk-fixed-factor-clock";
139 clocks = <&clk_gates13 4>;
140 clock-output-names = "otgphy0_480m";
146 otgphy1_480m: otgphy1_480m {
147 compatible = "rockchip,rk-fixed-factor-clock";
148 clocks = <&clk_gates13 5>;
149 clock-output-names = "otgphy1_480m";
155 otgphy2_480m: otgphy2_480m {
156 compatible = "rockchip,rk-fixed-factor-clock";
157 clocks = <&clk_gates13 6>;
158 clock-output-names = "otgphy2_480m";
164 clk_hsadc_inv: clk_hsadc_inv {
165 compatible = "rockchip,rk-fixed-factor-clock";
166 clocks = <&clk_hsadc_out>;
167 clock-output-names = "clk_hsadc_inv";
173 pclkin_cif_inv: pclkin_cif_inv {
174 compatible = "rockchip,rk-fixed-factor-clock";
175 clocks = <&clk_gates16 0>;
176 clock-output-names = "pclkin_cif_inv";
182 pclkin_isp_inv: pclkin_isp_inv {
183 compatible = "rockchip,rk-fixed-factor-clock";
184 clocks = <&clk_gates16 3>;
185 clock-output-names = "pclkin_isp_inv";
191 hclk_vepu: hclk_vepu {
192 compatible = "rockchip,rk-fixed-factor-clock";
193 clocks = <&clk_vepu>;
194 clock-output-names = "hclk_vepu";
200 hclk_vdpu: hclk_vdpu {
201 compatible = "rockchip,rk-fixed-factor-clock";
202 clocks = <&clk_vdpu>;
203 clock-output-names = "hclk_vdpu";
211 compatible = "rockchip,rk-pd-cons";
214 compatible = "rockchip,rk-pd-clock";
215 clock-output-names = "pd_gpu";
216 rockchip,pd-id = <CLK_PD_GPU>;
221 compatible = "rockchip,rk-pd-clock";
222 clock-output-names = "pd_video";
223 rockchip,pd-id = <CLK_PD_VIDEO>;
228 compatible = "rockchip,rk-pd-clock";
229 clock-output-names = "pd_vio";
230 rockchip,pd-id = <CLK_PD_VIO>;
235 compatible = "rockchip,rk-pd-clock";
236 clock-output-names = "pd_hevc";
237 rockchip,pd-id = <CLK_PD_HEVC>;
242 compatible = "rockchip,rk-pd-clock";
244 clock-output-names = "pd_edp";
245 rockchip,pd-id = <CLK_PD_VIRT>;
250 compatible = "rockchip,rk-pd-clock";
252 clock-output-names = "pd_vop0";
253 rockchip,pd-id = <CLK_PD_VIRT>;
258 compatible = "rockchip,rk-pd-clock";
260 clock-output-names = "pd_vop1";
261 rockchip,pd-id = <CLK_PD_VIRT>;
266 compatible = "rockchip,rk-pd-clock";
268 clock-output-names = "pd_isp";
269 rockchip,pd-id = <CLK_PD_VIRT>;
274 compatible = "rockchip,rk-pd-clock";
276 clock-output-names = "pd_iep";
277 rockchip,pd-id = <CLK_PD_VIRT>;
282 compatible = "rockchip,rk-pd-clock";
284 clock-output-names = "pd_rga";
285 rockchip,pd-id = <CLK_PD_VIRT>;
289 pd_mipicsi: pd_mipicsi {
290 compatible = "rockchip,rk-pd-clock";
292 clock-output-names = "pd_mipicsi";
293 rockchip,pd-id = <CLK_PD_VIRT>;
297 pd_mipidsi: pd_mipidsi {
298 compatible = "rockchip,rk-pd-clock";
300 clock-output-names = "pd_mipidsi";
301 rockchip,pd-id = <CLK_PD_VIRT>;
306 compatible = "rockchip,rk-pd-clock";
308 clock-output-names = "pd_lvds";
309 rockchip,pd-id = <CLK_PD_VIRT>;
314 compatible = "rockchip,rk-pd-clock";
316 clock-output-names = "pd_hdmi";
317 rockchip,pd-id = <CLK_PD_VIRT>;
325 compatible = "rockchip,rk-clock-regs";
326 #address-cells = <1>;
328 reg = <0x0000 0x3ff>;
331 /* PLL control regs */
333 compatible = "rockchip,rk-pll-cons";
334 #address-cells = <1>;
338 clk_apll: pll-clk@0000 {
339 compatible = "rockchip,rk3188-pll-clk";
341 mode-reg = <0x0050 0>;
342 status-reg = <0x0284 6>;
344 clock-output-names = "clk_apll";
345 rockchip,pll-type = <CLK_PLL_3288_APLL>;
349 clk_dpll: pll-clk@0010 {
350 compatible = "rockchip,rk3188-pll-clk";
352 mode-reg = <0x0050 4>;
353 status-reg = <0x0284 5>;
355 clock-output-names = "clk_dpll";
356 rockchip,pll-type = <CLK_PLL_3188PLUS>;
360 clk_cpll: pll-clk@0020 {
361 compatible = "rockchip,rk3188-pll-clk";
363 mode-reg = <0x0050 8>;
364 status-reg = <0x0284 7>;
366 clock-output-names = "clk_cpll";
367 rockchip,pll-type = <CLK_PLL_3188PLUS_AUTO>;
369 #clock-init-cells = <1>;
372 clk_gpll: pll-clk@0030 {
373 compatible = "rockchip,rk3188-pll-clk";
375 mode-reg = <0x0050 12>;
376 status-reg = <0x0284 8>;
378 clock-output-names = "clk_gpll";
379 rockchip,pll-type = <CLK_PLL_3188PLUS>;
381 #clock-init-cells = <1>;
384 clk_npll: pll-clk@0040 {
385 compatible = "rockchip,rk3188-pll-clk";
387 mode-reg = <0x0050 14>;
388 status-reg = <0x0284 9>;
390 clock-output-names = "clk_npll";
391 rockchip,pll-type = <CLK_PLL_3188PLUS>;
393 #clock-init-cells = <1>;
398 /* Select control regs */
400 compatible = "rockchip,rk-sel-cons";
401 #address-cells = <1>;
405 clk_sel_con0: sel-con@0060 {
406 compatible = "rockchip,rk3188-selcon";
408 #address-cells = <1>;
411 aclk_core_m0: aclk_core_m0_div {
412 compatible = "rockchip,rk3188-div-con";
413 rockchip,bits = <0 4>;
414 clocks = <&clk_core>;
415 clock-output-names = "aclk_core_m0";
416 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
418 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
421 aclk_core_mp: aclk_core_mp_div {
422 compatible = "rockchip,rk3188-div-con";
423 rockchip,bits = <4 4>;
424 clocks = <&clk_core>;
425 clock-output-names = "aclk_core_mp";
426 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
428 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
431 clk_core_div: clk_core_div {
432 compatible = "rockchip,rk3188-div-con";
433 rockchip,bits = <8 5>;
434 clocks = <&clk_core>;
435 clock-output-names = "clk_core";
436 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
438 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
439 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
440 CLK_SET_RATE_NO_REPARENT)>;
443 /* reg[14:13]: reserved */
445 clk_core: clk_core_mux {
446 compatible = "rockchip,rk3188-mux-con";
447 rockchip,bits = <15 1>;
448 clocks = <&clk_apll>, <&clk_gates0 2>;
449 clock-output-names = "clk_core";
451 #clock-init-cells = <1>;
456 clk_sel_con1: sel-con@0064 {
457 compatible = "rockchip,rk3188-selcon";
459 #address-cells = <1>;
462 aclk_bus: aclk_bus_div {
463 compatible = "rockchip,rk3188-div-con";
464 rockchip,bits = <0 3>;
465 clocks = <&aclk_bus_src_div>;
466 clock-output-names = "aclk_bus";
467 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
469 #clock-init-cells = <1>;
472 aclk_bus_src_div: aclk_bus_src_div {
473 compatible = "rockchip,rk3188-div-con";
474 rockchip,bits = <3 5>;
475 clocks = <&aclk_bus_src>;
476 clock-output-names = "aclk_bus_src";
477 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
479 rockchip,clkops-idx =
480 <CLKOPS_RATE_MUX_DIV>;
481 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
484 hclk_bus: hclk_bus_div {
485 compatible = "rockchip,rk3188-div-con";
486 rockchip,bits = <8 2>;
487 clocks = <&aclk_bus>;
488 clock-output-names = "hclk_bus";
489 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
490 rockchip,div-relations =
495 #clock-init-cells = <1>;
498 /* reg[11:10]: reserved */
500 pclk_bus: pclk_bus_div {
501 compatible = "rockchip,rk3188-div-con";
502 rockchip,bits = <12 3>;
503 clocks = <&aclk_bus>;
504 clock-output-names = "pclk_bus";
505 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
507 #clock-init-cells = <1>;
510 aclk_bus_src: aclk_bus_src_mux {
511 compatible = "rockchip,rk3188-mux-con";
512 rockchip,bits = <15 1>;
513 clocks = <&dummy_cpll>, <&clk_gpll>;
514 /*clocks = <&clk_gates0 11>, <&clk_gates0 10>; FIXME*/
515 clock-output-names = "aclk_bus_src";
517 #clock-init-cells = <1>;
522 clk_sel_con2: sel-con@0068 {
523 compatible = "rockchip,rk3188-selcon";
525 #address-cells = <1>;
528 clk_tsadc: clk_tsadc_div {
529 compatible = "rockchip,rk3188-div-con";
530 rockchip,bits = <0 6>;
532 clock-output-names = "clk_tsadc";
533 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
537 /* reg[7:6]: reserved */
539 testout_div: testout_div {
540 compatible = "rockchip,rk3188-div-con";
541 rockchip,bits = <8 5>;
543 clock-output-names = "testout_div";
544 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
548 /* reg[15:13]: reserved */
551 clk_sel_con3: sel-con@006c {
552 compatible = "rockchip,rk3188-selcon";
554 #address-cells = <1>;
557 clk_uart4_div: clk_uart4_div {
558 compatible = "rockchip,rk3188-div-con";
559 rockchip,bits = <0 7>;
560 clocks = <&uart_pll_mux>;
561 clock-output-names = "clk_uart4_div";
562 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
566 /* reg[7]: reserved */
568 clk_uart4: uart4_mux {
569 compatible = "rockchip,rk3188-mux-con";
570 rockchip,bits = <8 2>;
571 clocks = <&clk_uart4_div>, <&uart4_frac>, <&xin24m>, <&dummy>;
572 clock-output-names = "clk_uart4";
574 rockchip,clkops-idx =
575 <CLKOPS_RATE_RK3288_I2S>;
576 rockchip,flags = <CLK_SET_RATE_PARENT>;
579 /* reg[15:10]: reserved */
583 clk_sel_con4: sel-con@0070 {
584 compatible = "rockchip,rk3188-selcon";
586 #address-cells = <1>;
589 i2s_pll_div: i2s_pll_div {
590 compatible = "rockchip,rk3188-div-con";
591 rockchip,bits = <0 7>;
592 clocks = <&clk_i2s_pll>;
593 clock-output-names = "clk_i2s_pll";
594 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
596 rockchip,clkops-idx =
597 <CLKOPS_RATE_MUX_DIV>;
598 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
601 /* reg[7]: reserved */
604 compatible = "rockchip,rk3188-mux-con";
605 rockchip,bits = <8 2>;
606 clocks = <&clk_i2s_pll>, <&i2s_frac>, <&i2s_clkin>, <&xin12m>;
607 clock-output-names = "clk_i2s";
609 rockchip,clkops-idx =
610 <CLKOPS_RATE_RK3288_I2S>;
611 rockchip,flags = <CLK_SET_RATE_PARENT>;
614 /* reg[11:10]: reserved */
616 clk_i2s_out: i2s_outclk_mux {
617 compatible = "rockchip,rk3188-mux-con";
618 rockchip,bits = <12 1>;
619 clocks = <&clk_i2s>, <&xin12m>;
620 clock-output-names = "clk_i2s_out";
624 /* reg[14:13]: reserved */
626 clk_i2s_pll: i2s_pll_mux {
627 compatible = "rockchip,rk3188-mux-con";
628 rockchip,bits = <15 1>;
629 clocks = <&dummy_cpll>, <&clk_gpll>;
630 clock-output-names = "clk_i2s_pll";
632 #clock-init-cells = <1>;
636 clk_sel_con5: sel-con@0074 {
637 compatible = "rockchip,rk3188-selcon";
639 #address-cells = <1>;
642 spdif_div: spdif_div {
643 compatible = "rockchip,rk3188-div-con";
644 rockchip,bits = <0 7>;
645 clocks = <&clk_spdif_pll>;
646 clock-output-names = "spdif_div";
647 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
651 /* reg[7]: reserved */
653 clk_spdif: spdif_mux {
654 compatible = "rockchip,rk3188-mux-con";
655 rockchip,bits = <8 2>;
656 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>, <&dummy>;
657 clock-output-names = "clk_spdif";
659 rockchip,clkops-idx =
660 <CLKOPS_RATE_RK3288_I2S>;
661 rockchip,flags = <CLK_SET_RATE_PARENT>;
664 /* reg[14:10]: reserved */
666 clk_spdif_pll: spdif_pll_mux {
667 compatible = "rockchip,rk3188-mux-con";
668 rockchip,bits = <15 1>;
669 clocks = <&dummy_cpll>, <&clk_gpll>;
670 clock-output-names = "clk_spdif_pll";
672 #clock-init-cells = <1>;
676 clk_sel_con6: sel-con@0078 {
677 compatible = "rockchip,rk3188-selcon";
679 #address-cells = <1>;
682 clk_isp_div: clk_isp_div {
683 compatible = "rockchip,rk3188-div-con";
684 rockchip,bits = <0 6>;
686 clock-output-names = "clk_isp";
687 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
689 rockchip,clkops-idx =
690 <CLKOPS_RATE_MUX_DIV>;
693 clk_isp: clk_isp_mux {
694 compatible = "rockchip,rk3188-mux-con";
695 rockchip,bits = <6 2>;
696 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
697 clock-output-names = "clk_isp";
699 #clock-init-cells = <1>;
702 clk_isp_jpe_div: clk_isp_jpe_div {
703 compatible = "rockchip,rk3188-div-con";
704 rockchip,bits = <8 6>;
705 clocks = <&clk_isp_jpe>;
706 clock-output-names = "clk_isp_jpe";
707 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
709 rockchip,clkops-idx =
710 <CLKOPS_RATE_MUX_DIV>;
713 clk_isp_jpe: clk_isp_jpe_mux {
714 compatible = "rockchip,rk3188-mux-con";
715 rockchip,bits = <14 2>;
716 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
717 clock-output-names = "clk_isp_jpe";
719 #clock-init-cells = <1>;
723 clk_sel_con7: sel-con@007c {
724 compatible = "rockchip,rk3188-selcon";
726 #address-cells = <1>;
729 uart4_frac: uart4_frac {
730 compatible = "rockchip,rk3188-frac-con";
731 clocks = <&clk_uart4_div>;
732 clock-output-names = "uart4_frac";
733 /* numerator denominator */
734 rockchip,bits = <0 32>;
735 rockchip,clkops-idx =
741 clk_sel_con8: sel-con@0080 {
742 compatible = "rockchip,rk3188-selcon";
744 #address-cells = <1>;
748 compatible = "rockchip,rk3188-frac-con";
749 clocks = <&clk_i2s_pll>;
750 clock-output-names = "i2s_frac";
751 /* numerator denominator */
752 rockchip,bits = <0 32>;
753 rockchip,clkops-idx =
759 clk_sel_con9: sel-con@0084 {
760 compatible = "rockchip,rk3188-selcon";
762 #address-cells = <1>;
765 spdif_frac: spdif_frac {
766 compatible = "rockchip,rk3188-frac-con";
767 clocks = <&spdif_div>;
768 clock-output-names = "spdif_frac";
769 /* numerator denominator */
770 rockchip,bits = <0 32>;
771 rockchip,clkops-idx =
777 clk_sel_con10: sel-con@0088 {
778 compatible = "rockchip,rk3188-selcon";
780 #address-cells = <1>;
783 aclk_peri_div: aclk_peri_div {
784 compatible = "rockchip,rk3188-div-con";
785 rockchip,bits = <0 5>;
786 clocks = <&aclk_peri>;
787 clock-output-names = "aclk_peri";
788 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
790 rockchip,clkops-idx =
791 <CLKOPS_RATE_MUX_DIV>;
792 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
795 /* reg[7:5]: reserved */
797 hclk_peri: hclk_peri_div {
798 compatible = "rockchip,rk3188-div-con";
799 rockchip,bits = <8 2>;
800 clocks = <&aclk_peri>;
801 clock-output-names = "hclk_peri";
802 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
803 rockchip,div-relations =
808 #clock-init-cells = <1>;
811 /* reg[11:10]: reserved */
813 pclk_peri: pclk_peri_div {
814 compatible = "rockchip,rk3188-div-con";
815 rockchip,bits = <12 2>;
816 clocks = <&aclk_peri>;
817 clock-output-names = "pclk_peri";
818 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
819 rockchip,div-relations =
825 #clock-init-cells = <1>;
828 /* reg[14]: reserved */
830 aclk_peri: aclk_peri_mux {
831 compatible = "rockchip,rk3188-mux-con";
832 rockchip,bits = <15 1>;
833 clocks = <&dummy_cpll>, <&clk_gpll>;
834 clock-output-names = "aclk_peri";
836 #clock-init-cells = <1>;
840 clk_sel_con11: sel-con@008c {
841 compatible = "rockchip,rk3188-selcon";
843 #address-cells = <1>;
846 clk_sdmmc_div: clk_sdmmc_div {
847 compatible = "rockchip,rk3188-div-con";
848 rockchip,bits = <0 6>;
849 clocks = <&clk_sdmmc>;
850 clock-output-names = "clk_sdmmc";
851 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
853 rockchip,clkops-idx =
854 <CLKOPS_RATE_MUX_EVENDIV>;
857 clk_sdmmc: clk_sdmmc_mux {
858 compatible = "rockchip,rk3188-mux-con";
859 rockchip,bits = <6 2>;
860 clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
861 clock-output-names = "clk_sdmmc";
865 hsicphy_12m_div: hsicphy_12m_div {
866 compatible = "rockchip,rk3188-div-con";
867 rockchip,bits = <8 6>;
868 clocks = <&hsicphy_480m>;
869 clock-output-names = "hsicphy_12m_div";
870 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
876 clk_sel_con12: sel-con@0090 {
877 compatible = "rockchip,rk3188-selcon";
879 #address-cells = <1>;
882 clk_sdio0_div: clk_sdio0_div {
883 compatible = "rockchip,rk3188-div-con";
884 rockchip,bits = <0 6>;
885 clocks = <&clk_sdio0>;
886 clock-output-names = "clk_sdio0";
887 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
889 rockchip,clkops-idx =
890 <CLKOPS_RATE_MUX_EVENDIV>;
893 clk_sdio0: clk_sdio0_mux {
894 compatible = "rockchip,rk3188-mux-con";
895 rockchip,bits = <6 2>;
896 clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
897 clock-output-names = "clk_sdio0";
901 clk_emmc_div: clk_emmc_div {
902 compatible = "rockchip,rk3188-div-con";
903 rockchip,bits = <8 6>;
904 clocks = <&clk_emmc>;
905 clock-output-names = "clk_emmc";
906 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
908 rockchip,clkops-idx =
909 <CLKOPS_RATE_MUX_EVENDIV>;
912 clk_emmc: clk_emmc_mux {
913 compatible = "rockchip,rk3188-mux-con";
914 rockchip,bits = <14 2>;
915 clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
916 clock-output-names = "clk_emmc";
921 clk_sel_con13: sel-con@0094 {
922 compatible = "rockchip,rk3188-selcon";
924 #address-cells = <1>;
927 clk_uart0_pll_div: clk_uart0_pll_div {
928 compatible = "rockchip,rk3188-div-con";
929 rockchip,bits = <0 7>;
930 clocks = <&clk_uart0_pll>;
931 clock-output-names = "clk_uart0_pll";
932 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
934 rockchip,clkops-idx =
935 <CLKOPS_RATE_MUX_DIV>;
938 /* reg[7]: reserved */
940 clk_uart0: uart0_mux {
941 compatible = "rockchip,rk3188-mux-con";
942 rockchip,bits = <8 2>;
943 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>, <&dummy>;
944 clock-output-names = "clk_uart0";
946 rockchip,clkops-idx =
947 <CLKOPS_RATE_RK3288_I2S>;
948 rockchip,flags = <CLK_SET_RATE_PARENT>;
951 /* reg[10]: reserved */
953 usbphy_480m: usbphy_480m_mux {
954 compatible = "rockchip,rk3188-mux-con";
955 rockchip,bits = <11 2>;
956 clocks = <&otgphy1_480m>, <&otgphy2_480m>, <&otgphy0_480m>;
957 clock-output-names = "usbphy_480m";
959 rockchip,clkops-idx =
960 <CLKOPS_RATE_RK3288_USB480M>;
961 #clock-init-cells = <1>;
964 clk_uart0_pll: clk_uart0_pll_mux {
965 compatible = "rockchip,rk3188-mux-con";
966 rockchip,bits = <13 2>;
967 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
968 clock-output-names = "clk_uart0_pll";
972 uart_pll_mux: uart_pll_mux {
973 compatible = "rockchip,rk3188-mux-con";
974 rockchip,bits = <15 1>;
975 clocks = <&dummy_cpll>, <&clk_gpll>;
976 clock-output-names = "uart_pll_mux";
978 #clock-init-cells = <1>;
982 clk_sel_con14: sel-con@0098 {
983 compatible = "rockchip,rk3188-selcon";
985 #address-cells = <1>;
988 clk_uart1_div: clk_uart1_div {
989 compatible = "rockchip,rk3188-div-con";
990 rockchip,bits = <0 7>;
991 clocks = <&uart_pll_mux>;
992 clock-output-names = "clk_uart1_div";
993 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
997 /* reg[7]: reserved */
999 clk_uart1: uart1_mux {
1000 compatible = "rockchip,rk3188-mux-con";
1001 rockchip,bits = <8 2>;
1002 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>, <&dummy>;
1003 clock-output-names = "clk_uart1";
1005 rockchip,clkops-idx =
1006 <CLKOPS_RATE_RK3288_I2S>;
1007 rockchip,flags = <CLK_SET_RATE_PARENT>;
1010 /* reg[15:10]: reserved */
1013 clk_sel_con15: sel-con@009c {
1014 compatible = "rockchip,rk3188-selcon";
1016 #address-cells = <1>;
1019 clk_uart2_div: clk_uart2_div {
1020 compatible = "rockchip,rk3188-div-con";
1021 rockchip,bits = <0 7>;
1022 clocks = <&uart_pll_mux>;
1023 clock-output-names = "clk_uart2_div";
1024 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1028 /* reg[7]: reserved */
1030 clk_uart2: uart2_mux {
1031 compatible = "rockchip,rk3188-mux-con";
1032 rockchip,bits = <8 2>;
1033 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>, <&dummy>;
1034 clock-output-names = "clk_uart2";
1036 rockchip,clkops-idx =
1037 <CLKOPS_RATE_RK3288_I2S>;
1038 rockchip,flags = <CLK_SET_RATE_PARENT>;
1041 /* reg[15:10]: reserved */
1044 clk_sel_con16: sel-con@00a0 {
1045 compatible = "rockchip,rk3188-selcon";
1047 #address-cells = <1>;
1050 clk_uart3_div: clk_uart3_div {
1051 compatible = "rockchip,rk3188-div-con";
1052 rockchip,bits = <0 7>;
1053 clocks = <&uart_pll_mux>;
1054 clock-output-names = "clk_uart3_div";
1055 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1059 /* reg[7]: reserved */
1061 clk_uart3: uart3_mux {
1062 compatible = "rockchip,rk3188-mux-con";
1063 rockchip,bits = <8 2>;
1064 clocks = <&clk_uart3_div>, <&uart3_frac>, <&xin24m>, <&dummy>;
1065 clock-output-names = "clk_uart3";
1067 rockchip,clkops-idx =
1068 <CLKOPS_RATE_RK3288_I2S>;
1069 rockchip,flags = <CLK_SET_RATE_PARENT>;
1072 /* reg[15:10]: reserved */
1075 clk_sel_con17: sel-con@00a4 {
1076 compatible = "rockchip,rk3188-selcon";
1078 #address-cells = <1>;
1081 uart0_frac: uart0_frac {
1082 compatible = "rockchip,rk3188-frac-con";
1083 clocks = <&clk_uart0_pll>;
1084 clock-output-names = "uart0_frac";
1085 /* numerator denominator */
1086 rockchip,bits = <0 32>;
1087 rockchip,clkops-idx =
1093 clk_sel_con18: sel-con@00a8 {
1094 compatible = "rockchip,rk3188-selcon";
1096 #address-cells = <1>;
1099 uart1_frac: uart1_frac {
1100 compatible = "rockchip,rk3188-frac-con";
1101 clocks = <&clk_uart1_div>;
1102 clock-output-names = "uart1_frac";
1103 /* numerator denominator */
1104 rockchip,bits = <0 32>;
1105 rockchip,clkops-idx =
1111 clk_sel_con19: sel-con@00ac {
1112 compatible = "rockchip,rk3188-selcon";
1114 #address-cells = <1>;
1117 uart2_frac: uart2_frac {
1118 compatible = "rockchip,rk3188-frac-con";
1119 clocks = <&clk_uart2_div>;
1120 clock-output-names = "uart2_frac";
1121 /* numerator denominator */
1122 rockchip,bits = <0 32>;
1123 rockchip,clkops-idx =
1130 clk_sel_con20: sel-con@00b0 {
1131 compatible = "rockchip,rk3188-selcon";
1133 #address-cells = <1>;
1136 uart3_frac: uart3_frac {
1137 compatible = "rockchip,rk3188-frac-con";
1138 clocks = <&clk_uart3_div>;
1139 clock-output-names = "uart3_frac";
1140 /* numerator denominator */
1141 rockchip,bits = <0 32>;
1142 rockchip,clkops-idx =
1148 clk_sel_con21: sel-con@00b4 {
1149 compatible = "rockchip,rk3188-selcon";
1151 #address-cells = <1>;
1154 clk_mac_pll: clk_mac_pll_mux {
1155 compatible = "rockchip,rk3188-mux-con";
1156 rockchip,bits = <0 2>;
1157 clocks = <&clk_npll>, <&dummy_cpll>, <&clk_gpll>;
1158 clock-output-names = "clk_mac_pll";
1162 /* reg[3:2]: reserved */
1164 clk_mac: clk_mac_mux {
1165 compatible = "rockchip,rk3188-mux-con";
1166 rockchip,bits = <4 1>;
1167 clocks = <&clk_mac_pll>, <&gmac_clkin>;
1168 clock-output-names = "clk_mac";
1170 rockchip,clkops-idx =
1171 <CLKOPS_RATE_MAC_REF>;
1172 rockchip,flags = <CLK_SET_RATE_PARENT>;
1173 #clock-init-cells = <1>;
1176 /* reg[7:5]: reserved */
1178 clk_mac_pll_div: clk_mac_pll_div {
1179 compatible = "rockchip,rk3188-div-con";
1180 rockchip,bits = <8 5>;
1181 clocks = <&clk_mac_pll>;
1182 clock-output-names = "clk_mac_pll";
1183 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1185 rockchip,clkops-idx =
1186 <CLKOPS_RATE_MUX_DIV>;
1189 /* reg[15:13]: reserved */
1192 clk_sel_con22: sel-con@00b8 {
1193 compatible = "rockchip,rk3188-selcon";
1195 #address-cells = <1>;
1198 clk_hsadc_pll: clk_hsadc_pll_mux {
1199 compatible = "rockchip,rk3188-mux-con";
1200 rockchip,bits = <0 1>;
1201 clocks = <&dummy_cpll>, <&clk_gpll>;
1202 clock-output-names = "clk_hsadc_pll";
1206 wifi_pll_mux: wifi_pll_mux {
1207 compatible = "rockchip,rk3188-mux-con";
1208 rockchip,bits = <1 1>;
1210 clock-output-names = "wifi_pll_mux";
1215 /* reg[3:2]: reserved */
1217 clk_hsadc_out: clk_hsadc_out {
1218 compatible = "rockchip,rk3188-mux-con";
1219 rockchip,bits = <4 1>;
1220 clocks = <&clk_hsadc_pll>, <&clk_hsadc_ext>;
1221 clock-output-names = "clk_hsadc_out";
1223 rockchip,clkops-idx =
1224 <CLKOPS_RATE_HSADC>;
1225 rockchip,flags = <CLK_SET_RATE_PARENT>;
1228 /* reg[6:5]: reserved */
1230 clk_hsadc: clk_hsadc {
1231 compatible = "rockchip,rk3188-mux-con";
1232 rockchip,bits = <7 1>;
1233 clocks = <&clk_hsadc_out>, <&clk_hsadc_inv>;
1234 clock-output-names = "clk_hsadc";
1238 clk_hsadc_pll_div: clk_hsadc_pll_div {
1239 compatible = "rockchip,rk3188-div-con";
1240 rockchip,bits = <8 8>;
1241 clocks = <&clk_hsadc_pll>;
1242 clock-output-names = "clk_hsadc_pll";
1243 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1245 rockchip,clkops-idx =
1246 <CLKOPS_RATE_MUX_DIV>;
1250 clk_sel_con23: sel-con@00bc {
1251 compatible = "rockchip,rk3188-selcon";
1253 #address-cells = <1>;
1256 wifi_frac: wifi_frac {
1257 compatible = "rockchip,rk3188-frac-con";
1259 clock-output-names = "wifi_frac";
1260 / numerator denominator /
1261 rockchip,bits = <0 32>;
1262 rockchip,clkops-idx =
1269 clk_sel_con24: sel-con@00c0 {
1270 compatible = "rockchip,rk3188-selcon";
1272 #address-cells = <1>;
1275 /* reg[7:0]: reserved */
1277 clk_saradc: clk_saradc_div {
1278 compatible = "rockchip,rk3188-div-con";
1279 rockchip,bits = <8 8>;
1281 clock-output-names = "clk_saradc";
1282 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1287 clk_sel_con25: sel-con@00c4 {
1288 compatible = "rockchip,rk3188-selcon";
1290 #address-cells = <1>;
1293 clk_spi0_div: clk_spi0_div {
1294 compatible = "rockchip,rk3188-div-con";
1295 rockchip,bits = <0 7>;
1296 clocks = <&clk_spi0>;
1297 clock-output-names = "clk_spi0";
1298 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1300 rockchip,clkops-idx =
1301 <CLKOPS_RATE_MUX_DIV>;
1304 clk_spi0: clk_spi0_mux {
1305 compatible = "rockchip,rk3188-mux-con";
1306 rockchip,bits = <7 1>;
1307 clocks = <&dummy_cpll>, <&clk_gpll>;
1308 clock-output-names = "clk_spi0";
1312 clk_spi1_div: clk_spi1_div {
1313 compatible = "rockchip,rk3188-div-con";
1314 rockchip,bits = <8 7>;
1315 clocks = <&clk_spi1>;
1316 clock-output-names = "clk_spi1";
1317 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1319 rockchip,clkops-idx =
1320 <CLKOPS_RATE_MUX_DIV>;
1323 clk_spi1: clk_spi1_mux {
1324 compatible = "rockchip,rk3188-mux-con";
1325 rockchip,bits = <15 1>;
1326 clocks = <&dummy_cpll>, <&clk_gpll>;
1327 clock-output-names = "clk_spi1";
1332 clk_sel_con26: sel-con@00c8 {
1333 compatible = "rockchip,rk3188-selcon";
1335 #address-cells = <1>;
1339 compatible = "rockchip,rk3188-div-con";
1340 rockchip,bits = <0 2>;
1341 clocks = <&clk_ddr>;
1342 clock-output-names = "clk_ddr";
1343 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1344 rockchip,div-relations =
1349 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1350 CLK_SET_RATE_NO_REPARENT)>;
1351 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
1354 clk_ddr: ddr_clk_pll_mux {
1355 compatible = "rockchip,rk3188-mux-con";
1356 rockchip,bits = <2 1>;
1357 clocks = <&clk_dpll>, <&clk_gpll>;
1358 clock-output-names = "clk_ddr";
1362 /* reg[5:3]: reserved */
1364 clk_crypto: crypto_div {
1365 compatible = "rockchip,rk3188-div-con";
1366 rockchip,bits = <6 2>;
1367 clocks = <&aclk_bus>;
1368 clock-output-names = "clk_crypto";
1369 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1371 #clock-init-cells = <1>;
1374 clk_cif_pll: clk_cif_pll_mux {
1375 compatible = "rockchip,rk3188-mux-con";
1376 rockchip,bits = <8 1>;
1377 clocks = <&dummy_cpll>, <&clk_gpll>;
1378 clock-output-names = "clk_cif_pll";
1382 clk_cif_out_div: clk_cif_out_div {
1383 compatible = "rockchip,rk3188-div-con";
1384 rockchip,bits = <9 5>;
1385 clocks = <&clk_cif_out>;
1386 clock-output-names = "clk_cif_out";
1387 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1389 rockchip,clkops-idx =
1390 <CLKOPS_RATE_MUX_DIV>;
1393 /* reg[14]: reserved */
1395 clk_cif_out: clk_cif_out_mux {
1396 compatible = "rockchip,rk3188-mux-con";
1397 rockchip,bits = <15 1>;
1398 clocks = <&clk_cif_pll>, <&xin24m>;
1399 clock-output-names = "clk_cif_out";
1404 clk_sel_con27: sel-con@00cc {
1405 compatible = "rockchip,rk3188-selcon";
1407 #address-cells = <1>;
1410 dclk_lcdc0: dclk_lcdc0_mux {
1411 compatible = "rockchip,rk3188-mux-con";
1412 rockchip,bits = <0 2>;
1413 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1414 clock-output-names = "dclk_lcdc0";
1418 /* reg[7:2]: reserved */
1420 dclk_lcdc0_div: dclk_lcdc0_div {
1421 compatible = "rockchip,rk3188-div-con";
1422 rockchip,bits = <8 8>;
1423 clocks = <&dclk_lcdc0>;
1424 clock-output-names = "dclk_lcdc0";
1425 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1427 rockchip,clkops-idx =
1428 <CLKOPS_RATE_RK3288_DCLK_LCDC0>;
1429 rockchip,flags = <CLK_SET_RATE_PARENT>;
1433 clk_sel_con28: sel-con@00d0 {
1434 compatible = "rockchip,rk3188-selcon";
1436 #address-cells = <1>;
1439 clk_edp_div: clk_edp_div {
1440 compatible = "rockchip,rk3188-div-con";
1441 rockchip,bits = <0 6>;
1442 clocks = <&clk_edp>;
1443 clock-output-names = "clk_edp";
1444 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1446 rockchip,clkops-idx =
1447 <CLKOPS_RATE_MUX_DIV>;
1450 clk_edp: clk_edp_mux {
1451 compatible = "rockchip,rk3188-mux-con";
1452 rockchip,bits = <6 2>;
1453 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
1454 clock-output-names = "clk_edp";
1456 #clock-init-cells = <1>;
1459 hclk_vio: hclk_vio_div {
1460 compatible = "rockchip,rk3188-div-con";
1461 rockchip,bits = <8 5>;
1462 clocks = <&clk_gates15 11>;
1463 clock-output-names = "hclk_vio";
1464 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1466 #clock-init-cells = <1>;
1469 /* reg[14:13]: reserved */
1471 clk_edp_24m: edp_24m_mux {
1472 compatible = "rockchip,rk3188-mux-con";
1473 rockchip,bits = <15 1>;
1474 clocks = <&edp_24m_clkin>, <&xin24m>;
1475 clock-output-names = "clk_edp_24m";
1480 clk_sel_con29: sel-con@00d4 {
1481 compatible = "rockchip,rk3188-selcon";
1483 #address-cells = <1>;
1486 hsicphy_480m: hsicphy_480m_mux {
1487 compatible = "rockchip,rk3188-mux-con";
1488 rockchip,bits = <0 2>;
1489 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
1490 clock-output-names = "hsicphy_480m";
1494 hsicphy_12m: hsicphy_12m_mux {
1495 compatible = "rockchip,rk3188-mux-con";
1496 rockchip,bits = <2 1>;
1497 clocks = <&clk_gates13 9>, <&hsicphy_12m_div>;
1498 clock-output-names = "hsicphy_12m";
1502 clkin_isp: clkin_isp {
1503 compatible = "rockchip,rk3188-mux-con";
1504 rockchip,bits = <3 1>;
1505 clocks = <&clk_gates16 3>, <&pclkin_isp_inv>;
1506 clock-output-names = "clkin_isp";
1510 clkin_cif: clkin_cif {
1511 compatible = "rockchip,rk3188-mux-con";
1512 rockchip,bits = <4 1>;
1513 clocks = <&clk_gates16 0>, <&pclkin_cif_inv>;
1514 clock-output-names = "clkin_cif";
1518 /* reg[5]: reserved */
1520 dclk_lcdc1: dclk_lcdc1_mux {
1521 compatible = "rockchip,rk3188-mux-con";
1522 rockchip,bits = <6 2>;
1523 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>;
1524 clock-output-names = "dclk_lcdc1";
1528 dclk_lcdc1_div: dclk_lcdc1_div {
1529 compatible = "rockchip,rk3188-div-con";
1530 rockchip,bits = <8 8>;
1531 clocks = <&dclk_lcdc1>;
1532 clock-output-names = "dclk_lcdc1";
1533 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1535 rockchip,clkops-idx =
1536 <CLKOPS_RATE_RK3288_DCLK_LCDC1>;
1537 rockchip,flags = <CLK_SET_RATE_PARENT>;
1541 clk_sel_con30: sel-con@00d8 {
1542 compatible = "rockchip,rk3188-selcon";
1544 #address-cells = <1>;
1547 aclk_rga_div: aclk_rga_div {
1548 compatible = "rockchip,rk3188-div-con";
1549 rockchip,bits = <0 5>;
1550 clocks = <&aclk_rga>;
1551 clock-output-names = "aclk_rga";
1552 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1554 rockchip,clkops-idx =
1555 <CLKOPS_RATE_MUX_DIV>;
1558 /* reg[5]: reserved */
1560 aclk_rga: aclk_rga_mux {
1561 compatible = "rockchip,rk3188-mux-con";
1562 rockchip,bits = <6 2>;
1563 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
1564 clock-output-names = "aclk_rga";
1566 #clock-init-cells = <1>;
1569 clk_rga_div: clk_rga_div {
1570 compatible = "rockchip,rk3188-div-con";
1571 rockchip,bits = <8 5>;
1572 clocks = <&clk_rga>;
1573 clock-output-names = "clk_rga";
1574 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1576 rockchip,clkops-idx =
1577 <CLKOPS_RATE_MUX_DIV>;
1580 /* reg[13]: reserved */
1582 clk_rga: clk_rga_mux {
1583 compatible = "rockchip,rk3188-mux-con";
1584 rockchip,bits = <14 2>;
1585 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
1586 clock-output-names = "clk_rga";
1588 #clock-init-cells = <1>;
1592 clk_sel_con31: sel-con@00dc {
1593 compatible = "rockchip,rk3188-selcon";
1595 #address-cells = <1>;
1598 aclk_vio0_div: aclk_vio0_div {
1599 compatible = "rockchip,rk3188-div-con";
1600 rockchip,bits = <0 5>;
1601 clocks = <&aclk_vio0>;
1602 clock-output-names = "aclk_vio0";
1603 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1605 rockchip,clkops-idx =
1606 <CLKOPS_RATE_MUX_DIV>;
1607 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1610 /* reg[5]: reserved */
1612 aclk_vio0: aclk_vio0_mux {
1613 compatible = "rockchip,rk3188-mux-con";
1614 rockchip,bits = <6 2>;
1615 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1616 clock-output-names = "aclk_vio0";
1618 #clock-init-cells = <1>;
1621 aclk_vio1_div: aclk_vio1_div {
1622 compatible = "rockchip,rk3188-div-con";
1623 rockchip,bits = <8 5>;
1624 clocks = <&aclk_vio1>;
1625 clock-output-names = "aclk_vio1";
1626 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1628 rockchip,clkops-idx =
1629 <CLKOPS_RATE_MUX_DIV>;
1630 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1633 /* reg[13]: reserved */
1635 aclk_vio1: aclk_vio1_mux {
1636 compatible = "rockchip,rk3188-mux-con";
1637 rockchip,bits = <14 2>;
1638 clocks = <&clk_cpll>, <&clk_gpll>, <&usbphy_480m>;
1639 clock-output-names = "aclk_vio1";
1641 #clock-init-cells = <1>;
1645 clk_sel_con32: sel-con@00e0 {
1646 compatible = "rockchip,rk3188-selcon";
1648 #address-cells = <1>;
1651 clk_vepu_div: clk_vepu_div {
1652 compatible = "rockchip,rk3188-div-con";
1653 rockchip,bits = <0 5>;
1654 clocks = <&clk_vepu>;
1655 clock-output-names = "clk_vepu";
1656 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1658 rockchip,clkops-idx =
1659 <CLKOPS_RATE_MUX_DIV>;
1662 /* reg[5]: reserved */
1664 clk_vepu: clk_vepu_mux {
1665 compatible = "rockchip,rk3188-mux-con";
1666 rockchip,bits = <6 2>;
1667 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
1668 clock-output-names = "clk_vepu";
1670 #clock-init-cells = <1>;
1673 clk_vdpu_div: clk_vdpu_div {
1674 compatible = "rockchip,rk3188-div-con";
1675 rockchip,bits = <8 5>;
1676 clocks = <&clk_vdpu>;
1677 clock-output-names = "clk_vdpu";
1678 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1680 rockchip,clkops-idx =
1681 <CLKOPS_RATE_MUX_DIV>;
1684 /* reg[13]: reserved */
1686 clk_vdpu: clk_vdpu_mux {
1687 compatible = "rockchip,rk3188-mux-con";
1688 rockchip,bits = <14 2>;
1689 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>;
1690 clock-output-names = "clk_vdpu";
1692 #clock-init-cells = <1>;
1696 clk_sel_con33: sel-con@00e4 {
1697 compatible = "rockchip,rk3188-selcon";
1699 #address-cells = <1>;
1702 pclk_pd_pmu: pclk_pd_pmu_div {
1703 compatible = "rockchip,rk3188-div-con";
1704 rockchip,bits = <0 5>;
1705 clocks = <&clk_gpll>;
1706 clock-output-names = "pclk_pd_pmu";
1707 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1709 #clock-init-cells = <1>;
1712 /* reg[7:5]: reserved */
1714 pclk_pd_alive: pclk_pd_alive {
1715 compatible = "rockchip,rk3188-div-con";
1716 rockchip,bits = <8 5>;
1717 clocks = <&clk_gpll>;
1718 clock-output-names = "pclk_pd_alive";
1719 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1721 #clock-init-cells = <1>;
1724 /* reg[15:13]: reserved */
1727 clk_sel_con34: sel-con@00e8 {
1728 compatible = "rockchip,rk3188-selcon";
1730 #address-cells = <1>;
1733 clk_gpu_div: clk_gpu_div {
1734 compatible = "rockchip,rk3188-div-con";
1735 rockchip,bits = <0 5>;
1736 clocks = <&clk_gpu>;
1737 clock-output-names = "clk_gpu";
1738 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1740 rockchip,clkops-idx =
1741 <CLKOPS_RATE_MUX_DIV>;
1742 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1745 /* reg[5]: reserved */
1747 clk_gpu: clk_gpu_mux {
1748 compatible = "rockchip,rk3188-mux-con";
1749 rockchip,bits = <6 2>;
1750 clocks = <&dummy_cpll>, <&clk_gpll>, <&usbphy_480m>, <&clk_npll>;
1751 clock-output-names = "clk_gpu";
1753 #clock-init-cells = <1>;
1756 clk_sdio1_div: clk_sdio1_div {
1757 compatible = "rockchip,rk3188-div-con";
1758 rockchip,bits = <8 6>;
1759 clocks = <&clk_sdio1>;
1760 clock-output-names = "clk_sdio1";
1761 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1763 rockchip,clkops-idx =
1764 <CLKOPS_RATE_MUX_EVENDIV>;
1767 clk_sdio1: clk_sdio1_mux {
1768 compatible = "rockchip,rk3188-mux-con";
1769 rockchip,bits = <14 2>;
1770 clocks = <&dummy_cpll>, <&clk_gpll>, <&xin24m>;
1771 clock-output-names = "clk_sdio1";
1776 clk_sel_con35: sel-con@00ec {
1777 compatible = "rockchip,rk3188-selcon";
1779 #address-cells = <1>;
1782 clk_tsp_div: clk_tsp_div {
1783 compatible = "rockchip,rk3188-div-con";
1784 rockchip,bits = <0 5>;
1785 clocks = <&clk_tsp>;
1786 clock-output-names = "clk_tsp";
1787 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1789 rockchip,clkops-idx =
1790 <CLKOPS_RATE_MUX_DIV>;
1793 /* reg[5]: reserved */
1795 clk_tsp: clk_tsp_mux {
1796 compatible = "rockchip,rk3188-mux-con";
1797 rockchip,bits = <6 2>;
1798 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
1799 clock-output-names = "clk_tsp";
1801 #clock-init-cells = <1>;
1804 clk_tspout_div: clk_tspout_div {
1805 compatible = "rockchip,rk3188-div-con";
1806 rockchip,bits = <8 5>;
1807 clocks = <&clk_tspout>;
1808 clock-output-names = "clk_tspout";
1809 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1811 rockchip,clkops-idx =
1812 <CLKOPS_RATE_MUX_DIV>;
1815 /* reg[13]: reserved */
1817 clk_tspout: clk_tspout_mux {
1818 compatible = "rockchip,rk3188-mux-con";
1819 rockchip,bits = <14 2>;
1820 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>, <&io_27m_in>;
1821 clock-output-names = "clk_tspout";
1823 #clock-init-cells = <1>;
1827 clk_sel_con36: sel-con@00f0 {
1828 compatible = "rockchip,rk3188-selcon";
1830 #address-cells = <1>;
1833 clk_core0: clk_core0_div {
1834 compatible = "rockchip,rk3188-div-con";
1835 rockchip,bits = <0 3>;
1836 clocks = <&clk_core>;
1837 clock-output-names = "clk_core0";
1838 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1840 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1843 /* reg[3]: reserved */
1845 clk_core1: clk_core1_div {
1846 compatible = "rockchip,rk3188-div-con";
1847 rockchip,bits = <4 3>;
1848 clocks = <&clk_core>;
1849 clock-output-names = "clk_core1";
1850 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1852 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1855 /* reg[7]: reserved */
1857 clk_core2: clk_core2_div {
1858 compatible = "rockchip,rk3188-div-con";
1859 rockchip,bits = <8 3>;
1860 clocks = <&clk_core>;
1861 clock-output-names = "clk_core2";
1862 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1864 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1867 /* reg[11]: reserved */
1869 clk_core3: clk_core3_div {
1870 compatible = "rockchip,rk3188-div-con";
1871 rockchip,bits = <12 3>;
1872 clocks = <&clk_core>;
1873 clock-output-names = "clk_core3";
1874 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1876 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1879 /* reg[15]: reserved */
1882 clk_sel_con37: sel-con@00f4 {
1883 compatible = "rockchip,rk3188-selcon";
1885 #address-cells = <1>;
1888 clk_l2ram: clk_l2ram_div {
1889 compatible = "rockchip,rk3188-div-con";
1890 rockchip,bits = <0 3>;
1891 clocks = <&clk_core>;
1892 clock-output-names = "clk_l2ram";
1893 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1895 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1898 /* reg[3]: reserved */
1900 atclk_core: atclk_core_div {
1901 compatible = "rockchip,rk3188-div-con";
1902 rockchip,bits = <4 5>;
1903 clocks = <&clk_core>;
1904 clock-output-names = "atclk_core";
1905 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1907 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1910 pclk_dbg_src: pclk_core_dbg_div {
1911 compatible = "rockchip,rk3188-div-con";
1912 rockchip,bits = <9 5>;
1913 clocks = <&clk_core>;
1914 clock-output-names = "pclk_dbg_src";
1915 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1917 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
1920 /* reg[15:14]: reserved */
1923 clk_sel_con38: sel-con@00f8 {
1924 compatible = "rockchip,rk3188-selcon";
1926 #address-cells = <1>;
1929 clk_nandc0_div: clk_nandc0_div {
1930 compatible = "rockchip,rk3188-div-con";
1931 rockchip,bits = <0 5>;
1932 clocks = <&clk_nandc0>;
1933 clock-output-names = "clk_nandc0";
1934 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1936 rockchip,clkops-idx =
1937 <CLKOPS_RATE_MUX_DIV>;
1940 /* reg[6:5]: reserved */
1942 clk_nandc0: clk_nandc0_mux {
1943 compatible = "rockchip,rk3188-mux-con";
1944 rockchip,bits = <7 1>;
1945 clocks = <&dummy_cpll>, <&clk_gpll>;
1946 clock-output-names = "clk_nandc0";
1950 clk_nandc1_div: clk_nandc1_div {
1951 compatible = "rockchip,rk3188-div-con";
1952 rockchip,bits = <8 5>;
1953 clocks = <&clk_nandc1>;
1954 clock-output-names = "clk_nandc1";
1955 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1957 rockchip,clkops-idx =
1958 <CLKOPS_RATE_MUX_DIV>;
1961 /* reg[14:13]: reserved */
1963 clk_nandc1: clk_nandc1_mux {
1964 compatible = "rockchip,rk3188-mux-con";
1965 rockchip,bits = <15 1>;
1966 clocks = <&dummy_cpll>, <&clk_gpll>;
1967 clock-output-names = "clk_nandc1";
1972 clk_sel_con39: sel-con@00fc {
1973 compatible = "rockchip,rk3188-selcon";
1975 #address-cells = <1>;
1978 clk_spi2_div: clk_spi2_div {
1979 compatible = "rockchip,rk3188-div-con";
1980 rockchip,bits = <0 7>;
1981 clocks = <&clk_spi2>;
1982 clock-output-names = "clk_spi2";
1983 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1985 rockchip,clkops-idx =
1986 <CLKOPS_RATE_MUX_DIV>;
1989 clk_spi2: clk_spi2_mux {
1990 compatible = "rockchip,rk3188-mux-con";
1991 rockchip,bits = <7 1>;
1992 clocks = <&dummy_cpll>, <&clk_gpll>;
1993 clock-output-names = "clk_spi2";
1997 aclk_hevc_div: aclk_hevc_div {
1998 compatible = "rockchip,rk3188-div-con";
1999 rockchip,bits = <8 5>;
2000 clocks = <&aclk_hevc>;
2001 clock-output-names = "aclk_hevc";
2002 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2004 rockchip,clkops-idx =
2005 <CLKOPS_RATE_MUX_DIV>;
2006 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
2009 /* reg[13]: reserved */
2011 aclk_hevc: aclk_hevc_mux {
2012 compatible = "rockchip,rk3188-mux-con";
2013 rockchip,bits = <14 2>;
2014 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
2015 clock-output-names = "aclk_hevc";
2017 #clock-init-cells = <1>;
2021 clk_sel_con40: sel-con@0100 {
2022 compatible = "rockchip,rk3188-selcon";
2024 #address-cells = <1>;
2027 spdif_8ch_div: spdif_8ch_div {
2028 compatible = "rockchip,rk3188-div-con";
2029 rockchip,bits = <0 7>;
2030 clocks = <&clk_spdif_pll>;
2031 clock-output-names = "spdif_8ch_div";
2032 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2036 /* reg[7]: reserved */
2038 clk_spdif_8ch: spdif_8ch_clk_mux {
2039 compatible = "rockchip,rk3188-mux-con";
2040 rockchip,bits = <8 2>;
2041 clocks = <&spdif_8ch_div>, <&spdif_8ch_frac>, <&xin12m>;
2042 clock-output-names = "clk_spdif_8ch";
2044 rockchip,clkops-idx =
2045 <CLKOPS_RATE_RK3288_I2S>;
2046 rockchip,flags = <CLK_SET_RATE_PARENT>;
2049 /* reg[11:10]: reserved */
2051 hclk_hevc: hclk_hevc_div {
2052 compatible = "rockchip,rk3188-div-con";
2053 rockchip,bits = <12 2>;
2054 clocks = <&aclk_hevc>;
2055 clock-output-names = "hclk_hevc";
2056 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2058 #clock-init-cells = <1>;
2061 /* reg[15:14]: reserved */
2064 clk_sel_con41: sel-con@0104 {
2065 compatible = "rockchip,rk3188-selcon";
2067 #address-cells = <1>;
2070 spdif_8ch_frac: spdif_8ch_frac {
2071 compatible = "rockchip,rk3188-frac-con";
2072 clocks = <&spdif_8ch_div>;
2073 clock-output-names = "spdif_8ch_frac";
2074 /* numerator denominator */
2075 rockchip,bits = <0 32>;
2076 rockchip,clkops-idx =
2082 clk_sel_con42: sel-con@0108 {
2083 compatible = "rockchip,rk3188-selcon";
2085 #address-cells = <1>;
2088 clk_hevc_cabac_div: clk_hevc_cabac_div {
2089 compatible = "rockchip,rk3188-div-con";
2090 rockchip,bits = <0 5>;
2091 clocks = <&clk_hevc_cabac>;
2092 clock-output-names = "clk_hevc_cabac";
2093 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2095 rockchip,clkops-idx =
2096 <CLKOPS_RATE_MUX_DIV>;
2097 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
2100 /* reg[5]: reserved */
2102 clk_hevc_cabac: clk_hevc_cabac_mux {
2103 compatible = "rockchip,rk3188-mux-con";
2104 rockchip,bits = <6 2>;
2105 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
2106 clock-output-names = "clk_hevc_cabac";
2108 #clock-init-cells = <1>;
2111 clk_hevc_core_div: clk_hevc_core_div {
2112 compatible = "rockchip,rk3188-div-con";
2113 rockchip,bits = <8 5>;
2114 clocks = <&clk_hevc_core>;
2115 clock-output-names = "clk_hevc_core";
2116 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
2118 rockchip,clkops-idx =
2119 <CLKOPS_RATE_MUX_DIV>;
2120 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
2123 /* reg[13]: reserved */
2125 clk_hevc_core: clk_hevc_core_mux {
2126 compatible = "rockchip,rk3188-mux-con";
2127 rockchip,bits = <14 2>;
2128 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_npll>;
2129 clock-output-names = "clk_hevc_core";
2131 #clock-init-cells = <1>;
2138 /* Gate control regs */
2140 compatible = "rockchip,rk-gate-cons";
2141 #address-cells = <1>;
2145 clk_gates0: gate-clk@0160 {
2146 compatible = "rockchip,rk3188-gate-clk";
2149 <&dummy>, <&clk_apll>,
2150 <&clk_gpll>, <&aclk_bus>,
2152 <&hclk_bus>, <&pclk_bus>,
2153 <&dummy>, <&aclk_bus>,
2155 <&clk_dpll>, <&clk_gpll>,
2156 <&clk_gpll>, <&clk_cpll>,
2158 <&xin24m>, <&dummy>,
2161 clock-output-names =
2162 "reserved", "reserved", /* do not use bit1 = "core_apll" */
2163 "clk_arm_gpll", "g_aclk_bus",
2165 "hclk_bus", "pclk_bus",
2166 "reserved", "aclk_bus_2pmu",
2168 "reserved", "reserved", /*"clk_ddr_dpll", "clk_ddr_gpll",*/
2169 "reserved", "reserved", /*"clk_bus_gpll", "clk_bus_cpll",*/
2171 "clk_acc_efuse", "reserved",
2172 "reserved", "reserved";
2173 rockchip,suspend-clkgating-setting=<0x0fff 0x0fff>;
2178 clk_gates1: gate-clk@0164 {
2179 compatible = "rockchip,rk3188-gate-clk";
2182 <&xin24m>, <&xin24m>,
2183 <&xin24m>, <&xin24m>,
2185 <&xin24m>, <&xin24m>,
2188 <&clk_uart0_pll>, <&uart0_frac>,
2189 <&clk_uart1_div>, <&uart1_frac>,
2191 <&clk_uart2_div>, <&uart2_frac>,
2192 <&clk_uart3_div>, <&uart3_frac>;
2194 clock-output-names =
2195 "clk_timer0", "clk_timer1",
2196 "clk_timer2", "clk_timer3",
2198 "clk_timer4", "clk_timer5",
2199 "reserved", "reserved",
2201 "clk_uart0_pll", "uart0_frac",
2202 "clk_uart1_div", "uart1_frac",
2204 "clk_uart2_div", "uart2_frac",
2205 "clk_uart3_div", "uart3_frac";
2207 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2211 clk_gates2: gate-clk@0168 {
2212 compatible = "rockchip,rk3188-gate-clk";
2215 <&aclk_peri>, <&aclk_peri>,
2216 <&hclk_peri>, <&pclk_peri>,
2218 <&dummy>, <&clk_mac_pll>,
2219 <&clk_hsadc_pll>, <&clk_tsadc>,
2221 <&clk_saradc>, <&clk_spi0>,
2222 <&clk_spi1>, <&clk_spi2>,
2224 <&clk_uart4_div>, <&uart4_frac>,
2227 clock-output-names =
2228 "aclk_peri", "reserved", /*"g_aclk_periph",*/
2229 "hclk_peri", "pclk_peri",
2231 "reserved", "clk_mac_pll",
2232 "clk_hsadc_pll", "clk_tsadc",
2234 "clk_saradc", "clk_spi0",
2235 "clk_spi1", "clk_spi2",
2237 "clk_uart4_div", "uart4_frac",
2238 "reserved", "reserved";
2239 rockchip,suspend-clkgating-setting=<0x000f 0x000f>;
2244 clk_gates3: gate-clk@016c {
2245 compatible = "rockchip,rk3188-gate-clk";
2248 <&aclk_vio0>, <&dclk_lcdc0>,
2249 <&aclk_vio1>, <&dclk_lcdc1>,
2251 <&clk_rga>, <&aclk_rga>,
2252 <&hsicphy_480m>, <&clk_cif_pll>,
2254 <&dummy>, <&clk_vepu>,
2255 <&dummy>, <&clk_vdpu>,
2257 <&clk_edp_24m>, <&clk_edp>,
2258 <&clk_isp>, <&clk_isp_jpe>;
2260 clock-output-names =
2261 "aclk_vio0", "dclk_lcdc0",
2262 "aclk_vio1", "dclk_lcdc1",
2264 "clk_rga", "aclk_rga",
2265 "hsicphy_480m", "clk_cif_pll",
2267 /*Not use hclk_vpu_gate tmp, fixme*/
2268 "reserved", "clk_vepu",
2269 "reserved", "clk_vdpu",
2271 "clk_edp_24m", "clk_edp",
2272 "clk_isp", "clk_isp_jpe";
2273 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
2278 clk_gates4: gate-clk@0170 {
2279 compatible = "rockchip,rk3188-gate-clk";
2282 <&clk_i2s_out>, <&clk_i2s_pll>,
2283 <&i2s_frac>, <&clk_i2s>,
2285 <&spdif_div>, <&spdif_frac>,
2286 <&clk_spdif>, <&spdif_8ch_div>,
2288 <&spdif_8ch_frac>, <&clk_spdif_8ch>,
2289 <&clk_tsp>, <&clk_tspout>,
2291 <&clk_ddr>, <&clk_ddr>,
2292 <&jtag_clkin>, <&dummy>;
2294 clock-output-names =
2295 "clk_i2s_out", "clk_i2s_pll",
2296 "i2s_frac", "clk_i2s",
2298 "spdif_div", "spdif_frac",
2299 "clk_spdif", "spdif_8ch_div",
2301 "spdif_8ch_frac", "clk_spdif_8ch",
2302 "clk_tsp", "clk_tspout",
2304 /* Not use these ddr gates */
2305 "reserved", "reserved", /*"g_clk_ddrphy0", "g_clk_ddrphy1",*/
2306 "clk_jtag", "reserved"; /*"testclk_gate_en";*/
2308 rockchip,suspend-clkgating-setting=<0xf000 0xf000>;
2312 clk_gates5: gate-clk@0174 {
2313 compatible = "rockchip,rk3188-gate-clk";
2316 <&clk_mac>, <&clk_mac>,
2317 <&clk_mac>, <&clk_mac>,
2319 <&clk_crypto>, <&clk_nandc0>,
2320 <&clk_nandc1>, <&clk_gpu>,
2322 <&pclk_pd_pmu>, <&xin24m>,
2323 <&xin24m>, <&xin32k>,
2325 <&xin24m>, <&xin24m>,
2326 <&usbphy_480m>, <&xin24m>;
2328 clock-output-names =
2329 "g_clk_mac_rx", "g_clk_mac_tx",
2330 "g_clk_mac_ref", "g_mac_refout",
2332 "clk_crypto", "clk_nandc0",
2333 "clk_nandc1", "clk_gpu",
2335 "pclk_pd_pmu", "g_clk_pvtm_core",
2336 "g_clk_pvtm_gpu", "g_hdmi_cec_clk",
2338 "g_hdmi_hdcp_clk", "g_ps2c_clk",
2339 "usbphy_480m", "g_mipidsi_24m";
2340 rockchip,suspend-clkgating-setting=<0x0100 0x0100>;
2345 clk_gates6: gate-clk@0178 {
2346 compatible = "rockchip,rk3188-gate-clk";
2349 <&hclk_peri>, <&pclk_peri>,
2350 <&aclk_peri>, <&aclk_peri>,
2352 <&pclk_peri>, <&pclk_peri>,
2353 <&pclk_peri>, <&pclk_peri>,
2355 <&pclk_peri>, <&pclk_peri>,
2356 <&dummy>, <&pclk_peri>,
2358 <&pclk_peri>, <&pclk_peri>,
2359 <&pclk_peri>, <&pclk_peri>;
2361 clock-output-names =
2362 "g_hp_matrix", "g_pp_axi_matrix",
2363 "g_ap_axi_matrix", "g_aclk_dmac2",
2365 "g_pclk_spi0", "g_pclk_spi1",
2366 "g_pclk_spi2", "g_pclk_ps2c",
2368 "g_pclk_uart0", "g_pclk_uart1",
2369 "reserved", "g_pclk_uart3",
2371 "g_pclk_uart4", "g_pclk_i2c1",
2372 "g_pclk_i2c3", "g_pclk_i2c4";
2373 rockchip,suspend-clkgating-setting=<0x0003 0x0003>;
2378 clk_gates7: gate-clk@017c {
2379 compatible = "rockchip,rk3188-gate-clk";
2382 <&pclk_peri>, <&pclk_peri>,
2383 <&pclk_peri>, <&pclk_peri>,
2385 <&hclk_peri>, <&hclk_peri>,
2386 <&hclk_peri>, <&hclk_peri>,
2388 <&hclk_peri>, <&hclk_peri>,
2389 <&hclk_peri>, <&aclk_peri>,
2391 <&hclk_peri>, <&hclk_peri>,
2392 <&hclk_peri>, <&hclk_peri>;
2394 clock-output-names =
2395 "g_pclk_i2c5", "g_pclk_saradc",
2396 "g_pclk_tsadc", "g_pclk_sim",
2398 "g_hclk_otg0", "g_pmu_hclk_otg0",
2399 "g_hclk_host0", "g_hclk_host1",
2401 "g_hclk_hsic", "g_hclk_usb_peri",
2402 "g_hp_ahb_arbi", "g_aclk_peri_niu",
2404 "g_h_emem_peri", "g_hclk_mem_peri",
2405 "g_hclk_nandc0", "g_hclk_nandc1";
2406 rockchip,suspend-clkgating-setting=<0x0c00 0xc000>;
2411 clk_gates8: gate-clk@0180 {
2412 compatible = "rockchip,rk3188-gate-clk";
2415 <&aclk_peri>, <&pclk_peri>,
2416 <&aclk_peri>, <&hclk_peri>,
2418 <&hclk_peri>, <&hclk_peri>,
2419 <&hclk_peri>, <&hclk_peri>,
2421 <&hclk_peri>, <&hsadc_0_tsp>,
2422 <&hsadc_1_tsp>, <&io_27m_in>,
2424 <&aclk_peri>, <&dummy>,
2427 clock-output-names =
2428 "g_aclk_gmac", "g_pclk_gmac",
2429 "g_hclk_gps", "g_hclk_sdmmc",
2431 "g_hclk_sdio0", "g_hclk_sdio1",
2432 "g_hclk_emmc", "g_hclk_hsadc",
2434 "g_hclk_tsp", "g_hsadc_0_tsp",
2435 "g_hsadc_1_tsp", "g_clk_27m_tsp",
2437 "g_aclk_peri_mmu", "reserved",
2438 "reserved", "reserved";
2440 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
2444 clk_gates9: gate-clk@0184 {
2445 compatible = "rockchip,rk3188-gate-clk";
2460 clock-output-names =
2461 "reserved", "reserved", /*"aclk_video_gate_en", "hclk_video_clock_en",*/
2462 "reserved", "reserved",
2464 "reserved", "reserved",
2465 "reserved", "reserved",
2467 "reserved", "reserved",
2468 "reserved", "reserved",
2470 "reserved", "reserved",
2471 "reserved", "reserved";
2472 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2477 clk_gates10: gate-clk@0188 {
2478 compatible = "rockchip,rk3188-gate-clk";
2481 <&pclk_bus>, <&pclk_bus>,
2482 <&pclk_bus>, <&pclk_bus>,
2484 <&aclk_bus>, <&aclk_bus>,
2485 <&aclk_bus>, <&aclk_bus>,
2487 <&hclk_bus>, <&hclk_bus>,
2488 <&hclk_bus>, <&hclk_bus>,
2490 <&aclk_bus>, <&aclk_bus>,
2491 <&pclk_bus>, <&pclk_bus>;
2493 clock-output-names =
2494 "g_pclk_pwm", "g_pclk_timer",
2495 "g_pclk_i2c0", "g_pclk_i2c2",
2497 "g_aclk_intmem", "g_clk_intmem0",
2498 "g_clk_intmem1", "g_clk_intmem2",
2500 "g_hclk_i2s", "g_hclk_rom",
2501 "g_hclk_spdif", "g_h_spdif_8ch",
2503 "g_aclk_dmac1", "g_aclk_strc_sys",
2504 "reserved", "reserved"; /*"g_p_ddrupctl0", "g_pclk_publ0";*/
2506 //rockchip,suspend-clkgating-setting=<0xe2f1 0xe2f1>; // use sram mem no gating
2507 rockchip,suspend-clkgating-setting=<0xf2f1 0xf2f1>; // pwm logic vol
2512 clk_gates11: gate-clk@018c {
2513 compatible = "rockchip,rk3188-gate-clk";
2516 <&pclk_bus>, <&pclk_bus>,
2517 <&pclk_bus>, <&pclk_bus>,
2520 <&aclk_bus>, <&hclk_bus>,
2522 <&aclk_bus>, <&pclk_bus>,
2523 <&pclk_bus>, <&pclk_bus>,
2528 clock-output-names =
2529 "reserved", "reserved", /*"g_p_ddrupctl1", "g_pclk_publ1",*/
2530 "g_p_efuse_1024", "g_pclk_tzpc",
2532 "reserved", "reserved", /*"g_nclk_ddrupctl0", "g_nclk_ddrupctl1"*/
2533 "g_aclk_crypto", "g_hclk_crypto",
2535 "g_aclk_ccp", "g_pclk_uart2",
2536 "g_p_efuse_256", "g_pclk_rkpwm",
2538 "reserved", "reserved",
2539 "reserved", "reserved";
2540 rockchip,suspend-clkgating-setting=<0x0033 0x0033>;
2545 clk_gates12: gate-clk@0190 {
2546 compatible = "rockchip,rk3188-gate-clk";
2549 <&clk_core0>, <&clk_core1>,
2550 <&clk_core2>, <&clk_core3>,
2552 <&clk_l2ram>, <&aclk_core_m0>,
2553 <&aclk_core_mp>, <&atclk_core>,
2555 <&pclk_dbg_src>, <&pclk_dbg_src>,
2556 <&pclk_dbg_src>, <&pclk_dbg_src>,
2561 clock-output-names =
2562 "clk_core0", "clk_core1",
2563 "clk_core2", "clk_core3",
2565 "clk_l2ram", "aclk_core_m0",
2566 "aclk_core_mp", "atclk_core",
2568 "pclk_dbg_src", "g_dbg_core_clk",
2569 "g_cs_dbg_clk", "g_pclk_core_niu",
2571 "reserved", "reserved",
2572 "reserved", "reserved";
2573 rockchip,suspend-clkgating-setting=<0x0ff1 0x0ff1>;
2578 clk_gates13: gate-clk@0194 {
2579 compatible = "rockchip,rk3188-gate-clk";
2582 <&clk_sdmmc>, <&clk_sdio0>,
2583 <&clk_sdio1>, <&clk_emmc>,
2585 <&xin24m>, <&xin24m>,
2586 <&xin24m>, <&xin32k>,
2588 <&aclk_bus_src>, <&xin12m>,
2589 <&xin24m>, <&xin24m>,
2591 <&dummy>, <&aclk_hevc>,
2592 <&clk_hevc_cabac>, <&clk_hevc_core>;
2594 clock-output-names =
2595 "clk_sdmmc", "clk_sdio0",
2596 "clk_sdio1", "clk_emmc",
2598 "clk_otgphy0", "clk_otgphy1",
2599 "clk_otgphy2", "clk_otg_adp",
2601 "g_clk_c2c_host", "g_clk_hsic_12m",
2602 "g_clk_lcdc_pwm0", "g_clk_lcdc_pwm1",
2604 "g_clk_wifi", "aclk_hevc",
2605 "clk_hevc_cabac", "clk_hevc_core";
2606 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2611 clk_gates14: gate-clk@0198 {
2612 compatible = "rockchip,rk3188-gate-clk";
2615 <&dummy>, <&pclk_pd_alive>,
2616 <&pclk_pd_alive>, <&pclk_pd_alive>,
2618 <&pclk_pd_alive>, <&pclk_pd_alive>,
2619 <&pclk_pd_alive>, <&pclk_pd_alive>,
2621 <&pclk_pd_alive>, <&dummy>,
2622 <&dummy>, <&pclk_pd_alive>,
2624 <&pclk_pd_alive>, <&dummy>,
2627 clock-output-names =
2628 "reserved", "g_pclk_gpio1",
2629 "g_pclk_gpio2", "g_pclk_gpio3",
2631 "g_pclk_gpio4", "g_pclk_gpio5",
2632 "g_pclk_gpio6", "g_pclk_gpio7",
2634 "g_pclk_gpio8", "reserved",
2635 "reserved", "g_pclk_grf",
2637 "g_p_alive_niu", "reserved",
2638 "reserved", "reserved";
2639 //rockchip,suspend-clkgating-setting=<0xffff 0xffff>;
2641 rockchip,suspend-clkgating-setting=<0x19fe 0x19fe>;
2646 clk_gates15: gate-clk@019c {
2647 compatible = "rockchip,rk3188-gate-clk";
2650 <&aclk_rga>, <&hclk_vio>,
2651 <&clk_gates15 11>, <&hclk_vio>,
2653 <&dummy>, <&clk_gates15 11>,
2654 <&hclk_vio>, <&clk_gates15 12>,
2656 <&hclk_vio>, <&dummy>,
2657 <&dummy>, <&aclk_vio0>,
2659 <&aclk_vio1>, <&aclk_rga>,
2660 <&clk_gates15 11>, <&hclk_vio>;
2662 clock-output-names =
2663 "reserved", /*"g_aclk_rga"*/ "g_hclk_rga",
2664 "g_aclk_iep", "g_hclk_iep",
2666 "g_aclk_lcdc_iep", "g_aclk_lcdc0",
2667 "g_hclk_lcdc0", "g_aclk_lcdc1",
2669 "g_hclk_lcdc1", "reserved", /* "g_h_vio_ahb" */
2670 "reserved",/*"g_hclk_vio_niu"*/ "g_aclk_vio0_niu",
2672 "g_aclk_vio1_niu", "reserved",/*"g_aclk_rga_niu"*/
2673 "g_aclk_vip", "g_hclk_vip";
2674 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2679 clk_gates16: gate-clk@01a0 {
2680 compatible = "rockchip,rk3188-gate-clk";
2683 <&pclkin_cif>, <&hclk_vio>,
2684 <&clk_gates15 12>, <&pclkin_isp>,
2686 <&hclk_vio>, <&hclk_vio>,
2687 <&hclk_vio>, <&hclk_vio>,
2689 <&hclk_vio>, <&hclk_vio>,
2695 clock-output-names =
2696 "g_pclkin_cif", "g_hclk_isp",
2697 "g_aclk_isp", "g_pclkin_isp",
2699 "g_p_mipi_dsi0", "g_p_mipi_dsi1",
2700 "g_p_mipi_csi", "g_pclk_lvds_phy",
2702 "g_pclk_edp_ctrl", "g_p_hdmi_ctrl",
2703 "reserved", "reserved", /* bit10:"g_hclk_vio2_h2p" bit11: "g_pclk_vio2_h2p" */
2705 "reserved", "reserved",
2706 "reserved", "reserved";
2707 rockchip,suspend-clkgating-setting=<0x0 0x0>;
2712 clk_gates17: gate-clk@01a4 {
2713 compatible = "rockchip,rk3188-gate-clk";
2716 <&pclk_pd_pmu>, <&pclk_pd_pmu>,
2717 <&pclk_pd_pmu>, <&pclk_pd_pmu>,
2719 <&pclk_pd_pmu>, <&dummy>,
2728 clock-output-names =
2729 "g_pclk_pmu", "g_pclk_intmem1",
2730 "g_pclk_pmu_niu", "g_pclk_sgrf",
2732 "g_pclk_gpio0", "reserved",
2733 "reserved", "reserved",
2735 "reserved", "reserved",
2736 "reserved", "reserved",
2738 "reserved", "reserved",
2739 "reserved", "reserved";
2740 rockchip,suspend-clkgating-setting=<0x01f 0x01f>;
2745 clk_gates18: gate-clk@01a8 {
2746 compatible = "rockchip,rk3188-gate-clk";
2749 <&clk_gpu>, <&dummy>,
2761 clock-output-names =
2762 "reserved", /*"g_aclk_gpu",*/ "reserved",
2763 "reserved", "reserved",
2765 "reserved", "reserved",
2766 "reserved", "reserved",
2768 "reserved", "reserved",
2769 "reserved", "reserved",
2771 "reserved", "reserved",
2772 "reserved", "reserved";
2774 rockchip,suspend-clkgating-setting=<0x0 0x0>;