arch/arm/boot/dts/rk322x.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3228-cru.h>
  46 #include <dt-bindings/suspend/rockchip-rk322x.h>
  47 #include <dt-bindings/thermal/thermal.h>
  48 #include "skeleton.dtsi"
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52
  53         aliases {
  54                 serial0 = &uart0;
  55                 serial1 = &uart1;
  56                 serial2 = &uart2;
  57         };
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 cpu0: cpu@f00 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a7";
  66                         reg = <0xf00>;
  67                         resets = <&cru SRST_CORE0>;
  68                         operating-points-v2 = <&cpu0_opp_table>;
  69                         #cooling-cells = <2>; /* min followed by max */
  70                         clock-latency = <40000>;
  71                         clocks = <&cru ARMCLK>;
  72                 };
  73
  74                 cpu1: cpu@f01 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a7";
  77                         reg = <0xf01>;
  78                         resets = <&cru SRST_CORE1>;
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                 };
  81
  82                 cpu2: cpu@f02 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a7";
  85                         reg = <0xf02>;
  86                         resets = <&cru SRST_CORE2>;
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88                 };
  89
  90                 cpu3: cpu@f03 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0xf03>;
  94                         resets = <&cru SRST_CORE3>;
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                 };
  97         };
  98
  99         cpu0_opp_table: opp_table0 {
 100                 compatible = "operating-points-v2";
 101                 opp-shared;
 102
 103                 nvmem-cells = <&cpu_leakage>;
 104                 nvmem-cell-names = "cpu_leakage";
 105
 106                 opp-408000000 {
 107                         opp-hz = /bits/ 64 <408000000>;
 108                         opp-microvolt = <950000>;
 109                         clock-latency-ns = <40000>;
 110                         opp-suspend;
 111                 };
 112                 opp-600000000 {
 113                         opp-hz = /bits/ 64 <600000000>;
 114                         opp-microvolt = <975000>;
 115                 };
 116                 opp-816000000 {
 117                         opp-hz = /bits/ 64 <816000000>;
 118                         opp-microvolt = <1000000>;
 119                 };
 120                 opp-1008000000 {
 121                         opp-hz = /bits/ 64 <1008000000>;
 122                         opp-microvolt = <1175000>;
 123                 };
 124                 opp-1200000000 {
 125                         opp-hz = /bits/ 64 <1200000000>;
 126                         opp-microvolt = <1275000>;
 127                 };
 128         };
 129
 130         amba {
 131                 compatible = "arm,amba-bus";
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 ranges;
 135
 136                 pdma: pdma@110f0000 {
 137                         compatible = "arm,pl330", "arm,primecell";
 138                         reg = <0x110f0000 0x4000>;
 139                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 140                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 141                         #dma-cells = <1>;
 142                         clocks = <&cru ACLK_DMAC>;
 143                         clock-names = "apb_pclk";
 144                         peripherals-req-type-burst;
 145                 };
 146         };
 147
 148         arm-pmu {
 149                 compatible = "arm,cortex-a7-pmu";
 150                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 151                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 154                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 155         };
 156
 157         timer {
 158                 compatible = "arm,armv7-timer";
 159                 arm,cpu-registers-not-fw-configured;
 160                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 161                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 162                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 163                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 164                 clock-frequency = <24000000>;
 165         };
 166
 167         xin24m: oscillator {
 168                 compatible = "fixed-clock";
 169                 clock-frequency = <24000000>;
 170                 clock-output-names = "xin24m";
 171                 #clock-cells = <0>;
 172         };
 173
 174         i2s1: i2s1@100b0000 {
 175                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 176                 reg = <0x100b0000 0x4000>;
 177                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 178                 #address-cells = <1>;
 179                 #size-cells = <0>;
 180                 clock-names = "i2s_clk", "i2s_hclk";
 181                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 182                 dmas = <&pdma 14>, <&pdma 15>;
 183                 dma-names = "tx", "rx";
 184                 pinctrl-names = "default";
 185                 pinctrl-0 = <&i2s1_bus>;
 186                 status = "disabled";
 187         };
 188
 189         i2s0: i2s0@100c0000 {
 190                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 191                 reg = <0x100c0000 0x4000>;
 192                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 193                 #address-cells = <1>;
 194                 #size-cells = <0>;
 195                 clock-names = "i2s_clk", "i2s_hclk";
 196                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 197                 dmas = <&pdma 11>, <&pdma 12>;
 198                 dma-names = "tx", "rx";
 199                 status = "disabled";
 200         };
 201
 202         spdif: spdif@100d0000 {
 203                 compatible = "rockchip,rk3228-spdif";
 204                 reg = <0x100d0000 0x1000>;
 205                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 206                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 207                 clock-names = "mclk", "hclk";
 208                 dmas = <&pdma 10>;
 209                 #dma-cells = <1>;
 210                 dma-names = "tx";
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&spdif_tx>;
 213                 status = "disabled";
 214         };
 215
 216         i2s2: i2s2@100e0000 {
 217                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 218                 reg = <0x100e0000 0x4000>;
 219                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 220                 #address-cells = <1>;
 221                 #size-cells = <0>;
 222                 clock-names = "i2s_clk", "i2s_hclk";
 223                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 224                 dmas = <&pdma 0>, <&pdma 1>;
 225                 dma-names = "tx", "rx";
 226                 status = "disabled";
 227         };
 228
 229         grf: syscon@11000000 {
 230                 compatible = "syscon", "simple-mfd";
 231                 reg = <0x11000000 0x1000>;
 232                 #address-cells = <1>;
 233                 #size-cells = <1>;
 234
 235                 io_domains: io-domains {
 236                         compatible = "rockchip,rk322x-io-voltage-domain";
 237                         status = "disabled";
 238                 };
 239
 240                 u2phy0: usb2-phy@760 {
 241                         compatible = "rockchip,rk322x-usb2phy";
 242                         reg = <0x0760 0x0c>;
 243                         clocks = <&cru SCLK_OTGPHY0>;
 244                         clock-names = "phyclk";
 245                         #clock-cells = <0>;
 246                         clock-output-names = "usb480m_phy0";
 247                         status = "disabled";
 248
 249                         u2phy0_otg: otg-port {
 250                                 #phy-cells = <0>;
 251                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 252                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 253                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 254                                 interrupt-names = "otg-bvalid", "otg-id",
 255                                                   "linestate";
 256                                 status = "disabled";
 257                         };
 258
 259                         u2phy0_host: host-port {
 260                                 #phy-cells = <0>;
 261                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 262                                 interrupt-names = "linestate";
 263                                 status = "disabled";
 264                         };
 265                 };
 266
 267                 u2phy1: usb2-phy@800 {
 268                         compatible = "rockchip,rk322x-usb2phy";
 269                         reg = <0x0800 0x0c>;
 270                         clocks = <&cru SCLK_OTGPHY1>;
 271                         clock-names = "phyclk";
 272                         #clock-cells = <0>;
 273                         clock-output-names = "usb480m_phy1";
 274                         status = "disabled";
 275
 276                         u2phy1_otg: otg-port {
 277                                 #phy-cells = <0>;
 278                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 279                                 interrupt-names = "linestate";
 280                                 status = "disabled";
 281                         };
 282
 283                         u2phy1_host: host-port {
 284                                 #phy-cells = <0>;
 285                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 286                                 interrupt-names = "linestate";
 287                                 status = "disabled";
 288                         };
 289                 };
 290         };
 291
 292         uart0: serial@11010000 {
 293                 compatible = "snps,dw-apb-uart";
 294                 reg = <0x11010000 0x100>;
 295                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 296                 clock-frequency = <24000000>;
 297                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 298                 clock-names = "baudclk", "apb_pclk";
 299                 pinctrl-names = "default";
 300                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 301                 reg-shift = <2>;
 302                 reg-io-width = <4>;
 303                 status = "disabled";
 304         };
 305
 306         uart1: serial@11020000 {
 307                 compatible = "snps,dw-apb-uart";
 308                 reg = <0x11020000 0x100>;
 309                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 310                 clock-frequency = <24000000>;
 311                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 312                 clock-names = "baudclk", "apb_pclk";
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&uart1_xfer>;
 315                 reg-shift = <2>;
 316                 reg-io-width = <4>;
 317                 status = "disabled";
 318         };
 319
 320         uart2: serial@11030000 {
 321                 compatible = "snps,dw-apb-uart";
 322                 reg = <0x11030000 0x100>;
 323                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 324                 clock-frequency = <24000000>;
 325                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 326                 clock-names = "baudclk", "apb_pclk";
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&uart21_xfer>;
 329                 reg-shift = <2>;
 330                 reg-io-width = <4>;
 331                 status = "disabled";
 332         };
 333
 334         efuse: efuse@11040000 {
 335                 compatible = "rockchip,rk322x-efuse";
 336                 reg = <0x11040000 0x20>;
 337                 #address-cells = <1>;
 338                 #size-cells = <1>;
 339                 clocks = <&cru PCLK_EFUSE_256>;
 340                 clock-names = "pclk_efuse";
 341
 342                 /* Data cells */
 343                 efuse_id: id@7 {
 344                         reg = <0x7 0x10>;
 345                 };
 346                 cpu_leakage: cpu_leakage@17 {
 347                         reg = <0x17 0x1>;
 348                 };
 349         };
 350
 351         i2c0: i2c@11050000 {
 352                 compatible = "rockchip,rk3228-i2c";
 353                 reg = <0x11050000 0x1000>;
 354                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 clock-names = "i2c";
 358                 clocks = <&cru PCLK_I2C0>;
 359                 pinctrl-names = "default";
 360                 pinctrl-0 = <&i2c0_xfer>;
 361                 status = "disabled";
 362         };
 363
 364         i2c1: i2c@11060000 {
 365                 compatible = "rockchip,rk3228-i2c";
 366                 reg = <0x11060000 0x1000>;
 367                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 clock-names = "i2c";
 371                 clocks = <&cru PCLK_I2C1>;
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&i2c1_xfer>;
 374                 status = "disabled";
 375         };
 376
 377         i2c2: i2c@11070000 {
 378                 compatible = "rockchip,rk3228-i2c";
 379                 reg = <0x11070000 0x1000>;
 380                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 clock-names = "i2c";
 384                 clocks = <&cru PCLK_I2C2>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&i2c2_xfer>;
 387                 status = "disabled";
 388         };
 389
 390         i2c3: i2c@11080000 {
 391                 compatible = "rockchip,rk3228-i2c";
 392                 reg = <0x11080000 0x1000>;
 393                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 clock-names = "i2c";
 397                 clocks = <&cru PCLK_I2C3>;
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&i2c3_xfer>;
 400                 status = "disabled";
 401         };
 402
 403         wdt: watchdog@110a0000 {
 404                 compatible = "rockchip,rk322x-wdt", "snps,dw-wdt";
 405                 reg = <0x110a0000 0x100>;
 406                 clocks = <&cru PCLK_CPU>;
 407                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 408                 status = "disabled";
 409         };
 410
 411         pwm0: pwm@110b0000 {
 412                 compatible = "rockchip,rk3288-pwm";
 413                 reg = <0x110b0000 0x10>;
 414                 #pwm-cells = <3>;
 415                 clocks = <&cru PCLK_PWM>;
 416                 clock-names = "pwm";
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&pwm0_pin>;
 419                 status = "disabled";
 420         };
 421
 422         pwm1: pwm@110b0010 {
 423                 compatible = "rockchip,rk3288-pwm";
 424                 reg = <0x110b0010 0x10>;
 425                 #pwm-cells = <3>;
 426                 clocks = <&cru PCLK_PWM>;
 427                 clock-names = "pwm";
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&pwm1_pin>;
 430                 status = "disabled";
 431         };
 432
 433         pwm2: pwm@110b0020 {
 434                 compatible = "rockchip,rk3288-pwm";
 435                 reg = <0x110b0020 0x10>;
 436                 #pwm-cells = <3>;
 437                 clocks = <&cru PCLK_PWM>;
 438                 clock-names = "pwm";
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&pwm2_pin>;
 441                 status = "disabled";
 442         };
 443
 444         pwm3: pwm@110b0030 {
 445                 compatible = "rockchip,rk3288-pwm";
 446                 reg = <0x110b0030 0x10>;
 447                 #pwm-cells = <2>;
 448                 clocks = <&cru PCLK_PWM>;
 449                 clock-names = "pwm";
 450                 pinctrl-names = "default";
 451                 pinctrl-0 = <&pwm3_pin>;
 452                 status = "disabled";
 453         };
 454
 455         timer: timer@110c0000 {
 456                 compatible = "rockchip,rk3288-timer";
 457                 reg = <0x110c0000 0x20>;
 458                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 459                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 460                 clock-names = "timer", "pclk";
 461         };
 462
 463         cru: clock-controller@110e0000 {
 464                 compatible = "rockchip,rk3228-cru";
 465                 reg = <0x110e0000 0x1000>;
 466                 rockchip,grf = <&grf>;
 467                 #clock-cells = <1>;
 468                 #reset-cells = <1>;
 469                 assigned-clocks =
 470                         <&cru PLL_GPLL>, <&cru ARMCLK>,
 471                         <&cru PLL_CPLL>, <&cru ACLK_PERI>,
 472                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 473                         <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 474                         <&cru PCLK_CPU>;
 475                 assigned-clock-rates =
 476                         <594000000>, <816000000>,
 477                         <500000000>, <150000000>,
 478                         <150000000>, <75000000>,
 479                         <150000000>, <150000000>,
 480                         <75000000>;
 481         };
 482
 483         thermal-zones {
 484                 cpu_thermal: cpu-thermal {
 485                         polling-delay-passive = <100>; /* milliseconds */
 486                         polling-delay = <5000>; /* milliseconds */
 487
 488                         thermal-sensors = <&tsadc 0>;
 489
 490                         trips {
 491                                 cpu_alert0: cpu_alert0 {
 492                                         temperature = <70000>; /* millicelsius */
 493                                         hysteresis = <2000>; /* millicelsius */
 494                                         type = "passive";
 495                                 };
 496                                 cpu_alert1: cpu_alert1 {
 497                                         temperature = <75000>; /* millicelsius */
 498                                         hysteresis = <2000>; /* millicelsius */
 499                                         type = "passive";
 500                                 };
 501                                 cpu_crit: cpu_crit {
 502                                         temperature = <90000>; /* millicelsius */
 503                                         hysteresis = <2000>; /* millicelsius */
 504                                         type = "critical";
 505                                 };
 506                         };
 507
 508                         cooling-maps {
 509                                 map0 {
 510                                         trip = <&cpu_alert0>;
 511                                         cooling-device =
 512                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 513                                 };
 514                                 map1 {
 515                                         trip = <&cpu_alert1>;
 516                                         cooling-device =
 517                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 518                                 };
 519                         };
 520                 };
 521         };
 522
 523         tsadc: tsadc@11150000 {
 524                 compatible = "rockchip,rk3228-tsadc";
 525                 reg = <0x11150000 0x100>;
 526                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 527                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 528                 clock-names = "tsadc", "apb_pclk";
 529                 assigned-clocks = <&cru SCLK_TSADC>;
 530                 assigned-clock-rates = <32768>;
 531                 resets = <&cru SRST_TSADC>;
 532                 reset-names = "tsadc-apb";
 533                 pinctrl-names = "init", "default", "sleep";
 534                 pinctrl-0 = <&otp_gpio>;
 535                 pinctrl-1 = <&otp_out>;
 536                 pinctrl-2 = <&otp_gpio>;
 537                 #thermal-sensor-cells = <0>;
 538                 rockchip,hw-tshut-temp = <95000>;
 539                 status = "disabled";
 540         };
 541
 542         gpu: gpu@0x20001000 {
 543                 compatible = "arm,mali400";
 544                 reg = <0x20001000 0x200>,
 545                       <0x20000000 0x100>,
 546                       <0x20003000 0x100>,
 547                       <0x20008000 0x1100>,
 548                       <0x20004000 0x100>,
 549                       <0x2000A000 0x1100>,
 550                       <0x20005000 0x100>;
 551
 552                 reg-names = "Mali_L2",
 553                             "Mali_GP",
 554                             "Mali_GP_MMU",
 555                             "Mali_PP0",
 556                             "Mali_PP0_MMU",
 557                             "Mali_PP1",
 558                             "Mali_PP1_MMU";
 559
 560                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 561                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 562                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 563                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 564                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 565                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 566
 567                 interrupt-names = "Mali_GP_IRQ",
 568                                   "Mali_GP_MMU_IRQ",
 569                                   "Mali_PP0_IRQ",
 570                                   "Mali_PP0_MMU_IRQ",
 571                                   "Mali_PP1_IRQ",
 572                                   "Mali_PP1_MMU_IRQ";
 573                 clocks = <&cru ACLK_GPU>;
 574                 clock-names = "clk_mali";
 575                 operating-points-v2 = <&gpu_opp_table>;
 576                 status = "disabled";
 577         };
 578
 579         gpu_opp_table: opp-table2 {
 580                 compatible = "operating-points-v2";
 581
 582                 opp-200000000 {
 583                         opp-hz = /bits/ 64 <200000000>;
 584                         opp-microvolt = <1050000>;
 585                 };
 586                 opp-300000000 {
 587                         opp-hz = /bits/ 64 <300000000>;
 588                         opp-microvolt = <1050000>;
 589                 };
 590                 opp-500000000 {
 591                         opp-hz = /bits/ 64 <500000000>;
 592                         opp-microvolt = <1150000>;
 593                 };
 594         };
 595
 596         vop: vop@20050000 {
 597                 compatible = "rockchip,rk322x-vop";
 598                 reg = <0x20050000 0x1ffc>, <0x20052000 0x1000>;
 599                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 600                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
 601                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 602                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 603                 reset-names = "axi", "ahb", "dclk";
 604                 iommus = <&vop_mmu>;
 605                 status = "disabled";
 606
 607                 vop_out: port {
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610                 };
 611         };
 612
 613         vop_mmu: iommu@20050300 {
 614                 compatible = "rockchip,iommu";
 615                 reg = <0x20053f00 0x100>;
 616                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 617                 interrupt-names = "vop_mmu";
 618                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 619                 clock-names = "aclk", "hclk";
 620                 #iommu-cells = <0>;
 621                 status = "disabled";
 622         };
 623
 624         display-subsystem {
 625                 compatible = "rockchip,display-subsystem";
 626                 ports = <&vop_out>;
 627         };
 628
 629         sdmmc: dwmmc@30000000 {
 630                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 631                 reg = <0x30000000 0x4000>;
 632                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 633                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 634                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 635                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 636                 fifo-depth = <0x100>;
 637                 pinctrl-names = "default";
 638                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
 639                 status = "disabled";
 640         };
 641
 642         sdio: dwmmc@30010000 {
 643                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 644                 reg = <0x30010000 0x4000>;
 645                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 646                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 647                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 648                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 649                 fifo-depth = <0x100>;
 650                 pinctrl-names = "default";
 651                 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
 652                 status = "disabled";
 653         };
 654
 655         emmc: dwmmc@30020000 {
 656                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 657                 reg = <0x30020000 0x4000>;
 658                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 659                 clock-frequency = <37500000>;
 660                 clock-freq-min-max = <400000 37500000>;
 661                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 662                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 663                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 664                 bus-width = <8>;
 665                 default-sample-phase = <158>;
 666                 num-slots = <1>;
 667                 fifo-depth = <0x100>;
 668                 pinctrl-names = "default";
 669                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 670                 status = "disabled";
 671         };
 672
 673         usb_otg: usb@30040000 {
 674                 compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",
 675                              "snps,dwc2";
 676                 reg = <0x30040000 0x40000>;
 677                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 678                 clocks = <&cru HCLK_OTG>;
 679                 clock-names = "otg";
 680                 dr_mode = "otg";
 681                 g-np-tx-fifo-size = <16>;
 682                 g-rx-fifo-size = <275>;
 683                 g-tx-fifo-size = <256 128 128 64 64 32>;
 684                 g-use-dma;
 685                 phys = <&u2phy0_otg>;
 686                 phy-names = "usb2-phy";
 687                 status = "disabled";
 688         };
 689
 690         usb_host0_ehci: usb@30080000 {
 691                 compatible = "generic-ehci";
 692                 reg = <0x30080000 0x20000>;
 693                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 694                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
 695                 clock-names = "usbhost", "utmi";
 696                 phys = <&u2phy0_host>;
 697                 phy-names = "usb";
 698                 status = "disabled";
 699         };
 700
 701         usb_host0_ohci: usb@300a0000 {
 702                 compatible = "generic-ohci";
 703                 reg = <0x300a0000 0x20000>;
 704                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 705                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
 706                 clock-names = "usbhost", "utmi";
 707                 phys = <&u2phy0_host>;
 708                 phy-names = "usb";
 709                 status = "disabled";
 710         };
 711
 712         usb_host1_ehci: usb@300c0000 {
 713                 compatible = "generic-ehci";
 714                 reg = <0x300c0000 0x20000>;
 715                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 716                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
 717                 clock-names = "usbhost", "utmi";
 718                 phys = <&u2phy1_host>;
 719                 phy-names = "usb";
 720                 status = "disabled";
 721         };
 722
 723         usb_host1_ohci: usb@300e0000 {
 724                 compatible = "generic-ohci";
 725                 reg = <0x300e0000 0x20000>;
 726                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 727                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
 728                 clock-names = "usbhost", "utmi";
 729                 phys = <&u2phy1_host>;
 730                 phy-names = "usb";
 731                 status = "disabled";
 732         };
 733
 734         usb_host2_ehci: usb@30100000 {
 735                 compatible = "generic-ehci";
 736                 reg = <0x30100000 0x20000>;
 737                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 738                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 739                 phys = <&u2phy1_otg>;
 740                 phy-names = "usb";
 741                 clock-names = "usbhost", "utmi";
 742                 status = "disabled";
 743         };
 744
 745         usb_host2_ohci: usb@30120000 {
 746                 compatible = "generic-ohci";
 747                 reg = <0x30120000 0x20000>;
 748                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 749                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 750                 clock-names = "usbhost", "utmi";
 751                 phys = <&u2phy1_otg>;
 752                 phy-names = "usb";
 753                 status = "disabled";
 754         };
 755
 756         gmac: ethernet@30200000 {
 757                 compatible = "rockchip,rk3228-gmac";
 758                 reg = <0x30200000 0x10000>;
 759                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 760                 interrupt-names = "macirq";
 761                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 762                         <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
 763                         <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 764                         <&cru PCLK_GMAC>;
 765                 clock-names = "stmmaceth", "mac_clk_rx",
 766                         "mac_clk_tx", "clk_mac_ref",
 767                         "clk_mac_refout", "aclk_mac",
 768                         "pclk_mac";
 769                 resets = <&cru SRST_GMAC>;
 770                 reset-names = "stmmaceth";
 771                 rockchip,grf = <&grf>;
 772                 status = "disabled";
 773         };
 774
 775         gic: interrupt-controller@32010000 {
 776                 compatible = "arm,gic-400";
 777                 interrupt-controller;
 778                 #interrupt-cells = <3>;
 779                 #address-cells = <0>;
 780
 781                 reg = <0x32011000 0x1000>,
 782                       <0x32012000 0x2000>,
 783                       <0x32014000 0x2000>,
 784                       <0x32016000 0x2000>;
 785                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 786         };
 787
 788         pinctrl: pinctrl {
 789                 compatible = "rockchip,rk3228-pinctrl";
 790                 rockchip,grf = <&grf>;
 791                 #address-cells = <1>;
 792                 #size-cells = <1>;
 793                 ranges;
 794
 795                 gpio0: gpio0@11110000 {
 796                         compatible = "rockchip,gpio-bank";
 797                         reg = <0x11110000 0x100>;
 798                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 799                         clocks = <&cru PCLK_GPIO0>;
 800
 801                         gpio-controller;
 802                         #gpio-cells = <2>;
 803
 804                         interrupt-controller;
 805                         #interrupt-cells = <2>;
 806                 };
 807
 808                 gpio1: gpio1@11120000 {
 809                         compatible = "rockchip,gpio-bank";
 810                         reg = <0x11120000 0x100>;
 811                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 812                         clocks = <&cru PCLK_GPIO1>;
 813
 814                         gpio-controller;
 815                         #gpio-cells = <2>;
 816
 817                         interrupt-controller;
 818                         #interrupt-cells = <2>;
 819                 };
 820
 821                 gpio2: gpio2@11130000 {
 822                         compatible = "rockchip,gpio-bank";
 823                         reg = <0x11130000 0x100>;
 824                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 825                         clocks = <&cru PCLK_GPIO2>;
 826
 827                         gpio-controller;
 828                         #gpio-cells = <2>;
 829
 830                         interrupt-controller;
 831                         #interrupt-cells = <2>;
 832                 };
 833
 834                 gpio3: gpio3@11140000 {
 835                         compatible = "rockchip,gpio-bank";
 836                         reg = <0x11140000 0x100>;
 837                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 838                         clocks = <&cru PCLK_GPIO3>;
 839
 840                         gpio-controller;
 841                         #gpio-cells = <2>;
 842
 843                         interrupt-controller;
 844                         #interrupt-cells = <2>;
 845                 };
 846
 847                 pcfg_pull_up: pcfg-pull-up {
 848                         bias-pull-up;
 849                 };
 850
 851                 pcfg_pull_down: pcfg-pull-down {
 852                         bias-pull-down;
 853                 };
 854
 855                 pcfg_pull_none: pcfg-pull-none {
 856                         bias-disable;
 857                 };
 858
 859                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 860                         drive-strength = <12>;
 861                 };
 862
 863                 sdmmc {
 864                         sdmmc_clk: sdmmc-clk {
 865                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 866                         };
 867
 868                         sdmmc_cmd: sdmmc-cmd {
 869                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 870                         };
 871
 872                         sdmmc_bus4: sdmmc-bus4 {
 873                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 874                                                 <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 875                                                 <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 876                                                 <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 877                         };
 878                 };
 879
 880                 sdio {
 881                         sdio_clk: sdio-clk {
 882                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 883                         };
 884
 885                         sdio_cmd: sdio-cmd {
 886                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 887                         };
 888
 889                         sdio_bus4: sdio-bus4 {
 890                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 891                                                 <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 892                                                 <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 893                                                 <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 894                         };
 895                 };
 896
 897                 emmc {
 898                         emmc_clk: emmc-clk {
 899                                 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
 900                         };
 901
 902                         emmc_cmd: emmc-cmd {
 903                                 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
 904                         };
 905
 906                         emmc_bus8: emmc-bus8 {
 907                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
 908                                                 <1 25 RK_FUNC_2 &pcfg_pull_none>,
 909                                                 <1 26 RK_FUNC_2 &pcfg_pull_none>,
 910                                                 <1 27 RK_FUNC_2 &pcfg_pull_none>,
 911                                                 <1 28 RK_FUNC_2 &pcfg_pull_none>,
 912                                                 <1 29 RK_FUNC_2 &pcfg_pull_none>,
 913                                                 <1 30 RK_FUNC_2 &pcfg_pull_none>,
 914                                                 <1 31 RK_FUNC_2 &pcfg_pull_none>;
 915                         };
 916                 };
 917
 918                 gmac {
 919                         rgmii_pins: rgmii-pins {
 920                                 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
 921                                                 <2 12 RK_FUNC_1 &pcfg_pull_none>,
 922                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>,
 923                                                 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 924                                                 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 925                                                 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 926                                                 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 927                                                 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 928                                                 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 929                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 930                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 931                                                 <2 21 RK_FUNC_2 &pcfg_pull_none>,
 932                                                 <2 20 RK_FUNC_2 &pcfg_pull_none>,
 933                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>,
 934                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>;
 935                         };
 936
 937                         rmii_pins: rmii-pins {
 938                                 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
 939                                                 <2 12 RK_FUNC_1 &pcfg_pull_none>,
 940                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>,
 941                                                 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 942                                                 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 943                                                 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 944                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 945                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 946                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
 947                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>;
 948                         };
 949
 950                         phy_pins: phy-pins {
 951                                 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
 952                                                 <2 8 RK_FUNC_2 &pcfg_pull_none>;
 953                         };
 954                 };
 955
 956                 i2c0 {
 957                         i2c0_xfer: i2c0-xfer {
 958                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 959                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 960                         };
 961                 };
 962
 963                 i2c1 {
 964                         i2c1_xfer: i2c1-xfer {
 965                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 966                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 967                         };
 968                 };
 969
 970                 i2c2 {
 971                         i2c2_xfer: i2c2-xfer {
 972                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 973                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 974                         };
 975                 };
 976
 977                 i2c3 {
 978                         i2c3_xfer: i2c3-xfer {
 979                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 980                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 981                         };
 982                 };
 983
 984                 i2s1 {
 985                         i2s1_bus: i2s1-bus {
 986                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
 987                                                 <0 9 RK_FUNC_1 &pcfg_pull_none>,
 988                                                 <0 11 RK_FUNC_1 &pcfg_pull_none>,
 989                                                 <0 12 RK_FUNC_1 &pcfg_pull_none>,
 990                                                 <0 13 RK_FUNC_1 &pcfg_pull_none>,
 991                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,
 992                                                 <1 2 RK_FUNC_2 &pcfg_pull_none>,
 993                                                 <1 4 RK_FUNC_2 &pcfg_pull_none>,
 994                                                 <1 5 RK_FUNC_2 &pcfg_pull_none>;
 995                         };
 996                 };
 997
 998                 pwm0 {
 999                         pwm0_pin: pwm0-pin {
1000                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
1001                         };
1002                 };
1003
1004                 pwm1 {
1005                         pwm1_pin: pwm1-pin {
1006                                 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
1007                         };
1008                 };
1009
1010                 pwm2 {
1011                         pwm2_pin: pwm2-pin {
1012                                 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
1013                         };
1014                 };
1015
1016                 pwm3 {
1017                         pwm3_pin: pwm3-pin {
1018                                 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
1019                         };
1020                 };
1021
1022                 spdif {
1023                         spdif_tx: spdif-tx {
1024                                 rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;
1025                         };
1026                 };
1027
1028                 tsadc {
1029                         otp_gpio: otp-gpio {
1030                                 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
1031                         };
1032
1033                         otp_out: otp-out {
1034                                 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
1035                         };
1036                 };
1037
1038                 uart0 {
1039                         uart0_xfer: uart0-xfer {
1040                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
1041                                                 <2 27 RK_FUNC_1 &pcfg_pull_none>;
1042                         };
1043
1044                         uart0_cts: uart0-cts {
1045                                 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
1046                         };
1047
1048                         uart0_rts: uart0-rts {
1049                                 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
1050                         };
1051                 };
1052
1053                 uart1 {
1054                         uart1_xfer: uart1-xfer {
1055                                 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
1056                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>;
1057                         };
1058
1059                         uart1_cts: uart1-cts {
1060                                 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
1061                         };
1062
1063                         uart1_rts: uart1-rts {
1064                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
1065                         };
1066                 };
1067
1068                 uart2 {
1069                         uart2_xfer: uart2-xfer {
1070                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1071                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
1072                         };
1073
1074                         uart2_cts: uart2-cts {
1075                                 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
1076                         };
1077
1078                         uart2_rts: uart2-rts {
1079                                 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
1080                         };
1081                 };
1082
1083                 uart2-1 {
1084                         uart21_xfer: uart21-xfer {
1085                                 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
1086                                                 <1 9 RK_FUNC_2 &pcfg_pull_none>;
1087                         };
1088                 };
1089         };
1090
1091         rockchip_suspend: rockchip-suspend {
1092                 compatible = "rockchip,pm-rk322x";
1093                 status = "disabled";
1094                 rockchip,sleep-mode-config = <
1095                         (0
1096                         |RKPM_CTR_GTCLKS
1097                         |RKPM_CTR_IDLESRAM_MD
1098                         )
1099                 >;
1100         };
1101 };