arch/arm/boot/dts/rk322x.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3228-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include "skeleton.dtsi"
  48
  49 / {
  50         interrupt-parent = <&gic>;
  51
  52         aliases {
  53                 serial0 = &uart0;
  54                 serial1 = &uart1;
  55                 serial2 = &uart2;
  56         };
  57
  58         cpus {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 cpu0: cpu@f00 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a7";
  65                         reg = <0xf00>;
  66                         resets = <&cru SRST_CORE0>;
  67                         operating-points = <
  68                                 /* KHz    uV */
  69                                  816000 1000000
  70                         >;
  71                         #cooling-cells = <2>; /* min followed by max */
  72                         clock-latency = <40000>;
  73                         clocks = <&cru ARMCLK>;
  74                 };
  75
  76                 cpu1: cpu@f01 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a7";
  79                         reg = <0xf01>;
  80                         resets = <&cru SRST_CORE1>;
  81                 };
  82
  83                 cpu2: cpu@f02 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a7";
  86                         reg = <0xf02>;
  87                         resets = <&cru SRST_CORE2>;
  88                 };
  89
  90                 cpu3: cpu@f03 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0xf03>;
  94                         resets = <&cru SRST_CORE3>;
  95                 };
  96         };
  97
  98         amba {
  99                 compatible = "arm,amba-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 pdma: pdma@110f0000 {
 105                         compatible = "arm,pl330", "arm,primecell";
 106                         reg = <0x110f0000 0x4000>;
 107                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 108                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 109                         #dma-cells = <1>;
 110                         clocks = <&cru ACLK_DMAC>;
 111                         clock-names = "apb_pclk";
 112                 };
 113         };
 114
 115         arm-pmu {
 116                 compatible = "arm,cortex-a7-pmu";
 117                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 119                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 120                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 121                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 122         };
 123
 124         timer {
 125                 compatible = "arm,armv7-timer";
 126                 arm,cpu-registers-not-fw-configured;
 127                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 128                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 129                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 130                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 131                 clock-frequency = <24000000>;
 132         };
 133
 134         xin24m: oscillator {
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <24000000>;
 137                 clock-output-names = "xin24m";
 138                 #clock-cells = <0>;
 139         };
 140
 141         grf: syscon@11000000 {
 142                 compatible = "syscon";
 143                 reg = <0x11000000 0x1000>;
 144         };
 145
 146         uart0: serial@11010000 {
 147                 compatible = "snps,dw-apb-uart";
 148                 reg = <0x11010000 0x100>;
 149                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 150                 clock-frequency = <24000000>;
 151                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 152                 clock-names = "baudclk", "apb_pclk";
 153                 pinctrl-names = "default";
 154                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 155                 reg-shift = <2>;
 156                 reg-io-width = <4>;
 157                 status = "disabled";
 158         };
 159
 160         uart1: serial@11020000 {
 161                 compatible = "snps,dw-apb-uart";
 162                 reg = <0x11020000 0x100>;
 163                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 164                 clock-frequency = <24000000>;
 165                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 166                 clock-names = "baudclk", "apb_pclk";
 167                 pinctrl-names = "default";
 168                 pinctrl-0 = <&uart1_xfer>;
 169                 reg-shift = <2>;
 170                 reg-io-width = <4>;
 171                 status = "disabled";
 172         };
 173
 174         uart2: serial@11030000 {
 175                 compatible = "snps,dw-apb-uart";
 176                 reg = <0x11030000 0x100>;
 177                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 178                 clock-frequency = <24000000>;
 179                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 180                 clock-names = "baudclk", "apb_pclk";
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&uart2_xfer>;
 183                 reg-shift = <2>;
 184                 reg-io-width = <4>;
 185                 status = "disabled";
 186         };
 187
 188         i2c0: i2c@11050000 {
 189                 compatible = "rockchip,rk3228-i2c";
 190                 reg = <0x11050000 0x1000>;
 191                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 192                 #address-cells = <1>;
 193                 #size-cells = <0>;
 194                 clock-names = "i2c";
 195                 clocks = <&cru PCLK_I2C0>;
 196                 pinctrl-names = "default";
 197                 pinctrl-0 = <&i2c0_xfer>;
 198                 status = "disabled";
 199         };
 200
 201         i2c1: i2c@11060000 {
 202                 compatible = "rockchip,rk3228-i2c";
 203                 reg = <0x11060000 0x1000>;
 204                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 205                 #address-cells = <1>;
 206                 #size-cells = <0>;
 207                 clock-names = "i2c";
 208                 clocks = <&cru PCLK_I2C1>;
 209                 pinctrl-names = "default";
 210                 pinctrl-0 = <&i2c1_xfer>;
 211                 status = "disabled";
 212         };
 213
 214         i2c2: i2c@11070000 {
 215                 compatible = "rockchip,rk3228-i2c";
 216                 reg = <0x11070000 0x1000>;
 217                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220                 clock-names = "i2c";
 221                 clocks = <&cru PCLK_I2C2>;
 222                 pinctrl-names = "default";
 223                 pinctrl-0 = <&i2c2_xfer>;
 224                 status = "disabled";
 225         };
 226
 227         i2c3: i2c@11080000 {
 228                 compatible = "rockchip,rk3228-i2c";
 229                 reg = <0x11080000 0x1000>;
 230                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 231                 #address-cells = <1>;
 232                 #size-cells = <0>;
 233                 clock-names = "i2c";
 234                 clocks = <&cru PCLK_I2C3>;
 235                 pinctrl-names = "default";
 236                 pinctrl-0 = <&i2c3_xfer>;
 237                 status = "disabled";
 238         };
 239
 240         pwm0: pwm@110b0000 {
 241                 compatible = "rockchip,rk3288-pwm";
 242                 reg = <0x110b0000 0x10>;
 243                 #pwm-cells = <3>;
 244                 clocks = <&cru PCLK_PWM>;
 245                 clock-names = "pwm";
 246                 pinctrl-names = "default";
 247                 pinctrl-0 = <&pwm0_pin>;
 248                 status = "disabled";
 249         };
 250
 251         pwm1: pwm@110b0010 {
 252                 compatible = "rockchip,rk3288-pwm";
 253                 reg = <0x110b0010 0x10>;
 254                 #pwm-cells = <3>;
 255                 clocks = <&cru PCLK_PWM>;
 256                 clock-names = "pwm";
 257                 pinctrl-names = "default";
 258                 pinctrl-0 = <&pwm1_pin>;
 259                 status = "disabled";
 260         };
 261
 262         pwm2: pwm@110b0020 {
 263                 compatible = "rockchip,rk3288-pwm";
 264                 reg = <0x110b0020 0x10>;
 265                 #pwm-cells = <3>;
 266                 clocks = <&cru PCLK_PWM>;
 267                 clock-names = "pwm";
 268                 pinctrl-names = "default";
 269                 pinctrl-0 = <&pwm2_pin>;
 270                 status = "disabled";
 271         };
 272
 273         pwm3: pwm@110b0030 {
 274                 compatible = "rockchip,rk3288-pwm";
 275                 reg = <0x110b0030 0x10>;
 276                 #pwm-cells = <2>;
 277                 clocks = <&cru PCLK_PWM>;
 278                 clock-names = "pwm";
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&pwm3_pin>;
 281                 status = "disabled";
 282         };
 283
 284         timer: timer@110c0000 {
 285                 compatible = "rockchip,rk3288-timer";
 286                 reg = <0x110c0000 0x20>;
 287                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 289                 clock-names = "timer", "pclk";
 290         };
 291
 292         cru: clock-controller@110e0000 {
 293                 compatible = "rockchip,rk3228-cru";
 294                 reg = <0x110e0000 0x1000>;
 295                 rockchip,grf = <&grf>;
 296                 #clock-cells = <1>;
 297                 #reset-cells = <1>;
 298                 assigned-clocks = <&cru PLL_GPLL>;
 299                 assigned-clock-rates = <594000000>;
 300         };
 301
 302         thermal-zones {
 303                 cpu_thermal: cpu-thermal {
 304                         polling-delay-passive = <100>; /* milliseconds */
 305                         polling-delay = <5000>; /* milliseconds */
 306
 307                         thermal-sensors = <&tsadc 0>;
 308
 309                         trips {
 310                                 cpu_alert0: cpu_alert0 {
 311                                         temperature = <70000>; /* millicelsius */
 312                                         hysteresis = <2000>; /* millicelsius */
 313                                         type = "passive";
 314                                 };
 315                                 cpu_alert1: cpu_alert1 {
 316                                         temperature = <75000>; /* millicelsius */
 317                                         hysteresis = <2000>; /* millicelsius */
 318                                         type = "passive";
 319                                 };
 320                                 cpu_crit: cpu_crit {
 321                                         temperature = <90000>; /* millicelsius */
 322                                         hysteresis = <2000>; /* millicelsius */
 323                                         type = "critical";
 324                                 };
 325                         };
 326
 327                         cooling-maps {
 328                                 map0 {
 329                                         trip = <&cpu_alert0>;
 330                                         cooling-device =
 331                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 332                                 };
 333                                 map1 {
 334                                         trip = <&cpu_alert1>;
 335                                         cooling-device =
 336                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 337                                 };
 338                         };
 339                 };
 340         };
 341
 342         tsadc: tsadc@11150000 {
 343                 compatible = "rockchip,rk3228-tsadc";
 344                 reg = <0x11150000 0x100>;
 345                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 346                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 347                 clock-names = "tsadc", "apb_pclk";
 348                 resets = <&cru SRST_TSADC>;
 349                 reset-names = "tsadc-apb";
 350                 pinctrl-names = "init", "default", "sleep";
 351                 pinctrl-0 = <&otp_gpio>;
 352                 pinctrl-1 = <&otp_out>;
 353                 pinctrl-2 = <&otp_gpio>;
 354                 #thermal-sensor-cells = <0>;
 355                 rockchip,hw-tshut-temp = <95000>;
 356                 status = "disabled";
 357         };
 358
 359         emmc: dwmmc@30020000 {
 360                 compatible = "rockchip,rk3288-dw-mshc";
 361                 reg = <0x30020000 0x4000>;
 362                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 363                 clock-frequency = <37500000>;
 364                 clock-freq-min-max = <400000 37500000>;
 365                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 366                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 367                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 368                 bus-width = <8>;
 369                 default-sample-phase = <158>;
 370                 num-slots = <1>;
 371                 fifo-depth = <0x100>;
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 374                 status = "disabled";
 375         };
 376
 377         gic: interrupt-controller@32010000 {
 378                 compatible = "arm,gic-400";
 379                 interrupt-controller;
 380                 #interrupt-cells = <3>;
 381                 #address-cells = <0>;
 382
 383                 reg = <0x32011000 0x1000>,
 384                       <0x32012000 0x1000>,
 385                       <0x32014000 0x2000>,
 386                       <0x32016000 0x2000>;
 387                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 388         };
 389
 390         pinctrl: pinctrl {
 391                 compatible = "rockchip,rk3228-pinctrl";
 392                 rockchip,grf = <&grf>;
 393                 #address-cells = <1>;
 394                 #size-cells = <1>;
 395                 ranges;
 396
 397                 gpio0: gpio0@11110000 {
 398                         compatible = "rockchip,gpio-bank";
 399                         reg = <0x11110000 0x100>;
 400                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 401                         clocks = <&cru PCLK_GPIO0>;
 402
 403                         gpio-controller;
 404                         #gpio-cells = <2>;
 405
 406                         interrupt-controller;
 407                         #interrupt-cells = <2>;
 408                 };
 409
 410                 gpio1: gpio1@11120000 {
 411                         compatible = "rockchip,gpio-bank";
 412                         reg = <0x11120000 0x100>;
 413                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&cru PCLK_GPIO1>;
 415
 416                         gpio-controller;
 417                         #gpio-cells = <2>;
 418
 419                         interrupt-controller;
 420                         #interrupt-cells = <2>;
 421                 };
 422
 423                 gpio2: gpio2@11130000 {
 424                         compatible = "rockchip,gpio-bank";
 425                         reg = <0x11130000 0x100>;
 426                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 427                         clocks = <&cru PCLK_GPIO2>;
 428
 429                         gpio-controller;
 430                         #gpio-cells = <2>;
 431
 432                         interrupt-controller;
 433                         #interrupt-cells = <2>;
 434                 };
 435
 436                 gpio3: gpio3@11140000 {
 437                         compatible = "rockchip,gpio-bank";
 438                         reg = <0x11140000 0x100>;
 439                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 440                         clocks = <&cru PCLK_GPIO3>;
 441
 442                         gpio-controller;
 443                         #gpio-cells = <2>;
 444
 445                         interrupt-controller;
 446                         #interrupt-cells = <2>;
 447                 };
 448
 449                 pcfg_pull_up: pcfg-pull-up {
 450                         bias-pull-up;
 451                 };
 452
 453                 pcfg_pull_down: pcfg-pull-down {
 454                         bias-pull-down;
 455                 };
 456
 457                 pcfg_pull_none: pcfg-pull-none {
 458                         bias-disable;
 459                 };
 460
 461                 emmc {
 462                         emmc_clk: emmc-clk {
 463                                 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
 464                         };
 465
 466                         emmc_cmd: emmc-cmd {
 467                                 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
 468                         };
 469
 470                         emmc_bus8: emmc-bus8 {
 471                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
 472                                                 <1 25 RK_FUNC_2 &pcfg_pull_none>,
 473                                                 <1 26 RK_FUNC_2 &pcfg_pull_none>,
 474                                                 <1 27 RK_FUNC_2 &pcfg_pull_none>,
 475                                                 <1 28 RK_FUNC_2 &pcfg_pull_none>,
 476                                                 <1 29 RK_FUNC_2 &pcfg_pull_none>,
 477                                                 <1 30 RK_FUNC_2 &pcfg_pull_none>,
 478                                                 <1 31 RK_FUNC_2 &pcfg_pull_none>;
 479                         };
 480                 };
 481
 482                 i2c0 {
 483                         i2c0_xfer: i2c0-xfer {
 484                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 485                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 486                         };
 487                 };
 488
 489                 i2c1 {
 490                         i2c1_xfer: i2c1-xfer {
 491                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 492                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 493                         };
 494                 };
 495
 496                 i2c2 {
 497                         i2c2_xfer: i2c2-xfer {
 498                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 499                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 500                         };
 501                 };
 502
 503                 i2c3 {
 504                         i2c3_xfer: i2c3-xfer {
 505                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 506                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 507                         };
 508                 };
 509
 510                 pwm0 {
 511                         pwm0_pin: pwm0-pin {
 512                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
 513                         };
 514                 };
 515
 516                 pwm1 {
 517                         pwm1_pin: pwm1-pin {
 518                                 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
 519                         };
 520                 };
 521
 522                 pwm2 {
 523                         pwm2_pin: pwm2-pin {
 524                                 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
 525                         };
 526                 };
 527
 528                 pwm3 {
 529                         pwm3_pin: pwm3-pin {
 530                                 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
 531                         };
 532                 };
 533
 534                 tsadc {
 535                         otp_gpio: otp-gpio {
 536                                 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
 537                         };
 538
 539                         otp_out: otp-out {
 540                                 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
 541                         };
 542                 };
 543
 544                 uart0 {
 545                         uart0_xfer: uart0-xfer {
 546                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
 547                                                 <2 27 RK_FUNC_1 &pcfg_pull_none>;
 548                         };
 549
 550                         uart0_cts: uart0-cts {
 551                                 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
 552                         };
 553
 554                         uart0_rts: uart0-rts {
 555                                 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
 556                         };
 557                 };
 558
 559                 uart1 {
 560                         uart1_xfer: uart1-xfer {
 561                                 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
 562                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>;
 563                         };
 564
 565                         uart1_cts: uart1-cts {
 566                                 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
 567                         };
 568
 569                         uart1_rts: uart1-rts {
 570                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
 571                         };
 572                 };
 573
 574                 uart2 {
 575                         uart2_xfer: uart2-xfer {
 576                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
 577                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 578                         };
 579
 580                         uart2_cts: uart2-cts {
 581                                 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
 582                         };
 583
 584                         uart2_rts: uart2-rts {
 585                                 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
 586                         };
 587                 };
 588         };
 589 };