arch/arm/boot/dts/rk3228_dram_default_timing.dtsi

   1 /*
   2  * Copyright (C) 2014-2015 ROCKCHIP, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14 #include <dt-bindings/clock/ddr.h>
  15 #include <dt-bindings/dram/rockchip,rk3368.h>
  16
  17 / {
  18         dram_timing: dram_timing {
  19                 compatible = "rockchip,dram-timing";
  20                 dram_spd_bin = <DDR3_DEFAULT>;
  21                 sr_idle = <1>;
  22                 pd_idle = <0x20>;
  23                 dram_dll_disb_freq = <300>;
  24                 phy_dll_disb_freq = <400>;
  25                 dram_odt_disb_freq = <333>;
  26                 phy_odt_disb_freq = <333>;
  27                 ddr3_drv = <DDR3_DS_40ohm>;
  28                 ddr3_odt = <DDR3_ODT_120ohm>;
  29                 lpddr3_drv = <LP3_DS_34ohm>;
  30                 lpddr3_odt = <LP3_ODT_240ohm>;
  31                 lpddr2_drv = <LP2_DS_34ohm>;
  32                 /* lpddr2 not supported odt */
  33                 phy_clk_drv = <PHY_RON_45ohm>;
  34                 phy_cmd_drv = <PHY_RON_34ohm>;
  35                 phy_dqs_drv = <PHY_RON_34ohm>;
  36                 phy_odt = <PHY_RTT_279ohm>;
  37         };
  38 };