arch/arm/boot/dts/rk3228.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/rkfb/rk_fb.h>
   3
   4 #include "skeleton.dtsi"
   5 #include "rk3228-clocks.dtsi"
   6
   7 #include <dt-bindings/pinctrl/rockchip.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <rk3228_dram_default_timing.dtsi>
  10
  11 / {
  12         compatible = "rockchip,rk3228";
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 serial0 = &uart0;
  17                 serial1 = &uart1;
  18                 serial2 = &uart2;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a7";
  32                         reg = <0xf00>;
  33                 };
  34                 cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a7";
  37                         reg = <0xf01>;
  38                 };
  39                 cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a7";
  42                         reg = <0xf02>;
  43                 };
  44                 cpu@3 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a7";
  47                         reg = <0xf03>;
  48                 };
  49         };
  50
  51         psci {
  52                 compatible      = "arm,psci";
  53                 method          = "smc";
  54                 cpu_suspend     = <0x84000001>;
  55                 cpu_off         = <0x84000002>;
  56                 cpu_on          = <0x84000003>;
  57         };
  58
  59         gic: interrupt-controller@32010000 {
  60                 compatible = "arm,cortex-a15-gic";
  61                 interrupt-controller;
  62                 #interrupt-cells = <3>;
  63                 #address-cells = <0>;
  64                 reg = <0x32011000 0x1000>,
  65                       <0x32012000 0x1000>;
  66         };
  67
  68         sgrf: syscon@10140000 {
  69                 compatible = "rockchip,rk3228-sgrf", "rockchip,sgrf", "syscon";
  70                 reg = <0x10140000 0x1000>;
  71         };
  72
  73         grf: syscon@11000000 {
  74                 compatible = "rockchip,rk3228-grf", "rockchip,grf", "syscon";
  75                 reg = <0x11000000 0x1000>;
  76         };
  77
  78         cru: syscon@110e0000 {
  79                 compatible = "rockchip,rk3228-cru", "rockchip,cru", "syscon";
  80                 reg = <0x110e0000 0x1000>;
  81         };
  82
  83         ddrpctl: syscon@11200000 {
  84                 compatible = "rockchip,rk3228-ddrpctl", "syscon";
  85                 reg = <0x11200000 0x400>;
  86         };
  87
  88         msch: syscon@31020000 {
  89                 compatible = "rockchip,rk32288-msch", "rockchip,msch", "syscon";
  90                 reg = <0x31020000 0x3000>;
  91         };
  92
  93         arm-pmu {
  94                 compatible = "arm,cortex-a7-pmu";
  95                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  96                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  97                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  98                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  99         };
 100
 101         reset: reset@110e0110{
 102                 compatible = "rockchip,reset";
 103                 reg = <0x110e0110 0x20>;
 104                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 105                 #reset-cells = <1>;
 106         };
 107
 108         timer {
 109                 compatible = "arm,armv7-timer";
 110                 interrupts = <GIC_PPI 13
 111                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 112                              <GIC_PPI 14
 113                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 114                 clock-frequency = <24000000>;
 115         };
 116
 117         fiq-debugger {
 118                 compatible = "rockchip,fiq-debugger";
 119                 rockchip,serial-id = <2>;
 120                 rockchip,signal-irq = <159>;
 121                 rockchip,wake-irq = <0>;
 122                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
 123                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
 124                 status = "disabled";
 125         };
 126
 127         rockchip_ion: rockchip-ion {
 128                 compatible = "rockchip,ion";
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131
 132                 ion_cma: cma-heap {
 133                          compatible = "rockchip,ion-heap";
 134                          status = "disabled";
 135                          rockchip,ion_heap = <4>;
 136                          reg = <0x10000000 0x08000000>; /* 128 MB */
 137                 };
 138                 system_heap: system-heap {
 139                         compatible = "rockchip,ion-heap";
 140                         rockchip,ion_heap = <0>;
 141                 };
 142         };
 143
 144         dram: dram {
 145                 compatible = "rockchip,rk3228-dram";
 146                 status = "okay";
 147                 dram_freq = <600000000>;
 148                 rockchip,dram_timing = <&dram_timing>;
 149         };
 150
 151         rockchip_clocks_init: clocks-init{
 152                 compatible = "rockchip,clocks-init";
 153                 rockchip,clocks-init-parent =
 154                         <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
 155                         <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
 156                         <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
 157                         <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
 158                         <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
 159                         <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
 160                         <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
 161                 rockchip,clocks-init-rate =
 162                         <&clk_gpll 600000000>, <&clk_core 700000000>,
 163                         <&clk_cpll 500000000>, <&aclk_bus 250000000>,
 164                         <&hclk_bus 125000000>, <&pclk_bus 62500000>,
 165                         <&aclk_peri 250000000>, <&hclk_peri 125000000>,
 166                         <&pclk_peri 62500000>, <&clk_mac 125000000>,
 167                         <&aclk_iep 250000000>, <&hclk_vio 125000000>,
 168                         <&aclk_rga 250000000>, <&clk_gpu 250000000>,
 169                         <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
 170                         <&clk_vdec_cabac 250000000>;
 171 /*
 172                 rockchip,clocks-uboot-has-init =
 173                         <&aclk_vio0>;
 174 */
 175         };
 176
 177         rockchip_clocks_enable: clocks-enable {
 178                 compatible = "rockchip,clocks-enable";
 179                 clocks =
 180                         /*PLL*/
 181                         <&clk_apll>,
 182                         <&clk_dpll>,
 183                         <&clk_gpll>,
 184                         <&clk_cpll>,
 185
 186                         /*PD_CORE*/
 187                         <&clk_core>,
 188                         <&pclk_dbg>,
 189                         <&aclk_core>,
 190                         <&clk_gates4 2>,
 191
 192                         /*PD_BUS*/
 193                         <&aclk_bus>,
 194                         <&hclk_bus>,
 195                         <&pclk_bus>,
 196                         <&clk_gates8 0>,/*aclk_intmem*/
 197                         <&clk_gates8 1>,/*clk_intmem_mbist*/
 198                         <&clk_gates8 2>,/*aclk_dmac_bus*/
 199                         <&clk_gates10 1>,/*g_aclk_bus*/
 200                         <&clk_gates13 9>,/*aclk_gic400*/
 201                         <&clk_gates8 3>,/*hclk_rom*/
 202                         <&clk_gates8 4>,/*pclk_ddrupctl*/
 203                         <&clk_gates8 6>,/*pclk_ddrmon*/
 204                         <&clk_gates9 4>,/*pclk_timer0*/
 205                         <&clk_gates9 5>,/*pclk_stimer*/
 206                         <&clk_gates10 0>,/*pclk_grf*/
 207                         <&clk_gates10 4>,/*pclk_cru*/
 208                         <&clk_gates10 6>,/*pclk_sgrf*/
 209                         <&clk_gates10 3>,/*pclk_ddrphy*/
 210                         <&clk_gates10 9>,/*pclk_phy_noc*/
 211
 212                         /*PD_PERI*/
 213                         <&aclk_peri>,
 214                         <&hclk_peri>,
 215                         <&pclk_peri>,
 216                         <&clk_gates12 0>,/*aclk_peri_noc*/
 217                         <&clk_gates12 1>,/*hclk_peri_noc*/
 218                         <&clk_gates12 2>,/*pclk_peri_noc*/
 219
 220                         <&clk_gates6 5>, /* g_clk_timer0 */
 221                         <&clk_gates6 6>, /* g_clk_timer1 */
 222
 223                         <&clk_gates7 14>, /* g_aclk_gpu */
 224                         <&clk_gates7 15>, /* g_aclk_gpu_noc */
 225
 226                         <&clk_gates1 3>;/*clk_jtag*/
 227         };
 228
 229         uart0: serial@11010000 {
 230                 compatible = "rockchip,serial";
 231                 reg = <0x11010000 0x100>;
 232                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 233                 clock-frequency = <24000000>;
 234                 clocks = <&clk_uart0>, <&clk_gates9 12>;
 235                 clock-names = "sclk_uart", "pclk_uart";
 236                 reg-shift = <2>;
 237                 reg-io-width = <4>;
 238                 dmas = <&pdma 2>, <&pdma 3>;
 239                 #dma-cells = <2>;
 240                 pinctrl-names = "default";
 241                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 242                 status = "disabled";
 243         };
 244
 245         uart1: serial@11020000 {
 246                 compatible = "rockchip,serial";
 247                 reg = <0x11020000 0x100>;
 248                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 249                 clock-frequency = <24000000>;
 250                 clocks = <&clk_uart1>, <&clk_gates9 13>;
 251                 clock-names = "sclk_uart", "pclk_uart";
 252                 reg-shift = <2>;
 253                 reg-io-width = <4>;
 254                 dmas = <&pdma 4>, <&pdma 5>;
 255                 #dma-cells = <2>;
 256                 pinctrl-names = "default";
 257                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 258                 status = "disabled";
 259         };
 260
 261         uart2: serial@11030000 {
 262                 compatible = "rockchip,serial";
 263                 reg = <0x11030000 0x100>;
 264                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 265                 clock-frequency = <24000000>;
 266                 clocks = <&clk_uart2>, <&clk_gates9 14>;
 267                 lock-names = "sclk_uart", "pclk_uart";
 268                 reg-shift = <2>;
 269                 reg-io-width = <4>;
 270                 dmas = <&pdma 6>, <&pdma 7>;
 271                 #dma-cells = <2>;
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&uart2_xfer>;
 274                 status = "disabled";
 275         };
 276
 277         i2c0: i2c@11050000 {
 278                 compatible = "rockchip,rk30-i2c";
 279                 reg = <0x11050000 0x1000>;
 280                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 pinctrl-names = "default", "gpio", "sleep";
 284                 pinctrl-0 = <&i2c0_xfer>;
 285                 pinctrl-1 = <&i2c0_gpio>;
 286                 pinctrl-2 = <&i2c0_sleep>;
 287                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>,
 288                         <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 289                 clocks = <&clk_gates8 15>;
 290                 rockchip,check-idle = <1>;
 291                 status = "disabled";
 292         };
 293
 294         i2c1: i2c@11060000 {
 295                 compatible = "rockchip,rk30-i2c";
 296                 reg = <0x11060000 0x1000>;
 297                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300                 pinctrl-names = "default", "gpio", "sleep";
 301                 pinctrl-0 = <&i2c1_xfer>;
 302                 pinctrl-1 = <&i2c1_gpio>;
 303                 pinctrl-2 = <&i2c1_sleep>;
 304                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>,
 305                         <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 306                 clocks = <&clk_gates9 0>;
 307                 rockchip,check-idle = <1>;
 308                 status = "disabled";
 309         };
 310
 311         i2c2: i2c@11070000 {
 312                 compatible = "rockchip,rk30-i2c";
 313                 reg = <0x11070000 0x1000>;
 314                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 pinctrl-names = "default", "gpio", "sleep";
 318                 pinctrl-0 = <&i2c2_xfer>;
 319                 pinctrl-1 = <&i2c2_gpio>;
 320                 pinctrl-2 = <&i2c2_sleep>;
 321                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>,
 322                         <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 323                 clocks = <&clk_gates9 1>;
 324                 rockchip,check-idle = <1>;
 325                 status = "disabled";
 326         };
 327
 328         i2c3: i2c@11080000 {
 329                 compatible = "rockchip,rk30-i2c";
 330                 reg = <0x11080000 0x1000>;
 331                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334                 pinctrl-names = "default", "gpio", "sleep";
 335                 pinctrl-0 = <&i2c3_xfer>;
 336                 pinctrl-1 = <&i2c3_gpio>;
 337                 pinctrl-2 = <&i2c3_sleep>;
 338                 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>,
 339                         <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
 340                 clocks = <&clk_gates9 2>;
 341                 rockchip,check-idle = <1>;
 342                 status = "disabled";
 343         };
 344
 345         amba {
 346                 #address-cells = <1>;
 347                 #size-cells = <1>;
 348                 compatible = "arm,amba-bus";
 349                 interrupt-parent = <&gic>;
 350                 ranges;
 351
 352                 pdma: pdma@110f0000 {
 353                         compatible = "arm,pl330", "arm,primecell";
 354                         reg = <0x110f0000 0x4000>;
 355                         clocks = <&clk_gates8 2>;
 356                         clock-names = "apb_pclk";
 357                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 358                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 359                         #dma-cells = <1>;
 360                 };
 361         };
 362
 363         i2s0: i2s0@100c0000 {
 364                 compatible = "rockchip-i2s";
 365                 reg = <0x100c0000 0x1000>;
 366                 i2s-id = <0>;
 367                 clocks = <&clk_i2s0>, <&clk_gates8 7>;
 368                 clock-names = "i2s_clk", "i2s_hclk";
 369                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 370                 dmas = <&pdma 11>, <&pdma 12>;
 371                 #dma-cells = <2>;
 372                 dma-names = "tx", "rx";
 373         };
 374
 375         i2s1: i2s1@100b0000 {
 376                 compatible = "rockchip-i2s";
 377                 reg = <0x100b0000 0x1000>;
 378                 i2s-id = <1>;
 379                 clocks = <&clk_i2s1>, <&clk_i2s1_out>, <&clk_gates8 8>;
 380                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 381                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 382                 dmas = <&pdma 14>, <&pdma 15>;
 383                 #dma-cells = <2>;
 384                 dma-names = "tx", "rx";
 385                 status = "disabled";
 386         };
 387
 388         i2s2: i2s2@100e0000 {
 389                 compatible = "rockchip-i2s";
 390                 reg = <0x100e0000 0x1000>;
 391                 i2s-id = <2>;
 392                 clocks = <&clk_i2s2>, <&clk_gates8 9>;
 393                 clock-names = "i2s_clk", "i2s_hclk";
 394                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 395                 dmas = <&pdma 0>, <&pdma 1>;
 396                 #dma-cells = <2>;
 397                 dma-names = "tx", "rx";
 398                 status = "disabled";
 399         };
 400
 401         spdif: spdif@100d0000 {
 402                 compatible = "rockchip-spdif";
 403                 reg = <0x100d0000 0x1000>;
 404                 clocks = <&clk_spdif>, <&clk_gates8 10>;
 405                 clock-names = "spdif_mclk", "spdif_hclk";
 406                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 407                 dmas = <&pdma 10>;
 408                 #dma-cells = <1>;
 409                 dma-names = "tx";
 410                 status = "disabled";
 411         };
 412
 413         tsadc: tsadc@11150000 {
 414                 compatible = "rockchip,rk3228-tsadc";
 415                 reg = <0x11150000 0x100>;
 416                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 417                 clock-frequency = <32768>;
 418                 clocks = <&clk_tsadc>, <&clk_gates9 15>;
 419                 resets = <&reset RK3228_RST_TSADC>;
 420                 reset-names = "tsadc-apb";
 421                 #thermal-sensor-cells = <1>;
 422                 hw-shut-temp = <120000>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&tsadc_gpio>;
 425                 tsadc-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
 426                 tsadc-tshut-polarity = <0>;/* tshut polarity 0:LOW 1:HIGH */
 427                 status = "okay";
 428         };
 429
 430         gpu {
 431                 compatible = "arm,mali400";
 432                 reg = <0x20001000 0x200>,
 433                       <0x20000000 0x100>,
 434                       <0x20003000 0x100>,
 435                       <0x20008000 0x1100>,
 436                       <0x20004000 0x100>,
 437                       <0x2000A000 0x1100>,
 438                       <0x20005000 0x100>;
 439
 440                 reg-names = "Mali_L2",
 441                             "Mali_GP",
 442                             "Mali_GP_MMU",
 443                             "Mali_PP0",
 444                             "Mali_PP0_MMU",
 445                             "Mali_PP1",
 446                             "Mali_PP1_MMU";
 447
 448                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 449                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 450                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 451                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 452                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 453                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 454
 455                 interrupt-names = "Mali_GP_IRQ",
 456                                   "Mali_GP_MMU_IRQ",
 457                                   "Mali_PP0_IRQ",
 458                                   "Mali_PP0_MMU_IRQ",
 459                                   "Mali_PP1_IRQ",
 460                                   "Mali_PP1_MMU_IRQ";
 461         };
 462
 463         fb: fb {
 464                 compatible = "rockchip,rk-fb";
 465                 rockchip,disp-mode = <NO_DUAL>;
 466         };
 467
 468         rk_screen: rk_screen {
 469                 compatible = "rockchip,screen";
 470         };
 471
 472         pwm0: pwm@110b0000 {
 473                 compatible = "rockchip,rk-pwm";
 474                 reg = <0x110b0000 0x10>;
 475                 /* used by driver on remotectl'pwm */
 476                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 477                 #pwm-cells = <2>;
 478                 pinctrl-names = "default";
 479                 pinctrl-0 = <&pwm0_pin>;
 480                 clocks = <&clk_gates9 7>;
 481                 clock-names = "pclk_pwm";
 482                 status = "disabled";
 483         };
 484
 485         pwm1: pwm@110b0010 {
 486                 compatible = "rockchip,rk-pwm";
 487                 reg = <0x110b0010 0x10>;
 488                 /* used by driver on remotectl'pwm */
 489                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 490                 #pwm-cells = <2>;
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&pwm1_pin>;
 493                 clocks = <&clk_gates9 7>;
 494                 clock-names = "pclk_pwm";
 495                 status = "disabled";
 496         };
 497
 498         pwm2: pwm@110b0020 {
 499                 compatible = "rockchip,rk-pwm";
 500                 reg = <0x110b0020 0x10>;
 501                 /* used by driver on remotectl'pwm */
 502                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 503                 #pwm-cells = <2>;
 504                 pinctrl-names = "default";
 505                 pinctrl-0 = <&pwm2_pin>;
 506                 clocks = <&clk_gates9 7>;
 507                 clock-names = "pclk_pwm";
 508                 status = "disabled";
 509         };
 510
 511         pwm3: pwm@110b0030 {
 512                 compatible = "rockchip,rk-pwm";
 513                 reg = <0x110b0030 0x10>;
 514                 /* used by driver on remotectl'pwm */
 515                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 516                 #pwm-cells = <2>;
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&pwmir_pin>;
 519                 clocks = <&clk_gates9 7>;
 520                 clock-names = "pclk_pwm";
 521                 status = "disabled";
 522         };
 523
 524         vop: vop@20050000 {
 525                 compatible = "rockchip,rk3228-lcdc";
 526
 527                 rockchip,cabc_mode = <0>;
 528                 rockchip,pwr18 = <0>;
 529                 rockchip,iommu-enabled = <1>;
 530                 reg = <0x20050000 0x300>;
 531                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>;
 533                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 534         };
 535
 536         vop_mmu {
 537                 dbgname = "vop";
 538                 compatible = "rockchip,vop_mmu";
 539                 reg = <0x20053f00 0x100>;
 540                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 541                 interrupt-names = "vop_mmu";
 542         };
 543
 544         hevc_mmu {
 545                 dbgname = "hevc";
 546                 compatible = "rockchip,hevc_mmu";
 547                 reg = <0x20034440 0x40>,
 548                       <0x20034480 0x40>;
 549                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 550                 interrupt-names = "hevc_mmu";
 551         };
 552
 553         vpu_mmu {
 554                 dbgname = "vpu";
 555                 compatible = "rockchip,vpu_mmu";
 556                 reg = <0x20026800 0x100>;
 557                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 558                 interrupt-names = "vpu_mmu";
 559         };
 560
 561         iep_mmu {
 562                 dbgname = "iep";
 563                 compatible = "rockchip,iep_mmu";
 564                 reg = <0x20078800 0x100>;
 565                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 566                 interrupt-names = "iep_mmu";
 567         };
 568
 569         hdmi: hdmi@200a0000 {
 570                 compatible = "rockchip,rk3228-hdmi";
 571                 reg = <0x200a0000 0x20000>,
 572                       <0x12030000 0x10000>;
 573                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 574                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 575                 clocks = <&clk_gates3 7>,
 576                          <&clk_gates14 6>,
 577                          <&clk_gates10 7>,
 578                          <&clk_hdmi_cec>;
 579                 clock-names = "hdcp_clk_hdmi",
 580                               "pclk_hdmi",
 581                               "pclk_hdmi_phy",
 582                               "cec_clk_hdmi";
 583                 pinctrl-names = "default", "gpio";
 584                 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer>;
 585                 pinctrl-1 = <&i2c3_gpio>;
 586                 rockchip,hotplug = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>;
 587                 rockchip,hdmi_audio_source = <0>;
 588                 rockchip,hdcp_enable = <0>;
 589                 rockchip,cec_enable = <0>;
 590                 status = "disabled";
 591         };
 592
 593         hdmi_hdcp2: hdmi_hdcp2@20090000 {
 594                 compatible = "rockchip,rk3228-hdmi-hdcp2";
 595                 reg = <0x20090000 0x10000>;
 596                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 597                 clocks = <&aclk_hdcp>,
 598                          <&clk_gates14 12>,
 599                          <&clk_gates14 11>,
 600                          <&clk_hdcp>;
 601                 clock-names = "aclk_hdcp2",
 602                               "hclk_hdcp2_mmu",
 603                               "pclk_hdcp2",
 604                               "hdcp2_clk_hdmi";
 605                 status = "disabled";
 606         };
 607
 608         tve: tve {
 609                 compatible = "rockchip,rk3228-tve";
 610                 reg = <0x20053e00 0x100>,
 611                       <0x12020000 0x10000>;
 612                 clocks = <&clk_gates10 8>;
 613                 clock-names = "pclk_vdac";
 614                 status = "disabled";
 615         };
 616
 617         emmc: rksdmmc@30020000 {
 618                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 619                 reg = <0x30020000 0x10000>;
 620                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 621                 #address-cells = <1>;
 622                 #size-cells = <0>;
 623                 clocks = <&clk_emmc>, <&clk_gates11 2>;
 624                 clock-names = "clk_mmc", "hclk_mmc";
 625                 num-slots = <1>;
 626                 fifo-depth = <0x100>;
 627                 bus-width = <8>;
 628                 cru_regsbase = <0x124>;
 629                 cru_reset_offset = <3>;
 630         };
 631
 632         sdmmc: rksdmmc@30000000 {
 633                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 634                 reg = <0x30000000 0x10000>;
 635                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638                 pinctrl-names = "default", "idle";
 639                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
 640                 pinctrl-1 = <&sdmmc_gpio>;
 641                 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>; /* CD GPIO */
 642                 clocks = <&clk_sdmmc0>, <&clk_gates11 0>;
 643                 clock-names = "clk_mmc", "hclk_mmc";
 644                 num-slots = <1>;
 645                 fifo-depth = <0x100>;
 646                 bus-width = <4>;
 647                 cru_regsbase = <0x124>;
 648                 cru_reset_offset = <1>;
 649         };
 650
 651         sdio: rksdmmc@30010000 {
 652                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 653                 reg = <0x30010000 0x10000>;
 654                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 pinctrl-names = "default", "idle";
 658                 pinctrl-0 = <&sdio0_pwren &sdio0_cmd &sdio0_clk &sdio0_bus4>;
 659                 pinctrl-1 = <&sdio0_gpio>;
 660                 clocks = <&clk_sdio>, <&clk_gates11 1>;
 661                 clock-names = "clk_mmc", "hclk_mmc";
 662                 num-slots = <1>;
 663                 fifo-depth = <0x100>;
 664                 bus-width = <4>;
 665                 cru_regsbase = <0x124>;
 666                 cru_reset_offset = <2>;
 667         };
 668
 669         nandc: nandc@30030000 {
 670                 compatible = "rockchip,rk-nandc";
 671                 reg = <0x30030000 0x4000>;
 672                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 673                 nandc_id = <0>;
 674                 clocks = <&clk_nandc>, <&clk_gates1 0>, <&clk_gates11 3>;
 675                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 676         };
 677
 678         otg: usb@30040000 {
 679                 compatible = "rockchip,rk3228_usb20_otg";
 680                 reg = <0x30040000 0x40000>;
 681                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 682                 clocks = <&clk_gates1 5>, <&clk_gates11 12>;
 683                 clock-names = "clk_usbphy0", "hclk_usb0";
 684                 resets = <&reset RK3228_RST_USBOTG0>, <&reset RK3228_RST_UTMI0>,
 685                                 <&reset RK3228_RST_OTGC0>;
 686                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 687                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 688                 rockchip,usb-mode = <0>;
 689         };
 690
 691         ehci0: usb@30080000 {
 692                 compatible = "generic-ehci";
 693                 reg = <0x30080000 0x20000>;
 694                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 695                 clocks = <&clk_gates1 6>, <&clk_gates11 6>;
 696                 clock-names = "clk_usbphy1", "hclk_host0";
 697                 resets = <&reset RK3228_RST_USBHOST0>, <&reset RK3228_RST_UTMI1>,
 698                                 <&reset RK3228_RST_HOST_CTRL0>;
 699                 reset-names = "host_ahb", "host_phy", "host_controller";
 700         };
 701
 702         ohci0: usb@300a0000 {
 703                 compatible = "generic-ohci";
 704                 reg = <0x300a0000 0x20000>;
 705                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 706         };
 707
 708         ehci1: usb@300c0000 {
 709                 compatible = "generic-ehci";
 710                 reg = <0x300c0000 0x20000>;
 711                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 712                 clocks = <&clk_gates1 6>, <&clk_gates11 8>;
 713                 clock-names = "clk_usbphy1", "hclk_host0";
 714                 resets = <&reset RK3228_RST_USBHOST1>, <&reset RK3228_RST_UTMI2>,
 715                                 <&reset RK3228_RST_HOST_CTRL1>;
 716                 reset-names = "host_ahb", "host_phy", "host_controller";
 717         };
 718
 719         ohci1: usb@300e0000 {
 720                 compatible = "generic-ohci";
 721                 reg = <0x300e0000 0x20000>;
 722                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 723         };
 724
 725         ehci2: usb@30100000 {
 726                 compatible = "generic-ehci";
 727                 reg = <0x30100000 0x20000>;
 728                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 729                 clocks = <&clk_gates1 6>, <&clk_gates11 10>;
 730                 clock-names = "clk_usbphy1", "hclk_host0";
 731                 resets = <&reset RK3228_RST_USBHOST2>, <&reset RK3228_RST_UTMI3>,
 732                                 <&reset RK3228_RST_HOST_CTRL2>;
 733                 reset-names = "host_ahb", "host_phy", "host_controller";
 734         };
 735
 736         ohci2: usb@30120000 {
 737                 compatible = "generic-ohci";
 738                 reg = <0x30120000 0x20000>;
 739                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 740         };
 741
 742         gmac: eth@30200000 {
 743                 compatible = "rockchip,rk3228-gmac";
 744                 reg = <0x30200000 0x10000>;
 745                 rockchip,grf = <&grf>;
 746                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 747                 interrupt-names = "macirq";
 748                 clocks = <&clk_mac>, <&clk_gates5 5>,
 749                         <&clk_gates5 6>, <&clk_gates5 3>,
 750                         <&clk_gates5 4>, <&clk_gates11 4>,
 751                         <&clk_gates11 5>;
 752                 clock-names = "clk_mac", "mac_clk_rx",
 753                         "mac_clk_tx", "clk_mac_ref",
 754                         "clk_mac_refout", "aclk_mac",
 755                         "pclk_mac";
 756                 phy-mode = "rgmii";
 757                 pinctrl-names = "default";
 758                 pinctrl-0 = <&rgmii_pins>;
 759                 status = "disabled";
 760         };
 761
 762         pinctrl: pinctrl {
 763                 compatible = "rockchip,rk3228-pinctrl";
 764                 rockchip,grf = <&grf>;
 765                 #address-cells = <1>;
 766                 #size-cells = <1>;
 767                 ranges;
 768
 769                 gpio0: gpio0@11110000 {
 770                         compatible = "rockchip,gpio-bank";
 771                         reg =   <0x11110000 0x100>;
 772                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 773                         clocks = <&clk_gates9 9>;
 774
 775                         gpio-controller;
 776                         #gpio-cells = <2>;
 777
 778                         interrupt-controller;
 779                         #interrupt-cells = <2>;
 780                 };
 781
 782                 gpio1: gpio1@11120000 {
 783                         compatible = "rockchip,gpio-bank";
 784                         reg = <0x11120000 0x100>;
 785                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 786                         clocks = <&clk_gates9 9>;
 787
 788                         gpio-controller;
 789                         #gpio-cells = <2>;
 790
 791                         interrupt-controller;
 792                         #interrupt-cells = <2>;
 793                 };
 794
 795                 gpio2: gpio2@11130000 {
 796                         compatible = "rockchip,gpio-bank";
 797                         reg = <0x11130000 0x100>;
 798                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 799                         clocks = <&clk_gates9 10>;
 800
 801                         gpio-controller;
 802                         #gpio-cells = <2>;
 803
 804                         interrupt-controller;
 805                         #interrupt-cells = <2>;
 806                 };
 807
 808                 gpio3: gpio3@11140000 {
 809                         compatible = "rockchip,gpio-bank";
 810                         reg = <0x11140000 0x100>;
 811                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 812                         clocks = <&clk_gates9 11>;
 813
 814                         gpio-controller;
 815                         #gpio-cells = <2>;
 816
 817                         interrupt-controller;
 818                         #interrupt-cells = <2>;
 819                 };
 820
 821                 pcfg_pull_up: pcfg-pull-up {
 822                         bias-pull-up;
 823                 };
 824
 825                 pcfg_pull_down: pcfg-pull-down {
 826                         bias-pull-down;
 827                 };
 828
 829                 pcfg_pull_none: pcfg-pull-none {
 830                         bias-disable;
 831                 };
 832
 833                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 834                         drive-strength = <8>;
 835                 };
 836
 837                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 838                         drive-strength = <12>;
 839                 };
 840
 841                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 842                         bias-pull-up;
 843                         drive-strength = <8>;
 844                 };
 845
 846                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
 847                         drive-strength = <4>;
 848                 };
 849
 850                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
 851                         bias-pull-up;
 852                         drive-strength = <4>;
 853                 };
 854
 855                 pcfg_pull_down_drv_12ma: pcfg-pull-down-drv-12ma {
 856                         bias-pull-down;
 857                         drive-strength = <12>;
 858                 };
 859
 860                 pcfg_output_high: pcfg-output-high {
 861                         output-high;
 862                 };
 863
 864                 pcfg_output_low: pcfg-output-low {
 865                         output-low;
 866                 };
 867
 868                 pcfg_input_high: pcfg-input-high {
 869                         bias-pull-up;
 870                         input-enable;
 871                 };
 872
 873                 i2c0 {
 874                         i2c0_xfer: i2c0-xfer {
 875                                 rockchip,pins = <0 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,
 876                                                 <0 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>;
 877                         };
 878                         i2c0_gpio: i2c0-gpio {
 879                                 rockchip,pins = <0 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_none>,
 880                                                 <0 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_none>;
 881                         };
 882                         i2c0_sleep: i2c0-sleep {
 883                                 rockchip,pins = <0 GPIO_A0 RK_FUNC_GPIO &pcfg_input_high>,
 884                                                 <0 GPIO_A1 RK_FUNC_GPIO &pcfg_input_high>;
 885                         };
 886                 };
 887
 888                 i2c1 {
 889                         i2c1_xfer: i2c1-xfer {
 890                                 rockchip,pins = <0 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,
 891                                                 <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
 892                         };
 893                         i2c1_gpio: i2c1-gpio {
 894                                 rockchip,pins = <0 GPIO_A2  RK_FUNC_GPIO &pcfg_pull_none>,
 895                                                 <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
 896                         };
 897                         i2c1_sleep: i2c1-sleep {
 898                                 rockchip,pins = <0 GPIO_A2 RK_FUNC_GPIO &pcfg_input_high>,
 899                                                 <0 GPIO_A3 RK_FUNC_GPIO &pcfg_input_high>;
 900
 901                         };
 902                 };
 903
 904                 i2c2 {
 905                         i2c2_xfer: i2c2-xfer {
 906                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
 907                                                 <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
 908                         };
 909                         i2c2_gpio: i2c2-gpio {
 910                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
 911                                                 <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;
 912                         };
 913                         i2c2_sleep: i2c2-sleep {
 914                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
 915                                                 <2 GPIO_C4 RK_FUNC_GPIO &pcfg_input_high>;
 916                         };
 917                 };
 918
 919                 i2c3 {
 920                         i2c3_xfer: i2c3-xfer {
 921                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
 922                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
 923                         };
 924                         i2c3_gpio: i2c3-gpio {
 925                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
 926                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
 927                         };
 928                         i2c3_sleep: i2c3-sleep {
 929                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
 930                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
 931                         };
 932                 };
 933
 934                 uart0 {
 935                         uart0_xfer: uart0-xfer {
 936                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_up>,
 937                                                 <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
 938                         };
 939
 940                         uart0_cts: uart0-cts {
 941                                 rockchip,pins = <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;
 942                         };
 943
 944                         uart0_rts: uart0-rts {
 945                                 rockchip,pins = <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
 946                         };
 947
 948                         uart0_rts_gpio: uart0-rts-gpio {
 949                                 rockchip,pins = <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
 950                         };
 951                 };
 952
 953                 uart1 {
 954                         uart1_xfer: uart1-xfer {
 955                                 rockchip,pins = <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_up>,
 956                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>;
 957                         };
 958
 959                         uart1_cts: uart1-cts {
 960                                 rockchip,pins = <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
 961                         };
 962
 963                         uart1_rts: uart1-rts {
 964                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;
 965                         };
 966                 };
 967
 968                 uart11 {
 969                         uart11_xfer: uart11-xfer {
 970                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_up>,
 971                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
 972                         };
 973
 974                         uart11_cts: uart11-cts {
 975                                 rockchip,pins = <3 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
 976                         };
 977
 978                         uart11_rts: uart11-rts {
 979                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>;
 980                         };
 981                 };
 982
 983                 uart2 {
 984                         uart2_xfer: uart2-xfer {
 985                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up>,
 986                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>;
 987                         };
 988
 989                         uart2_cts: uart2-cts {
 990                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
 991                         };
 992
 993                         uart2_rts: uart2-rts {
 994                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>;
 995                         };
 996                 };
 997
 998                 uart21 {
 999                         uart21_xfer: uart21-xfer {
1000                                 rockchip,pins = <1 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
1001                                                 <1 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1002                         };
1003                 };
1004
1005                 spi0 {
1006                         spi0_clk: spi0-clk {
1007                                 rockchip,pins = <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
1008                         };
1009                         spi0_cs0: spi0-cs0 {
1010                                 rockchip,pins = <0 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1011                         };
1012                         spi0_tx: spi0-tx {
1013                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1014                         };
1015                         spi0_rx: spi0-rx {
1016                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1017                         };
1018                         spi0_cs1: spi0-cs1 {
1019                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_up>;
1020                         };
1021                 };
1022
1023                 spi1 {
1024                         spi1_clk: spi1-clk {
1025                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_2 &pcfg_pull_up>;
1026                         };
1027                         spi1_cs0: spi1-cs0 {
1028                                 rockchip,pins = <2 GPIO_A2 RK_FUNC_2 &pcfg_pull_up>;
1029                         };
1030                         spi1_rx: spi1-rx {
1031                                 rockchip,pins = <2 GPIO_A0 RK_FUNC_2 &pcfg_pull_up>;
1032                         };
1033                         spi1_tx: spi1-tx {
1034                                 rockchip,pins = <2 GPIO_A1 RK_FUNC_2 &pcfg_pull_up>;
1035                         };
1036                         spi1_cs1: spi1-cs1 {
1037                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_up>;
1038                         };
1039                 };
1040
1041                 i2s {
1042                         i2s_mclk: i2s-mclk {
1043                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
1044                         };
1045
1046                         i2s_sclk:i2s-sclk {
1047                                 rockchip,pins = <0 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>;
1048                         };
1049
1050                         i2s_lrckrx:i2s-lrckrx {
1051                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;
1052                         };
1053
1054                         i2s_lrcktx:i2s-lrcktx {
1055                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1056                         };
1057
1058                         i2s_sdi:i2s-sdi {
1059                                 rockchip,pins = <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1060                         };
1061
1062                         i2s_sdo0:i2s-sdo0 {
1063                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1064                         };
1065
1066                         i2s_sdo1:i2s-sdo1 {
1067                                 rockchip,pins = <1 GPIO_A2 RK_FUNC_2 &pcfg_pull_none>;
1068                         };
1069
1070                         i2s_sdo2:i2s-sdo2 {
1071                                 rockchip,pins = <1 GPIO_A4 RK_FUNC_2 &pcfg_pull_none>;
1072                         };
1073
1074                         i2s_sdo3:i2s-sdo3 {
1075                                 rockchip,pins = <1 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1076                         };
1077
1078                         i2s_gpio: i2s-gpio {
1079                                 rockchip,pins = <0 GPIO_B0  RK_FUNC_GPIO &pcfg_pull_none>,
1080                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>,
1081                                                 <0 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_none>,
1082                                                 <0 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1083                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1084                                                 <0 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1085                                                 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_none>,
1086                                                 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_none>,
1087                                                 <1 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_none>;
1088                         };
1089                 };
1090
1091                 spdif0 {
1092                         spdif0_tx: spdif0-tx {
1093                                 rockchip,pins = <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1094                         };
1095                 };
1096
1097                 spdif1 {
1098                         spdif1_tx: spdif1-tx {
1099                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>;
1100                         };
1101                 };
1102
1103                 sdmmc {
1104                         sdmmc_clk: sdmmc-clk {
1105                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1106                         };
1107
1108                         sdmmc_cmd: sdmmc-cmd {
1109                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1110                         };
1111
1112                         sdmmc_dectn: sdmmc-dectn {
1113                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1114                         };
1115
1116                         sdmmc_wrprt: sdmmc-wrprt {
1117                                 rockchip,pins = <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1118                         };
1119
1120                         sdmmc_pwren: sdmmc-pwren {
1121                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1122                         };
1123
1124                         sdmmc_bus1: sdmmc-bus1 {
1125                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1126                         };
1127
1128                         sdmmc_bus4: sdmmc-bus4 {
1129                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1130                                                 <1 GPIO_C3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1131                                                 <1 GPIO_C4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1132                                                 <1 GPIO_C5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1133                         };
1134
1135                         sdmmc_gpio: sdmmc-gpio {
1136                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1137                                                 <1 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1138                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1139                                                 <1 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1140                                                 <1 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1141                                                 <1 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1142                                                 <1 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1143                                                 <1 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1144                                                 <1 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
1145                         };
1146                 };
1147
1148                 sdio0 {
1149                         sdio0_bus1: sdio0-bus1 {
1150                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1151                         };
1152
1153                         sdio0_bus4: sdio0-bus4 {
1154                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1155                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1156                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1157                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1158                         };
1159
1160                         sdio0_cmd: sdio0-cmd {
1161                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_2 &pcfg_pull_up_drv_4ma>;
1162                         };
1163
1164                         sdio0_clk: sdio0-clk {
1165                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1166                         };
1167
1168                         sdio0_pwren: sdio0-pwren {
1169                                 rockchip,pins = <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_up>;
1170                         };
1171
1172                         sdio0_gpio: sdio0-gpio {
1173                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1174                                                 <1 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1175                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1176                                                 <1 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1177                                                 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1178                                                 <1 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1179                                                 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
1180                         };
1181                 };
1182
1183
1184                 sdio1 {
1185                         sdio1_bus1: sdio1-bus1 {
1186                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1187                         };
1188
1189                         sdio1_bus4: sdio1-bus4 {
1190                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1191                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1192                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1193                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1194                         };
1195
1196                         sdio1_cmd: sdio1-cmd {
1197                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_2 &pcfg_pull_up_drv_4ma>;
1198                         };
1199
1200                         sdio1_clk: sdio1-clk {
1201                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1202                         };
1203
1204                         sdio1_pwren: sdio1-pwren {
1205                                 rockchip,pins = <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_up>;
1206                         };
1207
1208                         sdio1_gpio: sdio1-gpio {
1209                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1210                                                 <1 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1211                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1212                                                 <1 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1213                                                 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1214                                                 <1 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1215                                                 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
1216                         };
1217                 };
1218
1219                 emmc {
1220                         emmc_clk: emmc-clk {
1221                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1222                         };
1223
1224                         emmc_cmd: emmc-cmd {
1225                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1226                         };
1227
1228                         emmc_pwren: emmc-pwren {
1229                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1230                         };
1231
1232                         emmc_rstnout: emmc_rstnout {
1233                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_2 &pcfg_pull_none>;
1234                         };
1235
1236                         emmc_bus1: emmc-bus1 {
1237                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
1238                         };
1239
1240                         emmc_bus4: emmc-bus4 {
1241                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
1242                                                 <1 GPIO_C3 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
1243                                                 <1 GPIO_C4 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
1244                                                 <1 GPIO_C5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
1245                         };
1246                 };
1247
1248                 pwm0 {
1249                         pwm0_pin: pwm0-pin {
1250                                 rockchip,pins = <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1251                         };
1252                 };
1253
1254                 pwm1 {
1255                         pwm1_pin: pwm1-pin {
1256                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1257                         };
1258                 };
1259
1260                 pwm2 {
1261                         pwm2_pin: pwm2-pin {
1262                                 rockchip,pins = <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;
1263                         };
1264                 };
1265
1266                 pwmir {
1267                         pwmir_pin: pwmir-pin {
1268                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1269                         };
1270                 };
1271
1272                 pwm10 {
1273                         pwm10_pin: pwm10-pin {
1274                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;
1275                         };
1276                 };
1277
1278                 pwm11 {
1279                         pwm11_pin: pwm11-pin {
1280                                 rockchip,pins = <0 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1281                         };
1282                 };
1283
1284                 pwm12 {
1285                         pwm12_pin: pwm12-pin {
1286                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_2 &pcfg_pull_none>;
1287                         };
1288                 };
1289
1290                 pwm1ir {
1291                         pwm1ir_pin: pwm1ir-pin {
1292                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_2 &pcfg_pull_none>;
1293                         };
1294                 };
1295
1296                 gmac {
1297                         rgmii_pins: rgmii-pins {
1298                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,
1299                                                 <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,
1300                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,
1301                                                 <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1302                                                 <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1303                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1304                                                 <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1305                                                 <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1306                                                 <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1307                                                 <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,
1308                                                 <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1309                                                 <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1310                                                 <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,
1311                                                 <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>,
1312                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
1313                         };
1314
1315                         rmii_pins: rmii-pins {
1316                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,
1317                                                 <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,
1318                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,
1319                                                 <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1320                                                 <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1321                                                 <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1322                                                 <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,
1323                                                 <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1324                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,
1325                                                 <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1326                         };
1327                 };
1328
1329                 tsadc_pin {
1330                         tsadc_int: tsadc-int {
1331                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>;
1332                         };
1333                         tsadc_gpio: tsadc-gpio {
1334                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>;
1335                         };
1336                 };
1337
1338                 hdmi_pin {
1339                         hdmi_cec: hdmi-cec {
1340                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1341                         };
1342
1343                         hdmi_hpd: hdmi-hpd {
1344                                 rockchip,pins = <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1345                         };
1346                 };
1347
1348                 hdmi_i2c {
1349                         hdmii2c_xfer: hdmii2c-xfer {
1350                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_2 &pcfg_pull_none>,
1351                                                 <0 GPIO_A7 RK_FUNC_2 &pcfg_pull_none>;
1352                         };
1353                 };
1354         };
1355 };