1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/rkfb/rk_fb.h>
4 #include "skeleton.dtsi"
5 #include "rk3228-clocks.dtsi"
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <rk3228_dram_default_timing.dtsi>
12 compatible = "rockchip,rk3228";
13 interrupt-parent = <&gic>;
31 compatible = "arm,cortex-a7";
36 compatible = "arm,cortex-a7";
41 compatible = "arm,cortex-a7";
46 compatible = "arm,cortex-a7";
52 compatible = "arm,psci";
54 cpu_suspend = <0x84000001>;
55 cpu_off = <0x84000002>;
56 cpu_on = <0x84000003>;
59 gic: interrupt-controller@32010000 {
60 compatible = "arm,cortex-a15-gic";
62 #interrupt-cells = <3>;
64 reg = <0x32011000 0x1000>,
68 sgrf: syscon@10140000 {
69 compatible = "rockchip,rk3228-sgrf", "rockchip,sgrf", "syscon";
70 reg = <0x10140000 0x1000>;
73 grf: syscon@11000000 {
74 compatible = "rockchip,rk3228-grf", "rockchip,grf", "syscon";
75 reg = <0x11000000 0x1000>;
78 cru: syscon@110e0000 {
79 compatible = "rockchip,rk3228-cru", "rockchip,cru", "syscon";
80 reg = <0x110e0000 0x1000>;
83 ddrpctl: syscon@11200000 {
84 compatible = "rockchip,rk3228-ddrpctl", "syscon";
85 reg = <0x11200000 0x400>;
88 msch: syscon@31020000 {
89 compatible = "rockchip,rk32288-msch", "rockchip,msch", "syscon";
90 reg = <0x31020000 0x3000>;
94 compatible = "arm,cortex-a7-pmu";
95 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
101 reset: reset@110e0110{
102 compatible = "rockchip,reset";
103 reg = <0x110e0110 0x20>;
104 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
109 compatible = "arm,armv7-timer";
110 interrupts = <GIC_PPI 13
111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
113 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
114 clock-frequency = <24000000>;
118 compatible = "rockchip,fiq-debugger";
119 rockchip,serial-id = <2>;
120 rockchip,signal-irq = <159>;
121 rockchip,wake-irq = <0>;
122 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
123 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
127 rockchip_ion: rockchip-ion {
128 compatible = "rockchip,ion";
129 #address-cells = <1>;
133 compatible = "rockchip,ion-heap";
135 rockchip,ion_heap = <4>;
136 reg = <0x10000000 0x08000000>; /* 128 MB */
138 system_heap: system-heap {
139 compatible = "rockchip,ion-heap";
140 rockchip,ion_heap = <0>;
145 compatible = "rockchip,rk3228-dram";
147 dram_freq = <600000000>;
148 rockchip,dram_timing = <&dram_timing>;
151 rockchip_clocks_init: clocks-init{
152 compatible = "rockchip,clocks-init";
153 rockchip,clocks-init-parent =
154 <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
155 <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
156 <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
157 <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
158 <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
159 <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
160 <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
161 rockchip,clocks-init-rate =
162 <&clk_gpll 600000000>, <&clk_core 700000000>,
163 <&clk_cpll 500000000>, <&aclk_bus 250000000>,
164 <&hclk_bus 125000000>, <&pclk_bus 62500000>,
165 <&aclk_peri 250000000>, <&hclk_peri 125000000>,
166 <&pclk_peri 62500000>, <&clk_mac 125000000>,
167 <&aclk_iep 250000000>, <&hclk_vio 125000000>,
168 <&aclk_rga 250000000>, <&clk_gpu 250000000>,
169 <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
170 <&clk_vdec_cabac 250000000>;
172 rockchip,clocks-uboot-has-init =
177 rockchip_clocks_enable: clocks-enable {
178 compatible = "rockchip,clocks-enable";
196 <&clk_gates8 0>,/*aclk_intmem*/
197 <&clk_gates8 1>,/*clk_intmem_mbist*/
198 <&clk_gates8 2>,/*aclk_dmac_bus*/
199 <&clk_gates10 1>,/*g_aclk_bus*/
200 <&clk_gates13 9>,/*aclk_gic400*/
201 <&clk_gates8 3>,/*hclk_rom*/
202 <&clk_gates8 4>,/*pclk_ddrupctl*/
203 <&clk_gates8 6>,/*pclk_ddrmon*/
204 <&clk_gates9 4>,/*pclk_timer0*/
205 <&clk_gates9 5>,/*pclk_stimer*/
206 <&clk_gates10 0>,/*pclk_grf*/
207 <&clk_gates10 4>,/*pclk_cru*/
208 <&clk_gates10 6>,/*pclk_sgrf*/
209 <&clk_gates10 3>,/*pclk_ddrphy*/
210 <&clk_gates10 9>,/*pclk_phy_noc*/
216 <&clk_gates12 0>,/*aclk_peri_noc*/
217 <&clk_gates12 1>,/*hclk_peri_noc*/
218 <&clk_gates12 2>,/*pclk_peri_noc*/
220 <&clk_gates6 5>, /* g_clk_timer0 */
221 <&clk_gates6 6>, /* g_clk_timer1 */
223 <&clk_gates7 14>, /* g_aclk_gpu */
224 <&clk_gates7 15>, /* g_aclk_gpu_noc */
226 <&clk_gates1 3>;/*clk_jtag*/
229 uart0: serial@11010000 {
230 compatible = "rockchip,serial";
231 reg = <0x11010000 0x100>;
232 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
233 clock-frequency = <24000000>;
234 clocks = <&clk_uart0>, <&clk_gates9 12>;
235 clock-names = "sclk_uart", "pclk_uart";
238 dmas = <&pdma 2>, <&pdma 3>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
245 uart1: serial@11020000 {
246 compatible = "rockchip,serial";
247 reg = <0x11020000 0x100>;
248 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
249 clock-frequency = <24000000>;
250 clocks = <&clk_uart1>, <&clk_gates9 13>;
251 clock-names = "sclk_uart", "pclk_uart";
254 dmas = <&pdma 4>, <&pdma 5>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
261 uart2: serial@11030000 {
262 compatible = "rockchip,serial";
263 reg = <0x11030000 0x100>;
264 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
265 clock-frequency = <24000000>;
266 clocks = <&clk_uart2>, <&clk_gates9 14>;
267 lock-names = "sclk_uart", "pclk_uart";
270 dmas = <&pdma 6>, <&pdma 7>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&uart2_xfer>;
278 compatible = "rockchip,rk30-i2c";
279 reg = <0x11050000 0x1000>;
280 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
283 pinctrl-names = "default", "gpio", "sleep";
284 pinctrl-0 = <&i2c0_xfer>;
285 pinctrl-1 = <&i2c0_gpio>;
286 pinctrl-2 = <&i2c0_sleep>;
287 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>,
288 <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
289 clocks = <&clk_gates8 15>;
290 rockchip,check-idle = <1>;
295 compatible = "rockchip,rk30-i2c";
296 reg = <0x11060000 0x1000>;
297 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
298 #address-cells = <1>;
300 pinctrl-names = "default", "gpio", "sleep";
301 pinctrl-0 = <&i2c1_xfer>;
302 pinctrl-1 = <&i2c1_gpio>;
303 pinctrl-2 = <&i2c1_sleep>;
304 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>,
305 <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
306 clocks = <&clk_gates9 0>;
307 rockchip,check-idle = <1>;
312 compatible = "rockchip,rk30-i2c";
313 reg = <0x11070000 0x1000>;
314 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
317 pinctrl-names = "default", "gpio", "sleep";
318 pinctrl-0 = <&i2c2_xfer>;
319 pinctrl-1 = <&i2c2_gpio>;
320 pinctrl-2 = <&i2c2_sleep>;
321 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>,
322 <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
323 clocks = <&clk_gates9 1>;
324 rockchip,check-idle = <1>;
329 compatible = "rockchip,rk30-i2c";
330 reg = <0x11080000 0x1000>;
331 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
332 #address-cells = <1>;
334 pinctrl-names = "default", "gpio", "sleep";
335 pinctrl-0 = <&i2c3_xfer>;
336 pinctrl-1 = <&i2c3_gpio>;
337 pinctrl-2 = <&i2c3_sleep>;
338 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>,
339 <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
340 clocks = <&clk_gates9 2>;
341 rockchip,check-idle = <1>;
346 #address-cells = <1>;
348 compatible = "arm,amba-bus";
349 interrupt-parent = <&gic>;
352 pdma: pdma@110f0000 {
353 compatible = "arm,pl330", "arm,primecell";
354 reg = <0x110f0000 0x4000>;
355 clocks = <&clk_gates8 2>;
356 clock-names = "apb_pclk";
357 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
363 i2s0: i2s0@100c0000 {
364 compatible = "rockchip-i2s";
365 reg = <0x100c0000 0x1000>;
367 clocks = <&clk_i2s0>, <&clk_gates8 7>;
368 clock-names = "i2s_clk", "i2s_hclk";
369 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
370 dmas = <&pdma 11>, <&pdma 12>;
372 dma-names = "tx", "rx";
375 i2s1: i2s1@100b0000 {
376 compatible = "rockchip-i2s";
377 reg = <0x100b0000 0x1000>;
379 clocks = <&clk_i2s1>, <&clk_i2s1_out>, <&clk_gates8 8>;
380 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
381 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
382 dmas = <&pdma 14>, <&pdma 15>;
384 dma-names = "tx", "rx";
388 i2s2: i2s2@100e0000 {
389 compatible = "rockchip-i2s";
390 reg = <0x100e0000 0x1000>;
392 clocks = <&clk_i2s2>, <&clk_gates8 9>;
393 clock-names = "i2s_clk", "i2s_hclk";
394 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
395 dmas = <&pdma 0>, <&pdma 1>;
397 dma-names = "tx", "rx";
401 spdif: spdif@100d0000 {
402 compatible = "rockchip-spdif";
403 reg = <0x100d0000 0x1000>;
404 clocks = <&clk_spdif>, <&clk_gates8 10>;
405 clock-names = "spdif_mclk", "spdif_hclk";
406 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
413 tsadc: tsadc@11150000 {
414 compatible = "rockchip,rk3228-tsadc";
415 reg = <0x11150000 0x100>;
416 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
417 clock-frequency = <32768>;
418 clocks = <&clk_tsadc>, <&clk_gates9 15>;
419 resets = <&reset RK3228_RST_TSADC>;
420 reset-names = "tsadc-apb";
421 #thermal-sensor-cells = <1>;
422 hw-shut-temp = <120000>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&tsadc_gpio>;
425 tsadc-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
426 tsadc-tshut-polarity = <0>;/* tshut polarity 0:LOW 1:HIGH */
431 compatible = "arm,mali400";
432 reg = <0x20001000 0x200>,
440 reg-names = "Mali_L2",
448 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
455 interrupt-names = "Mali_GP_IRQ",
464 compatible = "rockchip,rk-fb";
465 rockchip,disp-mode = <NO_DUAL>;
468 rk_screen: rk_screen {
469 compatible = "rockchip,screen";
473 compatible = "rockchip,rk-pwm";
474 reg = <0x110b0000 0x10>;
475 /* used by driver on remotectl'pwm */
476 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pwm0_pin>;
480 clocks = <&clk_gates9 7>;
481 clock-names = "pclk_pwm";
486 compatible = "rockchip,rk-pwm";
487 reg = <0x110b0010 0x10>;
488 /* used by driver on remotectl'pwm */
489 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pwm1_pin>;
493 clocks = <&clk_gates9 7>;
494 clock-names = "pclk_pwm";
499 compatible = "rockchip,rk-pwm";
500 reg = <0x110b0020 0x10>;
501 /* used by driver on remotectl'pwm */
502 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pwm2_pin>;
506 clocks = <&clk_gates9 7>;
507 clock-names = "pclk_pwm";
512 compatible = "rockchip,rk-pwm";
513 reg = <0x110b0030 0x10>;
514 /* used by driver on remotectl'pwm */
515 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&pwmir_pin>;
519 clocks = <&clk_gates9 7>;
520 clock-names = "pclk_pwm";
525 compatible = "rockchip,rk3228-lcdc";
527 rockchip,cabc_mode = <0>;
528 rockchip,pwr18 = <0>;
529 rockchip,iommu-enabled = <1>;
530 reg = <0x20050000 0x300>;
531 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>;
533 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
538 compatible = "rockchip,vop_mmu";
539 reg = <0x20053f00 0x100>;
540 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
541 interrupt-names = "vop_mmu";
546 compatible = "rockchip,hevc_mmu";
547 reg = <0x20034440 0x40>,
549 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
550 interrupt-names = "hevc_mmu";
555 compatible = "rockchip,vpu_mmu";
556 reg = <0x20026800 0x100>;
557 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
558 interrupt-names = "vpu_mmu";
563 compatible = "rockchip,iep_mmu";
564 reg = <0x20078800 0x100>;
565 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
566 interrupt-names = "iep_mmu";
569 hdmi: hdmi@200a0000 {
570 compatible = "rockchip,rk3228-hdmi";
571 reg = <0x200a0000 0x20000>,
572 <0x12030000 0x10000>;
573 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&clk_gates3 7>,
579 clock-names = "hdcp_clk_hdmi",
583 pinctrl-names = "default", "gpio";
584 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer>;
585 pinctrl-1 = <&i2c3_gpio>;
586 rockchip,hotplug = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>;
587 rockchip,hdmi_audio_source = <0>;
588 rockchip,hdcp_enable = <0>;
589 rockchip,cec_enable = <0>;
593 hdmi_hdcp2: hdmi_hdcp2@20090000 {
594 compatible = "rockchip,rk3228-hdmi-hdcp2";
595 reg = <0x20090000 0x10000>;
596 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&aclk_hdcp>,
601 clock-names = "aclk_hdcp2",
609 compatible = "rockchip,rk3228-tve";
610 reg = <0x20053e00 0x100>,
611 <0x12020000 0x10000>;
612 clocks = <&clk_gates10 8>;
613 clock-names = "pclk_vdac";
617 emmc: rksdmmc@30020000 {
618 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
619 reg = <0x30020000 0x10000>;
620 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
621 #address-cells = <1>;
623 clocks = <&clk_emmc>, <&clk_gates7 0>;
624 clock-names = "clk_mmc", "hclk_mmc";
626 fifo-depth = <0x100>;
628 cru_regsbase = <0x124>;
629 cru_reset_offset = <3>;
632 sdmmc: rksdmmc@30000000 {
633 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
634 reg = <0x30000000 0x10000>;
635 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
636 #address-cells = <1>;
638 pinctrl-names = "default", "idle";
639 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
640 pinctrl-1 = <&sdmmc_gpio>;
641 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>; /* CD GPIO */
642 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
643 clock-names = "clk_mmc", "hclk_mmc";
645 fifo-depth = <0x100>;
647 cru_regsbase = <0x124>;
648 cru_reset_offset = <1>;
651 sdio: rksdmmc@30010000 {
652 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
653 reg = <0x30010000 0x10000>;
654 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
655 #address-cells = <1>;
657 pinctrl-names = "default", "idle";
658 pinctrl-0 = <&sdio0_pwren &sdio0_cmd &sdio0_clk &sdio0_bus4>;
659 pinctrl-1 = <&sdio0_gpio>;
660 clocks = <&clk_sdio>, <&clk_gates5 11>;
661 clock-names = "clk_mmc", "hclk_mmc";
663 fifo-depth = <0x100>;
665 cru_regsbase = <0x124>;
666 cru_reset_offset = <2>;
669 nandc: nandc@30030000 {
670 compatible = "rockchip,rk-nandc";
671 reg = <0x30030000 0x4000>;
672 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&clk_nandc>, <&clk_gates1 0>, <&clk_gates11 3>;
675 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
679 compatible = "rockchip,rk3228_usb20_otg";
680 reg = <0x30040000 0x40000>;
681 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clk_gates1 5>, <&clk_gates11 12>;
683 clock-names = "clk_usbphy0", "hclk_usb0";
684 resets = <&reset RK3228_RST_USBOTG0>, <&reset RK3228_RST_UTMI0>,
685 <&reset RK3228_RST_OTGC0>;
686 reset-names = "otg_ahb", "otg_phy", "otg_controller";
687 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
688 rockchip,usb-mode = <0>;
691 ehci0: usb@30080000 {
692 compatible = "generic-ehci";
693 reg = <0x30080000 0x20000>;
694 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&clk_gates1 6>, <&clk_gates11 6>;
696 clock-names = "clk_usbphy1", "hclk_host0";
697 resets = <&reset RK3228_RST_USBHOST0>, <&reset RK3228_RST_UTMI1>,
698 <&reset RK3228_RST_HOST_CTRL0>;
699 reset-names = "host_ahb", "host_phy", "host_controller";
702 ohci0: usb@300a0000 {
703 compatible = "generic-ohci";
704 reg = <0x300a0000 0x20000>;
705 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
708 ehci1: usb@300c0000 {
709 compatible = "generic-ehci";
710 reg = <0x300c0000 0x20000>;
711 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&clk_gates1 6>, <&clk_gates11 8>;
713 clock-names = "clk_usbphy1", "hclk_host0";
714 resets = <&reset RK3228_RST_USBHOST1>, <&reset RK3228_RST_UTMI2>,
715 <&reset RK3228_RST_HOST_CTRL1>;
716 reset-names = "host_ahb", "host_phy", "host_controller";
719 ohci1: usb@300e0000 {
720 compatible = "generic-ohci";
721 reg = <0x300e0000 0x20000>;
722 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
725 ehci2: usb@30100000 {
726 compatible = "generic-ehci";
727 reg = <0x30100000 0x20000>;
728 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&clk_gates1 6>, <&clk_gates11 10>;
730 clock-names = "clk_usbphy1", "hclk_host0";
731 resets = <&reset RK3228_RST_USBHOST2>, <&reset RK3228_RST_UTMI3>,
732 <&reset RK3228_RST_HOST_CTRL2>;
733 reset-names = "host_ahb", "host_phy", "host_controller";
736 ohci2: usb@30120000 {
737 compatible = "generic-ohci";
738 reg = <0x30120000 0x20000>;
739 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
743 compatible = "rockchip,rk3228-pinctrl";
744 rockchip,grf = <&grf>;
745 #address-cells = <1>;
749 gpio0: gpio0@11110000 {
750 compatible = "rockchip,gpio-bank";
751 reg = <0x11110000 0x100>;
752 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&clk_gates9 9>;
758 interrupt-controller;
759 #interrupt-cells = <2>;
762 gpio1: gpio1@11120000 {
763 compatible = "rockchip,gpio-bank";
764 reg = <0x11120000 0x100>;
765 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&clk_gates9 9>;
771 interrupt-controller;
772 #interrupt-cells = <2>;
775 gpio2: gpio2@11130000 {
776 compatible = "rockchip,gpio-bank";
777 reg = <0x11130000 0x100>;
778 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clk_gates9 10>;
784 interrupt-controller;
785 #interrupt-cells = <2>;
788 gpio3: gpio3@11140000 {
789 compatible = "rockchip,gpio-bank";
790 reg = <0x11140000 0x100>;
791 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clk_gates9 11>;
797 interrupt-controller;
798 #interrupt-cells = <2>;
801 pcfg_pull_up: pcfg-pull-up {
805 pcfg_pull_down: pcfg-pull-down {
809 pcfg_pull_none: pcfg-pull-none {
813 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
814 drive-strength = <8>;
817 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
818 drive-strength = <12>;
821 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
823 drive-strength = <8>;
826 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
827 drive-strength = <4>;
830 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
832 drive-strength = <4>;
835 pcfg_pull_down_drv_12ma: pcfg-pull-down-drv-12ma {
837 drive-strength = <12>;
840 pcfg_output_high: pcfg-output-high {
844 pcfg_output_low: pcfg-output-low {
848 pcfg_input_high: pcfg-input-high {
854 i2c0_xfer: i2c0-xfer {
855 rockchip,pins = <0 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,
856 <0 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>;
858 i2c0_gpio: i2c0-gpio {
859 rockchip,pins = <0 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_none>,
860 <0 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_none>;
862 i2c0_sleep: i2c0-sleep {
863 rockchip,pins = <0 GPIO_A0 RK_FUNC_GPIO &pcfg_input_high>,
864 <0 GPIO_A1 RK_FUNC_GPIO &pcfg_input_high>;
869 i2c1_xfer: i2c1-xfer {
870 rockchip,pins = <0 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,
871 <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
873 i2c1_gpio: i2c1-gpio {
874 rockchip,pins = <0 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_none>,
875 <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
877 i2c1_sleep: i2c1-sleep {
878 rockchip,pins = <0 GPIO_A2 RK_FUNC_GPIO &pcfg_input_high>,
879 <0 GPIO_A3 RK_FUNC_GPIO &pcfg_input_high>;
885 i2c2_xfer: i2c2-xfer {
886 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
887 <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
889 i2c2_gpio: i2c2-gpio {
890 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
891 <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;
893 i2c2_sleep: i2c2-sleep {
894 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
895 <2 GPIO_C4 RK_FUNC_GPIO &pcfg_input_high>;
900 i2c3_xfer: i2c3-xfer {
901 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
902 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
904 i2c3_gpio: i2c3-gpio {
905 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
906 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
908 i2c3_sleep: i2c3-sleep {
909 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
910 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
915 uart0_xfer: uart0-xfer {
916 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_up>,
917 <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
920 uart0_cts: uart0-cts {
921 rockchip,pins = <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;
924 uart0_rts: uart0-rts {
925 rockchip,pins = <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
928 uart0_rts_gpio: uart0-rts-gpio {
929 rockchip,pins = <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
934 uart1_xfer: uart1-xfer {
935 rockchip,pins = <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_up>,
936 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>;
939 uart1_cts: uart1-cts {
940 rockchip,pins = <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
943 uart1_rts: uart1-rts {
944 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;
949 uart11_xfer: uart11-xfer {
950 rockchip,pins = <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_up>,
951 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
954 uart11_cts: uart11-cts {
955 rockchip,pins = <3 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
958 uart11_rts: uart11-rts {
959 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>;
964 uart2_xfer: uart2-xfer {
965 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up>,
966 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>;
969 uart2_cts: uart2-cts {
970 rockchip,pins = <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
973 uart2_rts: uart2-rts {
974 rockchip,pins = <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>;
979 uart21_xfer: uart21-xfer {
980 rockchip,pins = <1 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
981 <1 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
987 rockchip,pins = <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
990 rockchip,pins = <0 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
993 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
996 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
999 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_up>;
1004 spi1_clk: spi1-clk {
1005 rockchip,pins = <0 GPIO_C7 RK_FUNC_2 &pcfg_pull_up>;
1007 spi1_cs0: spi1-cs0 {
1008 rockchip,pins = <2 GPIO_A2 RK_FUNC_2 &pcfg_pull_up>;
1011 rockchip,pins = <2 GPIO_A0 RK_FUNC_2 &pcfg_pull_up>;
1014 rockchip,pins = <2 GPIO_A1 RK_FUNC_2 &pcfg_pull_up>;
1016 spi1_cs1: spi1-cs1 {
1017 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_up>;
1022 i2s_mclk: i2s-mclk {
1023 rockchip,pins = <0 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
1027 rockchip,pins = <0 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>;
1030 i2s_lrckrx:i2s-lrckrx {
1031 rockchip,pins = <0 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;
1034 i2s_lrcktx:i2s-lrcktx {
1035 rockchip,pins = <0 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1039 rockchip,pins = <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1043 rockchip,pins = <0 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1047 rockchip,pins = <1 GPIO_A2 RK_FUNC_2 &pcfg_pull_none>;
1051 rockchip,pins = <1 GPIO_A4 RK_FUNC_2 &pcfg_pull_none>;
1055 rockchip,pins = <1 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1058 i2s_gpio: i2s-gpio {
1059 rockchip,pins = <0 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_none>,
1060 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>,
1061 <0 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_none>,
1062 <0 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1063 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1064 <0 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1065 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_none>,
1066 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_none>,
1067 <1 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_none>;
1072 spdif0_tx: spdif0-tx {
1073 rockchip,pins = <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1078 spdif1_tx: spdif1-tx {
1079 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>;
1084 sdmmc_clk: sdmmc-clk {
1085 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1088 sdmmc_cmd: sdmmc-cmd {
1089 rockchip,pins = <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1092 sdmmc_dectn: sdmmc-dectn {
1093 rockchip,pins = <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1096 sdmmc_wrprt: sdmmc-wrprt {
1097 rockchip,pins = <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1100 sdmmc_pwren: sdmmc-pwren {
1101 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1104 sdmmc_bus1: sdmmc-bus1 {
1105 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1108 sdmmc_bus4: sdmmc-bus4 {
1109 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1110 <1 GPIO_C3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1111 <1 GPIO_C4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1112 <1 GPIO_C5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1115 sdmmc_gpio: sdmmc-gpio {
1116 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1117 <1 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1118 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1119 <1 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1120 <1 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1121 <1 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1122 <1 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1123 <1 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1124 <1 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
1129 sdio0_bus1: sdio0-bus1 {
1130 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1133 sdio0_bus4: sdio0-bus4 {
1134 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1135 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1136 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1137 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1140 sdio0_cmd: sdio0-cmd {
1141 rockchip,pins = <0 GPIO_A3 RK_FUNC_2 &pcfg_pull_up_drv_4ma>;
1144 sdio0_clk: sdio0-clk {
1145 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1148 sdio0_pwren: sdio0-pwren {
1149 rockchip,pins = <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_up>;
1152 sdio0_gpio: sdio0-gpio {
1153 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1154 <1 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1155 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1156 <1 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1157 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1158 <1 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1159 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
1165 sdio1_bus1: sdio1-bus1 {
1166 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1169 sdio1_bus4: sdio1-bus4 {
1170 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1171 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1172 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1173 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1176 sdio1_cmd: sdio1-cmd {
1177 rockchip,pins = <0 GPIO_A3 RK_FUNC_2 &pcfg_pull_up_drv_4ma>;
1180 sdio1_clk: sdio1-clk {
1181 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1184 sdio1_pwren: sdio1-pwren {
1185 rockchip,pins = <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_up>;
1188 sdio1_gpio: sdio1-gpio {
1189 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1190 <1 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1191 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1192 <1 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1193 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1194 <1 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1195 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
1200 emmc_clk: emmc-clk {
1201 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1204 emmc_cmd: emmc-cmd {
1205 rockchip,pins = <1 GPIO_C6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1208 emmc_pwren: emmc-pwren {
1209 rockchip,pins = <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1212 emmc_rstnout: emmc_rstnout {
1213 rockchip,pins = <1 GPIO_C7 RK_FUNC_2 &pcfg_pull_none>;
1216 emmc_bus1: emmc-bus1 {
1217 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
1220 emmc_bus4: emmc-bus4 {
1221 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
1222 <1 GPIO_C3 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
1223 <1 GPIO_C4 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
1224 <1 GPIO_C5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
1229 pwm0_pin: pwm0-pin {
1230 rockchip,pins = <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1235 pwm1_pin: pwm1-pin {
1236 rockchip,pins = <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1241 pwm2_pin: pwm2-pin {
1242 rockchip,pins = <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;
1247 pwmir_pin: pwmir-pin {
1248 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1253 pwm10_pin: pwm10-pin {
1254 rockchip,pins = <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;
1259 pwm11_pin: pwm11-pin {
1260 rockchip,pins = <0 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1265 pwm12_pin: pwm12-pin {
1266 rockchip,pins = <1 GPIO_B4 RK_FUNC_2 &pcfg_pull_none>;
1271 pwm1ir_pin: pwm1ir-pin {
1272 rockchip,pins = <1 GPIO_B3 RK_FUNC_2 &pcfg_pull_none>;
1277 rgmii_pins: rgmii-pins {
1278 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,
1279 <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,
1280 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,
1281 <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1282 <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1283 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1284 <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1285 <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1286 <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1287 <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,
1288 <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1289 <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1290 <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,
1291 <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>,
1292 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
1295 rmii_pins: rmii-pins {
1296 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,
1297 <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,
1298 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,
1299 <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1300 <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1301 <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1302 <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,
1303 <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1304 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,
1305 <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1310 tsadc_int: tsadc-int {
1311 rockchip,pins = <0 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>;
1313 tsadc_gpio: tsadc-gpio {
1314 rockchip,pins = <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>;
1319 hdmi_cec: hdmi-cec {
1320 rockchip,pins = <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1323 hdmi_hpd: hdmi-hpd {
1324 rockchip,pins = <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1329 hdmii2c_xfer: hdmii2c-xfer {
1330 rockchip,pins = <0 GPIO_A6 RK_FUNC_2 &pcfg_pull_none>,
1331 <0 GPIO_A7 RK_FUNC_2 &pcfg_pull_none>;