arch/arm/boot/dts/rk3188.dtsi

   1
   2 #include "skeleton.dtsi"
   3 #include "rk3188-pinctrl.dtsi"
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5 #include "rk3188_io_vol_domain.dtsi"
   6
   7
   8 / {
   9         compatible = "rockchip,rk3188";
  10         interrupt-parent = <&gic>;
  11         rockchip,sram = <&sram>;
  12
  13         aliases {
  14                 serial0 = &uart0;
  15                 serial1 = &uart1;
  16                 serial2 = &uart2;
  17                 serial3 = &uart3;
  18                 i2c0 = &i2c0;
  19                 i2c1 = &i2c1;
  20                 i2c2 = &i2c2;
  21                 i2c3 = &i2c3;
  22                 i2c4 = &i2c4;
  23                 lcdc0 = &lcdc0;
  24                 lcdc1 = &lcdc1;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <0>;
  35                 };
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a9";
  39                         reg = <1>;
  40                 };
  41                 cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <2>;
  45                 };
  46                 cpu@3 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a9";
  49                         reg = <3>;
  50                 };
  51         };
  52
  53         twd-wdt@1013c620 {
  54                 compatible = "arm,cortex-a9-twd-wdt";
  55                 reg = <0x1013c620 0x20>;
  56                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  57         };
  58
  59         gic: interrupt-controller@1013d000 {
  60                 compatible = "arm,cortex-a9-gic";
  61                 interrupt-controller;
  62                 #interrupt-cells = <3>;
  63                 reg = <0x1013d000 0x1000>,
  64                       <0x1013c100 0x0100>;
  65         };
  66
  67         L2: cache-controller@10138000 {
  68                 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
  69                 reg = <0x10138000 0x1000>;
  70                 cache-unified;
  71                 cache-level = <2>;
  72                 arm,tag-latency = <1 1 1>;
  73                 arm,data-latency = <3 1 2>;
  74                 rockchip,prefetch-ctrl = <0x70000003>;
  75                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  76                 rockchip,power-ctrl = <0x3>;
  77 /*
  78                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  79                 (0x1 << 25) |   // Round-robin replacement
  80                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  81                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  82                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  83 */
  84                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  85         };
  86
  87         cpu_axi_bus: cpu_axi_bus@10128000 {
  88                 compatible = "rockchip,cpu_axi_bus";
  89                 reg = <0x10128000 0x8000>;
  90                 qos {
  91                         dmac {
  92                                 rockchip,offset = <0x1000>;
  93                                 rockchip,priority = <0 0>;
  94                         };
  95                         cpu0 {
  96                                 rockchip,offset = <0x2000>;
  97                                 rockchip,priority = <0 0>;
  98                         };
  99                         cpu1r {
 100                                 rockchip,offset = <0x2080>;
 101                                 rockchip,priority = <0 0>;
 102                         };
 103                         cpu1w {
 104                                 rockchip,offset = <0x2100>;
 105                                 rockchip,priority = <0 0>;
 106                         };
 107                         peri {
 108                                 rockchip,offset = <0x4000>;
 109                                 rockchip,priority = <2 2>;
 110                         };
 111                         gpu {
 112                                 rockchip,offset = <0x5000>;
 113                                 rockchip,priority = <2 1>;
 114                         };
 115                         vpu {
 116                                 rockchip,offset = <0x6000>;
 117                         };
 118                         vop0 {
 119                                 rockchip,offset = <0x7000>;
 120                                 rockchip,priority = <3 3>;
 121                         };
 122                         cif0 {
 123                                 rockchip,offset = <0x7080>;
 124                         };
 125                         ipp {
 126                                 rockchip,offset = <0x7100>;
 127                         };
 128                         vop1 {
 129                                 rockchip,offset = <0x7180>;
 130                                 rockchip,priority = <3 3>;
 131                         };
 132                         cif1 {
 133                                 rockchip,offset = <0x7200>;
 134                         };
 135                         rga {
 136                                 rockchip,offset = <0x7280>;
 137                         };
 138                 };
 139         };
 140
 141         bootrom@10120000 {
 142                 compatible = "rockchip,bootrom";
 143                 reg = <0x10120000 0x4000>;
 144         };
 145
 146         bootram@10080000 {
 147                 compatible = "rockchip,bootram";
 148                 reg = <0x10080000 0x20>; /* 32 bytes */
 149         };
 150
 151         sram: sram@10080020 {
 152                 compatible = "mmio-sram";
 153                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 154                 map-exec;
 155         };
 156
 157         pmu@20004000 {
 158                 compatible = "rockchip,pmu";
 159                 reg = <0x20004000 0x4000>;
 160         };
 161
 162         timer@20038000 {
 163                 compatible = "rockchip,timer";
 164                 reg = <0x20038000 0x20>;
 165                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 166                 rockchip,percpu = <0>;
 167         };
 168
 169         timer@20038020 {
 170                 compatible = "rockchip,timer";
 171                 reg = <0x20038020 0x20>;
 172                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 173                 rockchip,percpu = <1>;
 174         };
 175
 176         timer@20038040 {
 177                 compatible = "rockchip,timer";
 178                 reg = <0x20038040 0x20>;
 179                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 180                 rockchip,percpu = <2>;
 181         };
 182
 183         timer@20038060 {
 184                 compatible = "rockchip,timer";
 185                 reg = <0x20038060 0x20>;
 186                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 187                 rockchip,percpu = <3>;
 188         };
 189
 190         timer@20038080 {
 191                 compatible = "rockchip,timer";
 192                 reg = <0x20038080 0x20>;
 193                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 194                 rockchip,broadcast = <1>;
 195         };
 196
 197         timer@200380a0 {
 198                 compatible = "rockchip,timer";
 199                 reg = <0x200380a0 0x20>;
 200                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 201                 rockchip,clocksource = <1>;
 202         };
 203
 204         watchdog:wdt@2004c000 {
 205                 compatible = "rockchip,watch dog";
 206                 reg = <0x2004c000 0x100>;
 207                 clocks = <&clk_gates7 15>;
 208                 clock-names = "pclk_wdt";
 209                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 210                 rockchip,irq = <1>;
 211                 rockchip,timeout = <5>;
 212                 rockchip,atboot = <1>;
 213                 rockchip,debug = <0>;
 214                 status = "disabled";
 215         };
 216
 217         amba {
 218                 #address-cells = <1>;
 219                 #size-cells = <1>;
 220                 compatible = "arm,amba-bus";
 221                 interrupt-parent = <&gic>;
 222                 ranges;
 223
 224                 pdma0: pdma@20018000 {
 225                         compatible = "arm,pl330", "arm,primecell";
 226                         reg = <0x20018000 0x4000>;
 227                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 228                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 229                         #dma-cells = <1>;
 230                         #dma-channels = <9>;
 231                         #dma-requests = <10>;
 232                 };
 233
 234                 pdma1: pdma@20078000 {
 235                         compatible = "arm,pl330", "arm,primecell";
 236                         reg = <0x20078000 0x4000>;
 237                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 239                         #dma-cells = <1>;
 240                         #dma-channels = <7>;
 241                         #dma-requests = <14>;
 242                 };
 243         };
 244
 245         uart0: serial@10124000 {
 246                 compatible = "rockchip,serial";
 247                 reg = <0x10124000 0x100>;
 248                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 249                 clock-frequency = <24000000>;
 250                 reg-shift = <2>;
 251                 reg-io-width = <4>;
 252                 pinctrl-names = "default";
 253                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 254                 status = "disabled";
 255         };
 256
 257         uart1: serial@10126000 {
 258                 compatible = "rockchip,serial";
 259                 reg = <0x10126000 0x100>;
 260                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 261                 clock-frequency = <24000000>;
 262                 reg-shift = <2>;
 263                 reg-io-width = <4>;
 264                 pinctrl-names = "default";
 265                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 266                 status = "disabled";
 267         };
 268
 269         uart2: serial@20064000 {
 270                 compatible = "rockchip,serial";
 271                 reg = <0x20064000 0x100>;
 272                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 273                 clock-frequency = <24000000>;
 274                 current-speed = <115200>;
 275                 reg-shift = <2>;
 276                 reg-io-width = <4>;
 277                 pinctrl-names = "default";
 278                 pinctrl-0 = <&uart2_xfer>;
 279                 status = "disabled";
 280         };
 281
 282         uart3: serial@20068000 {
 283                 compatible = "rockchip,serial";
 284                 reg = <0x20068000 0x100>;
 285                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 286                 clock-frequency = <24000000>;
 287                 reg-shift = <2>;
 288                 reg-io-width = <4>;
 289                 pinctrl-names = "default";
 290                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 291                 status = "disabled";
 292         };
 293
 294         fiq-debugger {
 295                 compatible = "rockchip,fiq-debugger";
 296                 rockchip,serial-id = <2>;
 297                 rockchip,signal-irq = <112>;
 298                 rockchip,wake-irq = <0>;
 299                 status = "disabled";
 300         };
 301
 302         i2c0: i2c@2002d000 {
 303                 compatible = "rockchip,rk30-i2c";
 304                 reg = <0x2002d000 0x1000>;
 305                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308                 pinctrl-names = "default", "gpio";
 309                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 310                 pinctrl-1 = <&i2c0_gpio>;
 311                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 312                 clocks = <&clk_gates8 4>;
 313                 rockchip,check-idle = <1>;
 314                 status = "disabled";
 315         };
 316
 317         i2c1: i2c@2002f000 {
 318                 compatible = "rockchip,rk30-i2c";
 319                 reg = <0x2002f000 0x1000>;
 320                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 321                 #address-cells = <1>;
 322                 #size-cells = <0>;
 323                 pinctrl-names = "default", "gpio";
 324                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 325                 pinctrl-1 = <&i2c1_gpio>;
 326                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 327                 clocks = <&clk_gates8 5>;
 328                 rockchip,check-idle = <1>;
 329                 status = "disabled";
 330         };
 331
 332         i2c2: i2c@20056000 {
 333                 compatible = "rockchip,rk30-i2c";
 334                 reg = <0x20056000 0x1000>;
 335                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 336                 #address-cells = <1>;
 337                 #size-cells = <0>;
 338                 pinctrl-names = "default", "gpio";
 339                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 340                 pinctrl-1 = <&i2c2_gpio>;
 341                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 342                 clocks = <&clk_gates8 6>;
 343                 rockchip,check-idle = <1>;
 344                 status = "disabled";
 345         };
 346
 347         i2c3: i2c@2005a000 {
 348                 compatible = "rockchip,rk30-i2c";
 349                 reg = <0x2005a000 0x1000>;
 350                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 351                 #address-cells = <1>;
 352                 #size-cells = <0>;
 353                 pinctrl-names = "default", "gpio";
 354                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 355                 pinctrl-1 = <&i2c3_gpio>;
 356                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 357                 clocks = <&clk_gates8 7>;
 358                 rockchip,check-idle = <1>;
 359                 status = "disabled";
 360         };
 361
 362         i2c4: i2c@2005e000 {
 363                 compatible = "rockchip,rk30-i2c";
 364                 reg = <0x2005e000 0x1000>;
 365                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 pinctrl-names = "default", "gpio";
 369                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 370                 pinctrl-1 = <&i2c4_gpio>;
 371                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 372                 clocks = <&clk_gates8 8>;
 373                 rockchip,check-idle = <1>;
 374                 status = "disabled";
 375         };
 376
 377         clocks-init{
 378                 compatible = "rockchip,clocks-init";
 379                 rockchip,clocks-init-parent =
 380                         <&clk_core &clk_apll>,  <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
 381                         <&aclk_peri_mux &clk_gpll>,     <&clk_i2s_pll_mux &clk_cpll>,
 382                         <&clk_uart_pll_mux &clk_gpll>;
 383                 rockchip,clocks-init-rate =
 384                         <&clk_core 792000000>,  <&clk_gpll 768000000>,
 385                         <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
 386                         <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
 387                         <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
 388                         <&hclk_peri 96000000>,  <&pclk_peri 48000000>,
 389                         <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
 390                         <&aclk_lcdc1 300000000>;
 391         };
 392
 393         fb: fb{
 394                 compatible = "rockchip,rk-fb";
 395                 rockchip,disp-mode = <DUAL>;
 396         };
 397
 398         nandc: nandc {
 399                 compatible = "rockchip,rk-nandc";
 400                 reg = <0x10050000 0x4000>;
 401                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 402         };
 403
 404         lcdc0:lcdc@1010c000 {
 405                 compatible = "rockchip,rk3188-lcdc";
 406                 rockchip,prop = <PRMRY>;
 407                 rochchip,pwr18 = <0>;
 408                 reg = <0x1010c000 0x1000>;
 409                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 410                 status = "disabled";
 411         };
 412
 413         lcdc1:lcdc@1010e000 {
 414                 compatible = "rockchip,rk3188-lcdc";
 415                 rockchip,prop = <EXTEND>;
 416                 rockchip,pwr18 = <0>;
 417                 reg = <0x1010e000 0x1000>;
 418                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 419                 pinctrl-names = "default", "gpio";
 420                 pinctrl-0 = <&lcdc1_lcdc>;
 421                 pinctrl-1 = <&lcdc1_gpio>;
 422                 status = "disabled";
 423   };
 424   rga@10114000 {
 425                 compatible = "rockchip,rga";
 426                 reg = <0x10114000 0x1000>;
 427                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 428                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 429     clock-names = "hclk_rga", "aclk_rga";
 430                 status = "disabled";
 431         };
 432
 433     adc: adc@2006c000 {
 434            compatible = "rockchip,saradc";
 435            reg = <0x2006c000 0x100>;
 436            interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 437            #io-channel-cells = <1>;
 438            io-channel-ranges;
 439            rockchip,adc-vref = <1800>;
 440            clock-frequency = <1000000>;
 441            clocks = <&clk_saradc>, <&clk_gates7 14>;
 442            clock-names = "saradc", "pclk_saradc";
 443            status = "disabled";
 444     };
 445
 446         spdif: rockchip-spdif@0x1011e000 {
 447                 compatible = "rockchip-spdif";
 448                 reg = <0x1011e000 0x2000>;
 449                 clocks = <&clk_spdif>;
 450                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 451                 dmas = <&pdma0 8>;
 452                 #dma-cells = <1>;
 453                 dma-names = "tx";
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&spdif_tx>;
 456         };
 457
 458         i2s1: rockchip-i2s@0x1011a000 {
 459                 compatible = "rockchip-i2s";
 460                 reg = <0x1011a000 0x2000>;
 461                 i2s-id = <1>;
 462                 clocks = <&clk_i2s>;
 463                 clock-names = "i2s_clk";
 464                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 465                 dmas = <&pdma0 6>,
 466                         <&pdma0 7>;
 467                 #dma-cells = <2>;
 468                 dma-names = "tx", "rx";
 469                 pinctrl-names = "default", "sleep";
 470                 pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 471                 pinctrl-1 = <&i2s0_gpio>;
 472         };
 473
 474         pwm0: pwm@20030000{
 475                 compatible = "rockchip,pwm";
 476                 reg = <0x20030000 0x10>;
 477                 #pwm-cells = <2>;
 478                 pinctrl-names = "default";
 479                 pinctrl-0 = <&pwm0_pin>;
 480                 status = "disabled";
 481
 482         };
 483
 484         pwm1: pwm@20030010{
 485                 compatible = "rockchip,pwm";
 486                 reg = <0x20030010 0x10>; /*0x20030000*/
 487                 #pwm-cells = <2>;
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&pwm1_pin>;
 490                 status = "disabled";
 491
 492         };
 493         pwm2: pwm@20050020{
 494                 compatible = "rockchip,pwm";
 495                 reg = <0x20050020 0x10>; /*0x20030000*/
 496                 #pwm-cells = <2>;
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&pwm2_pin>;
 499                 status = "disabled";
 500
 501         };
 502
 503         pwm3: pwm@20050030{
 504                 compatible = "rockchip,pwm";
 505                 reg = <0x20050030 0x10>; /*0x20030000*/
 506                 #pwm-cells = <2>;
 507                 pinctrl-names = "default";
 508                 pinctrl-0 = <&pwm3_pin>;
 509                 status = "disabled";
 510
 511         };
 512         dvfs {
 513                 vd_cpu:
 514                 vd_cpu {
 515                         regulator_name="vdd_arm";
 516                         suspend_volt=<1000>; //mV
 517                         pd_a9 {
 518                                 clk_core_dvfs_table:
 519                                 clk_core {
 520                                         operating-points = <
 521                                                 /* KHz    uV */
 522                                                 312000 900000
 523                                                 504000 950000
 524                                                 816000 1000000
 525                                                 1008000 1100000
 526                                                 1200000 1200000
 527                                                 1416000 1300000
 528                                                 1608000 1350000
 529                                                 >;
 530                                 };
 531                         };
 532                 };
 533
 534                 vd_core:
 535                 vd_core {
 536                         regulator_name="vdd_logic";
 537                         suspend_volt=<1000>; //mV
 538
 539                         pd_gpu {
 540                                 clk_gpu_dvfs_table:
 541                                 clk_gpu {
 542                                         operating-points = <
 543                                                 /* KHz    uV */
 544                                                 200000 1200000
 545                                                 300000 1200000
 546                                                 400000 1200000
 547                                                 >;
 548                                 };
 549                         };
 550
 551                         pd_ddr {
 552                                 clk_ddr_dvfs_table:
 553                                 clk_ddr {
 554                                         operating-points = <
 555                                                 /* KHz    uV */
 556                                                 200000 1200000
 557                                                 300000 1200000
 558                                                 400000 1200000
 559                                                 >;
 560                                 };
 561                         };
 562                 };
 563         };
 564         ion: ion{
 565                 compatible = "rockchip,ion";
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 rockchip,ion-heap@1 { /* CMA HEAP */
 569                         reg = <1>;
 570                 };
 571                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 572                         reg = <3>;
 573                 };
 574         };
 575
 576         dwc_control_usb: dwc-control-usb@0x200080ac {
 577                 compatible = "rockchip,dwc-control-usb";
 578                 reg = <0x200080ac 0x4>,
 579                       <0x2000810c 0x10>,
 580                       <0x2000811c 0x10>,
 581                       <0x2000812c 0x8>,
 582                       <0x20008138 0x8>;
 583                 reg-names = "GRF_SOC_STATUS0",
 584                             "GRF_UOC0_BASE",
 585                             "GRF_UOC1_BASE",
 586                             "GRF_UOC2_BASE",
 587                             "GRF_UOC3_BASE";
 588                 gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 589                 clocks = <&clk_gates4 5>;
 590                 clock-names = "hclk_usb_peri";
 591         };
 592
 593         usb@10180000 {
 594                 compatible = "rockchip,usb20_otg";
 595                 reg = <0x10180000 0x40000>;
 596                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 597                 clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;
 598                 clock-names = "otgphy0", "hclk_otg0";
 599         };
 600
 601         usb@101c0000 {
 602                 compatible = "rockchip,usb20_host";
 603                 reg = <0x101c0000 0x40000>;
 604                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 605                 clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;
 606                 clock-names = "otgphy1", "hclk_otg1";
 607         };
 608
 609         hsic@10240000 {
 610                 compatible = "rockchip,rk_hsic_host";
 611                 reg = <0x10240000 0x40000>;
 612                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 613                 clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
 614                          <&clk_hsicphy12m>, <&clk_otgphy1_480m>;
 615                 clock-names = "hsicphy480m", "hclk_hsic",
 616                               "hsicphy12m", "hsic_otgphy1";
 617         };
 618
 619 };