arch/arm/boot/dts/rk3188.dtsi

   1
   2 #include "skeleton.dtsi"
   3 #include "rk3188-pinctrl.dtsi"
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5 #include "rk3188_io_vol_domain.dtsi"
   6
   7
   8 / {
   9         compatible = "rockchip,rk3188";
  10         interrupt-parent = <&gic>;
  11         rockchip,sram = <&sram>;
  12
  13         aliases {
  14                 serial0 = &uart0;
  15                 serial1 = &uart1;
  16                 serial2 = &uart2;
  17                 serial3 = &uart3;
  18                 i2c0 = &i2c0;
  19                 i2c1 = &i2c1;
  20                 i2c2 = &i2c2;
  21                 i2c3 = &i2c3;
  22                 i2c4 = &i2c4;
  23                 lcdc0 = &lcdc0;
  24                 lcdc1 = &lcdc1;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <0>;
  35                 };
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a9";
  39                         reg = <1>;
  40                 };
  41                 cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <2>;
  45                 };
  46                 cpu@3 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a9";
  49                         reg = <3>;
  50                 };
  51         };
  52
  53         twd-wdt@1013c620 {
  54                 compatible = "arm,cortex-a9-twd-wdt";
  55                 reg = <0x1013c620 0x20>;
  56                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  57         };
  58
  59         gic: interrupt-controller@1013d000 {
  60                 compatible = "arm,cortex-a9-gic";
  61                 interrupt-controller;
  62                 #interrupt-cells = <3>;
  63                 reg = <0x1013d000 0x1000>,
  64                       <0x1013c100 0x0100>;
  65         };
  66
  67         L2: cache-controller@10138000 {
  68                 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
  69                 reg = <0x10138000 0x1000>;
  70                 cache-unified;
  71                 cache-level = <2>;
  72                 arm,tag-latency = <1 1 1>;
  73                 arm,data-latency = <3 1 2>;
  74                 rockchip,prefetch-ctrl = <0x70000003>;
  75                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  76                 rockchip,power-ctrl = <0x3>;
  77 /*
  78                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  79                 (0x1 << 25) |   // Round-robin replacement
  80                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  81                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  82                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  83 */
  84                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  85         };
  86
  87         cpu_axi_bus: cpu_axi_bus@10128000 {
  88                 compatible = "rockchip,cpu_axi_bus";
  89                 reg = <0x10128000 0x8000>;
  90                 qos {
  91                         dmac {
  92                                 rockchip,offset = <0x1000>;
  93                                 rockchip,priority = <0 0>;
  94                         };
  95                         cpu0 {
  96                                 rockchip,offset = <0x2000>;
  97                                 rockchip,priority = <0 0>;
  98                         };
  99                         cpu1r {
 100                                 rockchip,offset = <0x2080>;
 101                                 rockchip,priority = <0 0>;
 102                         };
 103                         cpu1w {
 104                                 rockchip,offset = <0x2100>;
 105                                 rockchip,priority = <0 0>;
 106                         };
 107                         peri {
 108                                 rockchip,offset = <0x4000>;
 109                                 rockchip,priority = <2 2>;
 110                         };
 111                         gpu {
 112                                 rockchip,offset = <0x5000>;
 113                                 rockchip,priority = <2 1>;
 114                         };
 115                         vpu {
 116                                 rockchip,offset = <0x6000>;
 117                         };
 118                         vop0 {
 119                                 rockchip,offset = <0x7000>;
 120                                 rockchip,priority = <3 3>;
 121                         };
 122                         cif0 {
 123                                 rockchip,offset = <0x7080>;
 124                         };
 125                         ipp {
 126                                 rockchip,offset = <0x7100>;
 127                         };
 128                         vop1 {
 129                                 rockchip,offset = <0x7180>;
 130                                 rockchip,priority = <3 3>;
 131                         };
 132                         cif1 {
 133                                 rockchip,offset = <0x7200>;
 134                         };
 135                         rga {
 136                                 rockchip,offset = <0x7280>;
 137                         };
 138                 };
 139         };
 140
 141         bootrom@10120000 {
 142                 compatible = "rockchip,bootrom";
 143                 reg = <0x10120000 0x4000>;
 144         };
 145
 146         bootram@10080000 {
 147                 compatible = "rockchip,bootram";
 148                 reg = <0x10080000 0x20>; /* 32 bytes */
 149         };
 150
 151         sram: sram@10080020 {
 152                 compatible = "mmio-sram";
 153                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 154                 map-exec;
 155         };
 156
 157         pmu@20004000 {
 158                 compatible = "rockchip,pmu";
 159                 reg = <0x20004000 0x4000>;
 160         };
 161
 162         timer@20038000 {
 163                 compatible = "rockchip,timer";
 164                 reg = <0x20038000 0x20>;
 165                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 166                 rockchip,percpu = <0>;
 167         };
 168
 169         timer@20038020 {
 170                 compatible = "rockchip,timer";
 171                 reg = <0x20038020 0x20>;
 172                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 173                 rockchip,percpu = <1>;
 174         };
 175
 176         timer@20038040 {
 177                 compatible = "rockchip,timer";
 178                 reg = <0x20038040 0x20>;
 179                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 180                 rockchip,percpu = <2>;
 181         };
 182
 183         timer@20038060 {
 184                 compatible = "rockchip,timer";
 185                 reg = <0x20038060 0x20>;
 186                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 187                 rockchip,percpu = <3>;
 188         };
 189
 190         timer@20038080 {
 191                 compatible = "rockchip,timer";
 192                 reg = <0x20038080 0x20>;
 193                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 194                 rockchip,broadcast = <1>;
 195         };
 196
 197         timer@200380a0 {
 198                 compatible = "rockchip,timer";
 199                 reg = <0x200380a0 0x20>;
 200                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 201                 rockchip,clocksource = <1>;
 202         };
 203
 204         amba {
 205                 #address-cells = <1>;
 206                 #size-cells = <1>;
 207                 compatible = "arm,amba-bus";
 208                 interrupt-parent = <&gic>;
 209                 ranges;
 210
 211                 pdma0: pdma@20018000 {
 212                         compatible = "arm,pl330", "arm,primecell";
 213                         reg = <0x20018000 0x4000>;
 214                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 216                         #dma-cells = <1>;
 217                         #dma-channels = <9>;
 218                         #dma-requests = <10>;
 219                 };
 220
 221                 pdma1: pdma@20078000 {
 222                         compatible = "arm,pl330", "arm,primecell";
 223                         reg = <0x20078000 0x4000>;
 224                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 226                         #dma-cells = <1>;
 227                         #dma-channels = <7>;
 228                         #dma-requests = <14>;
 229                 };
 230         };
 231
 232         uart0: serial@10124000 {
 233                 compatible = "rockchip,serial";
 234                 reg = <0x10124000 0x100>;
 235                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 236                 clock-frequency = <24000000>;
 237                 reg-shift = <2>;
 238                 reg-io-width = <4>;
 239                 pinctrl-names = "default";
 240                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 241                 status = "disabled";
 242         };
 243
 244         uart1: serial@10126000 {
 245                 compatible = "rockchip,serial";
 246                 reg = <0x10126000 0x100>;
 247                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 248                 clock-frequency = <24000000>;
 249                 reg-shift = <2>;
 250                 reg-io-width = <4>;
 251                 pinctrl-names = "default";
 252                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 253                 status = "disabled";
 254         };
 255
 256         uart2: serial@20064000 {
 257                 compatible = "rockchip,serial";
 258                 reg = <0x20064000 0x100>;
 259                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 260                 clock-frequency = <24000000>;
 261                 current-speed = <115200>;
 262                 reg-shift = <2>;
 263                 reg-io-width = <4>;
 264                 pinctrl-names = "default";
 265                 pinctrl-0 = <&uart2_xfer>;
 266                 status = "disabled";
 267         };
 268
 269         uart3: serial@20068000 {
 270                 compatible = "rockchip,serial";
 271                 reg = <0x20068000 0x100>;
 272                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 273                 clock-frequency = <24000000>;
 274                 reg-shift = <2>;
 275                 reg-io-width = <4>;
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 278                 status = "disabled";
 279         };
 280
 281         fiq-debugger {
 282                 compatible = "rockchip,fiq-debugger";
 283                 rockchip,serial-id = <2>;
 284                 rockchip,signal-irq = <112>;
 285                 rockchip,wake-irq = <0>;
 286                 status = "disabled";
 287         };
 288
 289         i2c0: i2c@2002d000 {
 290                 compatible = "rockchip,rk30-i2c";
 291                 reg = <0x2002d000 0x1000>;
 292                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 293                 #address-cells = <1>;
 294                 #size-cells = <0>;
 295                 pinctrl-names = "default", "gpio";
 296                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 297                 pinctrl-1 = <&i2c0_gpio>;
 298                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 299                 clocks = <&clk_gates8 4>;
 300                 rockchip,check-idle = <1>;
 301                 status = "disabled";
 302         };
 303
 304         i2c1: i2c@2002f000 {
 305                 compatible = "rockchip,rk30-i2c";
 306                 reg = <0x2002f000 0x1000>;
 307                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 pinctrl-names = "default", "gpio";
 311                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 312                 pinctrl-1 = <&i2c1_gpio>;
 313                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 314                 clocks = <&clk_gates8 5>;
 315                 rockchip,check-idle = <1>;
 316                 status = "disabled";
 317         };
 318
 319         i2c2: i2c@20056000 {
 320                 compatible = "rockchip,rk30-i2c";
 321                 reg = <0x20056000 0x1000>;
 322                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 pinctrl-names = "default", "gpio";
 326                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 327                 pinctrl-1 = <&i2c2_gpio>;
 328                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 329                 clocks = <&clk_gates8 6>;
 330                 rockchip,check-idle = <1>;
 331                 status = "disabled";
 332         };
 333
 334         i2c3: i2c@2005a000 {
 335                 compatible = "rockchip,rk30-i2c";
 336                 reg = <0x2005a000 0x1000>;
 337                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 pinctrl-names = "default", "gpio";
 341                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 342                 pinctrl-1 = <&i2c3_gpio>;
 343                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 344                 clocks = <&clk_gates8 7>;
 345                 rockchip,check-idle = <1>;
 346                 status = "disabled";
 347         };
 348
 349         i2c4: i2c@2005e000 {
 350                 compatible = "rockchip,rk30-i2c";
 351                 reg = <0x2005e000 0x1000>;
 352                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 pinctrl-names = "default", "gpio";
 356                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 357                 pinctrl-1 = <&i2c4_gpio>;
 358                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 359                 clocks = <&clk_gates8 8>;
 360                 rockchip,check-idle = <1>;
 361                 status = "disabled";
 362         };
 363
 364         clocks-init{
 365                 compatible = "rockchip,clocks-init";
 366                 rockchip,clocks-init-parent =
 367                         <&clk_core &clk_apll>,  <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
 368                         <&aclk_peri_mux &clk_gpll>,     <&clk_i2s_pll_mux &clk_cpll>,
 369                         <&clk_uart_pll_mux &clk_gpll>;
 370                 rockchip,clocks-init-rate =
 371                         <&clk_core 792000000>,  <&clk_gpll 768000000>,
 372                         <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
 373                         <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
 374                         <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
 375                         <&hclk_peri 96000000>,  <&pclk_peri 48000000>,
 376                         <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
 377                         <&aclk_lcdc1 300000000>;
 378         };
 379
 380         fb: fb{
 381                 compatible = "rockchip,rk-fb";
 382                 rockchip,disp-mode = <DUAL>;
 383         };
 384
 385         nandc: nandc {
 386                 compatible = "rockchip,rk-nandc";
 387                 reg = <0x10050000 0x4000>;
 388                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 389         };
 390
 391         lcdc0:lcdc@1010c000 {
 392                 compatible = "rockchip,rk3188-lcdc";
 393                 rockchip,prop = <PRMRY>;
 394                 rochchip,pwr18 = <0>;
 395                 reg = <0x1010c000 0x1000>;
 396                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 397                 status = "disabled";
 398         };
 399
 400         lcdc1:lcdc@1010e000 {
 401                 compatible = "rockchip,rk3188-lcdc";
 402                 rockchip,prop = <EXTEND>;
 403                 rockchip,pwr18 = <0>;
 404                 reg = <0x1010e000 0x1000>;
 405                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 406                 pinctrl-names = "default", "gpio";
 407                 pinctrl-0 = <&lcdc1_lcdc>;
 408                 pinctrl-1 = <&lcdc1_gpio>;
 409                 status = "disabled";
 410         };
 411
 412     adc: adc@2006c000 {
 413            compatible = "rockchip,saradc";
 414            reg = <0x2006c000 0x100>;
 415            interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 416            #io-channel-cells = <1>;
 417            io-channel-ranges;
 418            rockchip,adc-vref = <1800>;
 419            clock-frequency = <1000000>;
 420            clocks = <&clk_saradc>, <&clk_gates7 14>;
 421            clock-names = "saradc", "pclk_saradc";
 422            status = "disabled";
 423     };
 424
 425         spdif: rockchip-spdif@0x1011e000 {
 426                 compatible = "rockchip-spdif";
 427                 reg = <0x1011e000 0x2000>;
 428                 clocks = <&clk_spdif>;
 429                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 430                 dmas = <&pdma0 8>;
 431                 #dma-cells = <1>;
 432                 dma-names = "tx";
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&spdif_tx>;
 435         };
 436
 437         i2s1: rockchip-i2s@0x1011a000 {
 438                 compatible = "rockchip-i2s";
 439                 reg = <0x1011a000 0x2000>;
 440                 i2s-id = <1>;
 441                 clocks = <&clk_i2s>;
 442                 clock-names = "i2s_clk";
 443                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 444                 dmas = <&pdma0 6>,
 445                         <&pdma0 7>;
 446                 #dma-cells = <2>;
 447                 dma-names = "tx", "rx";
 448                 pinctrl-names = "default", "sleep";
 449                 pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 450                 pinctrl-1 = <&i2s0_gpio>;
 451         };
 452
 453         pwm0: pwm@20030000{
 454                 compatible = "rockchip,pwm";
 455                 reg = <0x20030000 0x10>;
 456                 #pwm-cells = <2>;
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&pwm0_pin>;
 459                 status = "disabled";
 460
 461         };
 462
 463         pwm1: pwm@20030010{
 464                 compatible = "rockchip,pwm";
 465                 reg = <0x20030010 0x10>; /*0x20030000*/
 466                 #pwm-cells = <2>;
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&pwm1_pin>;
 469                 status = "disabled";
 470
 471         };
 472         pwm2: pwm@20050020{
 473                 compatible = "rockchip,pwm";
 474                 reg = <0x20050020 0x10>; /*0x20030000*/
 475                 #pwm-cells = <2>;
 476                 pinctrl-names = "default";
 477                 pinctrl-0 = <&pwm2_pin>;
 478                 status = "disabled";
 479
 480         };
 481
 482         pwm3: pwm@20050030{
 483                 compatible = "rockchip,pwm";
 484                 reg = <0x20050030 0x10>; /*0x20030000*/
 485                 #pwm-cells = <2>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&pwm3_pin>;
 488                 status = "disabled";
 489
 490         };
 491         dvfs {
 492                 vd_cpu:
 493                 vd_cpu {
 494                         regulator_name="vdd_arm";
 495                         suspend_volt=<1000>; //mV
 496                         pd_a9 {
 497                                 clk_core_dvfs_table:
 498                                 clk_core {
 499                                         operating-points = <
 500                                                 /* KHz    uV */
 501                                                 312000 900000
 502                                                 504000 950000
 503                                                 816000 1000000
 504                                                 1008000 1100000
 505                                                 1200000 1200000
 506                                                 1416000 1300000
 507                                                 1608000 1350000
 508                                                 >;
 509                                 };
 510                         };
 511                 };
 512
 513                 vd_core:
 514                 vd_core {
 515                         regulator_name="vdd_logic";
 516                         suspend_volt=<1000>; //mV
 517
 518                         pd_gpu {
 519                                 clk_gpu_dvfs_table:
 520                                 clk_gpu {
 521                                         operating-points = <
 522                                                 /* KHz    uV */
 523                                                 200000 1200000
 524                                                 300000 1200000
 525                                                 400000 1200000
 526                                                 >;
 527                                 };
 528                         };
 529
 530                         pd_ddr {
 531                                 clk_ddr_dvfs_table:
 532                                 clk_ddr {
 533                                         operating-points = <
 534                                                 /* KHz    uV */
 535                                                 200000 1200000
 536                                                 300000 1200000
 537                                                 400000 1200000
 538                                                 >;
 539                                 };
 540                         };
 541                 };
 542         };
 543         ion: ion{
 544                 compatible = "rockchip,ion";
 545                 #address-cells = <1>;
 546                 #size-cells = <0>;
 547                 rockchip,ion-heap@1 { /* CMA HEAP */
 548                         reg = <1>;
 549                 };
 550                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 551                         reg = <3>;
 552                 };
 553         };
 554
 555         dwc_control_usb: dwc-control-usb@0x200080ac {
 556                 compatible = "rockchip,dwc-control-usb";
 557                 reg = <0x200080ac 0x4>,
 558                       <0x2000810c 0x10>,
 559                       <0x2000811c 0x10>;
 560                 reg-names = "GRF_SOC_STATUS0",
 561                             "GRF_UOC0_BASE",
 562                             "GRF_UOC1_BASE";
 563                 gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 564         };
 565
 566         usb@10180000 {
 567                 compatible = "rockchip,usb20_otg";
 568                 reg = <0x10180000 0x40000>;
 569                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 570                 /*clocks = <&clk_gates1 5>, <&clk_gates5 13>;*/
 571                 /*clock-names = "otgphy0", "hclk_otg0"*/
 572         };
 573
 574         usb@101c0000 {
 575                 compatible = "rockchip,usb20_host";
 576                 reg = <0x101c0000 0x40000>;
 577                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 578                 /*clocks = <&clk_gates1 6>, <&clk_gates7 3>;*/
 579                 /*clock-names = "otgphy1", "hclk_otg1"*/
 580         };
 581
 582 };