2 #include "skeleton.dtsi"
3 #include "rk3188-pinctrl.dtsi"
4 #include <dt-bindings/rkfb/rk_fb.h>
5 #include "rk3188_io_vol_domain.dtsi"
9 compatible = "rockchip,rk3188";
10 interrupt-parent = <&gic>;
11 rockchip,sram = <&sram>;
33 compatible = "arm,cortex-a9";
38 compatible = "arm,cortex-a9";
43 compatible = "arm,cortex-a9";
48 compatible = "arm,cortex-a9";
54 compatible = "arm,cortex-a9-twd-wdt";
55 reg = <0x1013c620 0x20>;
56 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
59 gic: interrupt-controller@1013d000 {
60 compatible = "arm,cortex-a9-gic";
62 #interrupt-cells = <3>;
63 reg = <0x1013d000 0x1000>,
67 L2: cache-controller@10138000 {
68 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
69 reg = <0x10138000 0x1000>;
72 arm,tag-latency = <1 1 1>;
73 arm,data-latency = <3 1 2>;
74 rockchip,prefetch-ctrl = <0x70000003>;
75 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
76 rockchip,power-ctrl = <0x3>;
78 (0x1 << 0) | // Full line of write zero behavior Enabled
79 (0x1 << 25) | // Round-robin replacement
80 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
81 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
82 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
84 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
87 cpu_axi_bus: cpu_axi_bus@10128000 {
88 compatible = "rockchip,cpu_axi_bus";
89 reg = <0x10128000 0x8000>;
92 rockchip,offset = <0x1000>;
93 rockchip,priority = <0 0>;
96 rockchip,offset = <0x2000>;
97 rockchip,priority = <0 0>;
100 rockchip,offset = <0x2080>;
101 rockchip,priority = <0 0>;
104 rockchip,offset = <0x2100>;
105 rockchip,priority = <0 0>;
108 rockchip,offset = <0x4000>;
109 rockchip,priority = <2 2>;
112 rockchip,offset = <0x5000>;
113 rockchip,priority = <2 1>;
116 rockchip,offset = <0x6000>;
119 rockchip,offset = <0x7000>;
120 rockchip,priority = <3 3>;
123 rockchip,offset = <0x7080>;
126 rockchip,offset = <0x7100>;
129 rockchip,offset = <0x7180>;
130 rockchip,priority = <3 3>;
133 rockchip,offset = <0x7200>;
136 rockchip,offset = <0x7280>;
142 compatible = "rockchip,bootrom";
143 reg = <0x10120000 0x4000>;
147 compatible = "rockchip,bootram";
148 reg = <0x10080000 0x20>; /* 32 bytes */
151 sram: sram@10080020 {
152 compatible = "mmio-sram";
153 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
158 compatible = "rockchip,pmu";
159 reg = <0x20004000 0x4000>;
163 compatible = "rockchip,timer";
164 reg = <0x20038000 0x20>;
165 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
166 rockchip,percpu = <0>;
170 compatible = "rockchip,timer";
171 reg = <0x20038020 0x20>;
172 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
173 rockchip,percpu = <1>;
177 compatible = "rockchip,timer";
178 reg = <0x20038040 0x20>;
179 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
180 rockchip,percpu = <2>;
184 compatible = "rockchip,timer";
185 reg = <0x20038060 0x20>;
186 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
187 rockchip,percpu = <3>;
191 compatible = "rockchip,timer";
192 reg = <0x20038080 0x20>;
193 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
194 rockchip,broadcast = <1>;
198 compatible = "rockchip,timer";
199 reg = <0x200380a0 0x20>;
200 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
201 rockchip,clocksource = <1>;
205 #address-cells = <1>;
207 compatible = "arm,amba-bus";
208 interrupt-parent = <&gic>;
211 pdma0: pdma@20018000 {
212 compatible = "arm,pl330", "arm,primecell";
213 reg = <0x20018000 0x4000>;
214 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
218 #dma-requests = <10>;
221 pdma1: pdma@20078000 {
222 compatible = "arm,pl330", "arm,primecell";
223 reg = <0x20078000 0x4000>;
224 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
228 #dma-requests = <14>;
232 uart0: serial@10124000 {
233 compatible = "rockchip,serial";
234 reg = <0x10124000 0x100>;
235 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
236 clock-frequency = <24000000>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
244 uart1: serial@10126000 {
245 compatible = "rockchip,serial";
246 reg = <0x10126000 0x100>;
247 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
248 clock-frequency = <24000000>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
256 uart2: serial@20064000 {
257 compatible = "rockchip,serial";
258 reg = <0x20064000 0x100>;
259 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
260 clock-frequency = <24000000>;
261 current-speed = <115200>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&uart2_xfer>;
269 uart3: serial@20068000 {
270 compatible = "rockchip,serial";
271 reg = <0x20068000 0x100>;
272 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
273 clock-frequency = <24000000>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
282 compatible = "rockchip,fiq-debugger";
283 rockchip,serial-id = <2>;
284 rockchip,signal-irq = <112>;
285 rockchip,wake-irq = <0>;
290 compatible = "rockchip,rk30-i2c";
291 reg = <0x2002d000 0x1000>;
292 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
293 #address-cells = <1>;
295 pinctrl-names = "default", "gpio";
296 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
297 pinctrl-1 = <&i2c0_gpio>;
298 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
299 clocks = <&clk_gates8 4>;
300 rockchip,check-idle = <1>;
305 compatible = "rockchip,rk30-i2c";
306 reg = <0x2002f000 0x1000>;
307 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
308 #address-cells = <1>;
310 pinctrl-names = "default", "gpio";
311 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
312 pinctrl-1 = <&i2c1_gpio>;
313 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
314 clocks = <&clk_gates8 5>;
315 rockchip,check-idle = <1>;
320 compatible = "rockchip,rk30-i2c";
321 reg = <0x20056000 0x1000>;
322 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
323 #address-cells = <1>;
325 pinctrl-names = "default", "gpio";
326 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
327 pinctrl-1 = <&i2c2_gpio>;
328 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
329 clocks = <&clk_gates8 6>;
330 rockchip,check-idle = <1>;
335 compatible = "rockchip,rk30-i2c";
336 reg = <0x2005a000 0x1000>;
337 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
340 pinctrl-names = "default", "gpio";
341 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
342 pinctrl-1 = <&i2c3_gpio>;
343 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
344 clocks = <&clk_gates8 7>;
345 rockchip,check-idle = <1>;
350 compatible = "rockchip,rk30-i2c";
351 reg = <0x2005e000 0x1000>;
352 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
355 pinctrl-names = "default", "gpio";
356 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
357 pinctrl-1 = <&i2c4_gpio>;
358 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
359 clocks = <&clk_gates8 8>;
360 rockchip,check-idle = <1>;
365 compatible = "rockchip,clocks-init";
366 rockchip,clocks-init-parent =
367 <&clk_core &clk_apll>, <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
368 <&aclk_peri_mux &clk_gpll>, <&clk_i2s_pll_mux &clk_cpll>,
369 <&clk_uart_pll_mux &clk_gpll>;
370 rockchip,clocks-init-rate =
371 <&clk_core 792000000>, <&clk_gpll 768000000>,
372 <&clk_cpll 594000000>, <&aclk_cpu 192000000>,
373 <&hclk_cpu 96000000>, <&pclk_cpu 48000000>,
374 <&pclk_ahb2apb 48000000>, <&aclk_peri 192000000>,
375 <&hclk_peri 96000000>, <&pclk_peri 48000000>,
376 <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
377 <&aclk_lcdc1 300000000>;
381 compatible = "rockchip,rk-fb";
382 rockchip,disp-mode = <DUAL>;
386 compatible = "rockchip,rk-nandc";
387 reg = <0x10050000 0x4000>;
388 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
391 lcdc0:lcdc@1010c000 {
392 compatible = "rockchip,rk3188-lcdc";
393 rockchip,prop = <PRMRY>;
394 rochchip,pwr18 = <0>;
395 reg = <0x1010c000 0x1000>;
396 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
400 lcdc1:lcdc@1010e000 {
401 compatible = "rockchip,rk3188-lcdc";
402 rockchip,prop = <EXTEND>;
403 rockchip,pwr18 = <0>;
404 reg = <0x1010e000 0x1000>;
405 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
406 pinctrl-names = "default", "gpio";
407 pinctrl-0 = <&lcdc1_lcdc>;
408 pinctrl-1 = <&lcdc1_gpio>;
412 compatible = "rockchip,rga";
413 reg = <0x10114000 0x1000>;
414 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
416 clock-names = "hclk_rga", "aclk_rga";
421 compatible = "rockchip,saradc";
422 reg = <0x2006c000 0x100>;
423 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
424 #io-channel-cells = <1>;
426 rockchip,adc-vref = <1800>;
427 clock-frequency = <1000000>;
428 clocks = <&clk_saradc>, <&clk_gates7 14>;
429 clock-names = "saradc", "pclk_saradc";
433 spdif: rockchip-spdif@0x1011e000 {
434 compatible = "rockchip-spdif";
435 reg = <0x1011e000 0x2000>;
436 clocks = <&clk_spdif>;
437 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&spdif_tx>;
445 i2s1: rockchip-i2s@0x1011a000 {
446 compatible = "rockchip-i2s";
447 reg = <0x1011a000 0x2000>;
450 clock-names = "i2s_clk";
451 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
455 dma-names = "tx", "rx";
456 pinctrl-names = "default", "sleep";
457 pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
458 pinctrl-1 = <&i2s0_gpio>;
462 compatible = "rockchip,pwm";
463 reg = <0x20030000 0x10>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pwm0_pin>;
472 compatible = "rockchip,pwm";
473 reg = <0x20030010 0x10>; /*0x20030000*/
475 pinctrl-names = "default";
476 pinctrl-0 = <&pwm1_pin>;
481 compatible = "rockchip,pwm";
482 reg = <0x20050020 0x10>; /*0x20030000*/
484 pinctrl-names = "default";
485 pinctrl-0 = <&pwm2_pin>;
491 compatible = "rockchip,pwm";
492 reg = <0x20050030 0x10>; /*0x20030000*/
494 pinctrl-names = "default";
495 pinctrl-0 = <&pwm3_pin>;
502 regulator_name="vdd_arm";
503 suspend_volt=<1000>; //mV
523 regulator_name="vdd_logic";
524 suspend_volt=<1000>; //mV
552 compatible = "rockchip,ion";
553 #address-cells = <1>;
555 rockchip,ion-heap@1 { /* CMA HEAP */
558 rockchip,ion-heap@3 { /* SYSTEM HEAP */
563 dwc_control_usb: dwc-control-usb@0x200080ac {
564 compatible = "rockchip,dwc-control-usb";
565 reg = <0x200080ac 0x4>,
570 reg-names = "GRF_SOC_STATUS0",
575 gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
576 clocks = <&clk_gates4 5>;
577 clock-names = "hclk_usb_peri";
581 compatible = "rockchip,usb20_otg";
582 reg = <0x10180000 0x40000>;
583 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;
585 clock-names = "otgphy0", "hclk_otg0";
589 compatible = "rockchip,usb20_host";
590 reg = <0x101c0000 0x40000>;
591 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;
593 clock-names = "otgphy1", "hclk_otg1";
597 compatible = "rockchip,rk_hsic_host";
598 reg = <0x10240000 0x40000>;
599 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
601 <&clk_hsicphy12m>, <&clk_otgphy1_480m>;
602 clock-names = "hsicphy480m", "hclk_hsic",
603 "hsicphy12m", "hsic_otgphy1";