arch/arm/boot/dts/rk3188.dtsi

   1
   2 #include "skeleton.dtsi"
   3 #include "rk3188-pinctrl.dtsi"
   4
   5
   6 / {
   7         compatible = "rockchip,rk3188";
   8         interrupt-parent = <&gic>;
   9
  10         aliases {
  11                 serial0 = &uart0;
  12                 serial1 = &uart1;
  13                 serial2 = &uart2;
  14                 serial3 = &uart3;
  15         };
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         reg = <0>;
  25                 };
  26                 cpu@1 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         reg = <1>;
  30                 };
  31                 cpu@2 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <2>;
  35                 };
  36                 cpu@3 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a9";
  39                         reg = <3>;
  40                 };
  41         };
  42
  43         twd-wdt@1013c620 {
  44                 compatible = "arm,cortex-a9-twd-wdt";
  45                 reg = <0x1013c620 0x20>;
  46                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  47         };
  48
  49         gic: interrupt-controller@1013d000 {
  50                 compatible = "arm,cortex-a9-gic";
  51                 interrupt-controller;
  52                 #interrupt-cells = <3>;
  53                 reg = <0x1013d000 0x1000>,
  54                       <0x1013c100 0x0100>;
  55         };
  56
  57         L2: cache-controller@10138000 {
  58                 compatible = "arm,pl310-cache";
  59                 reg = <0x10138000 0x1000>;
  60                 cache-unified;
  61                 cache-level = <2>;
  62                 arm,tag-latency = <1 1 1>;
  63                 arm,data-latency = <2 3 1>;
  64                 prefetch-ctrl = <0x70000003>;
  65                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  66                 power-ctrl = <0x3>;
  67 /*
  68                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  69                 (0x1 << 25) |   // Round-robin replacement
  70                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  71                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  72                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  73 */
  74                 aux-ctrl = <0x72000001 (~0x72000001)>;
  75         };
  76
  77         cpu_axi_bus: cpu_axi_bus@10128000 {
  78                 compatible = "rockchip,cpu_axi_bus";
  79                 reg = <0x10128000 0x8000>;
  80                 qos {
  81                         dmac {
  82                                 offset = <0x1000>;
  83                                 priority = <0 0>;
  84                         };
  85                         cpu0 {
  86                                 offset = <0x2000>;
  87                                 priority = <0 0>;
  88                         };
  89                         cpu1r {
  90                                 offset = <0x2080>;
  91                                 priority = <0 0>;
  92                         };
  93                         cpu1w {
  94                                 offset = <0x2100>;
  95                                 priority = <0 0>;
  96                         };
  97                         peri {
  98                                 offset = <0x4000>;
  99                                 priority = <2 2>;
 100                         };
 101                         gpu {
 102                                 offset = <0x5000>;
 103                                 priority = <2 1>;
 104                         };
 105                         vpu {
 106                                 offset = <0x6000>;
 107                         };
 108                         vop0 {
 109                                 offset = <0x7000>;
 110                                 priority = <3 3>;
 111                         };
 112                         cif0 {
 113                                 offset = <0x7080>;
 114                         };
 115                         ipp {
 116                                 offset = <0x7100>;
 117                         };
 118                         vop1 {
 119                                 offset = <0x7180>;
 120                                 priority = <3 3>;
 121                         };
 122                         cif1 {
 123                                 offset = <0x7200>;
 124                         };
 125                         rga {
 126                                 offset = <0x7280>;
 127                         };
 128                 };
 129         };
 130
 131         bootrom@10120000 {
 132                 compatible = "rockchip,bootrom";
 133                 reg = <0x10120000 0x4000>;
 134         };
 135
 136         bootram@10080000 {
 137                 compatible = "rockchip,bootram";
 138                 reg = <0x10080000 0x20>; /* 32 bytes */
 139         };
 140
 141         sram@10080020 {
 142                 compatible = "mmio-sram";
 143                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 144                 map-exec;
 145         };
 146
 147         pmu@20004000 {
 148                 compatible = "rockchip,pmu";
 149                 reg = <0x20004000 0x4000>;
 150         };
 151
 152         timer@200380a0 {
 153                 compatible = "rockchip,timer";
 154                 reg = <0x200380a0 0x20>;
 155                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 156         };
 157
 158         timer@20038000 {
 159                 compatible = "rockchip,timer";
 160                 reg = <0x20038000 0x20>;
 161                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 162         };
 163
 164         timer@20038020 {
 165                 compatible = "rockchip,timer";
 166                 reg = <0x20038020 0x20>;
 167                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 168         };
 169
 170         timer@20038060 {
 171                 compatible = "rockchip,timer";
 172                 reg = <0x20038060 0x20>;
 173                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 174         };
 175
 176         timer@20038080 {
 177                 compatible = "rockchip,timer";
 178                 reg = <0x20038080 0x20>;
 179                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 180         };
 181
 182         uart0: serial@10124000 {
 183                 compatible = "rockchip,serial";
 184                 reg = <0x10124000 0x100>;
 185                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 186                 clock-frequency = <24000000>;
 187                 reg-shift = <2>;
 188                 reg-io-width = <4>;
 189                 pinctrl-names = "default";
 190                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 191                 status = "disabled";
 192         };
 193
 194         uart1: serial@10126000 {
 195                 compatible = "rockchip,serial";
 196                 reg = <0x10126000 0x100>;
 197                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 198                 clock-frequency = <24000000>;
 199                 reg-shift = <2>;
 200                 reg-io-width = <4>;
 201                 pinctrl-names = "default";
 202                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 203                 status = "disabled";
 204         };
 205
 206         uart2: serial@20064000 {
 207                 compatible = "rockchip,serial";
 208                 reg = <0x20064000 0x100>;
 209                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 210                 clock-frequency = <24000000>;
 211                 current-speed = <115200>;
 212                 reg-shift = <2>;
 213                 reg-io-width = <4>;
 214                 pinctrl-names = "default";
 215                 pinctrl-0 = <&uart2_xfer>;
 216                 status = "disabled";
 217         };
 218
 219         uart3: serial@20068000 {
 220                 compatible = "rockchip,serial";
 221                 reg = <0x20068000 0x100>;
 222                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 223                 clock-frequency = <24000000>;
 224                 reg-shift = <2>;
 225                 reg-io-width = <4>;
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 228                 status = "disabled";
 229         };
 230
 231         fiq-debugger {
 232                 compatible = "rockchip,fiq-debugger";
 233                 rockchip,serial-id = <2>;
 234                 rockchip,signal-irq = <112>;
 235                 rockchip,wake-irq = <0>;
 236                 status = "disabled";
 237         };
 238
 239 };