1 #include <dt-bindings/clock/ddr.h>
2 #include <dt-bindings/rkfb/rk_fb.h>
3 #include <dt-bindings/suspend/rockchip-pm.h>
4 #include <dt-bindings/sensor-dev.h>
6 #include "skeleton.dtsi"
7 #include "rk3188-pinctrl.dtsi"
8 #include "rk3188-clocks.dtsi"
11 compatible = "rockchip,rk3188";
12 interrupt-parent = <&gic>;
13 rockchip,sram = <&sram>;
37 compatible = "arm,cortex-a9";
42 compatible = "arm,cortex-a9";
47 compatible = "arm,cortex-a9";
52 compatible = "arm,cortex-a9";
58 compatible = "arm,cortex-a9-twd-wdt";
59 reg = <0x1013c620 0x20>;
60 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
63 gic: interrupt-controller@1013d000 {
64 compatible = "arm,cortex-a9-gic";
66 #interrupt-cells = <3>;
67 reg = <0x1013d000 0x1000>,
71 L2: cache-controller@10138000 {
72 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
73 reg = <0x10138000 0x1000>;
76 arm,tag-latency = <1 1 1>;
77 arm,data-latency = <3 1 2>;
78 rockchip,prefetch-ctrl = <0x70000003>;
79 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
80 rockchip,power-ctrl = <0x3>;
82 (0x1 << 0) | // Full line of write zero behavior Enabled
83 (0x1 << 25) | // Round-robin replacement
84 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
85 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
86 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
88 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
91 cpu_axi_bus: cpu_axi_bus {
92 compatible = "rockchip,cpu_axi_bus";
101 reg = <0x10129000 0x20>;
102 rockchip,priority = <0 0>;
105 reg = <0x1012a000 0x20>;
106 rockchip,priority = <0 0>;
109 reg = <0x1012a080 0x20>;
110 rockchip,priority = <0 0>;
113 reg = <0x1012a100 0x20>;
114 rockchip,priority = <0 0>;
117 reg = <0x1012c000 0x20>;
118 rockchip,priority = <2 2>;
121 reg = <0x1012d000 0x20>;
122 rockchip,priority = <2 1>;
125 reg = <0x1012e000 0x20>;
128 reg = <0x1012f000 0x20>;
129 rockchip,priority = <3 3>;
132 reg = <0x1012f080 0x20>;
135 reg = <0x1012f100 0x20>;
138 reg = <0x1012f180 0x20>;
139 rockchip,priority = <3 3>;
142 reg = <0x1012f200 0x20>;
145 reg = <0x1012f280 0x20>;
149 #address-cells = <1>;
153 reg = <0x10128000 0x18>;
154 rockchip,read-latency = <0x3f>;
160 compatible = "rockchip,bootrom";
161 reg = <0x10120000 0x4000>;
165 compatible = "rockchip,bootram";
166 reg = <0x10080000 0x20>; /* 32 bytes */
169 sram: sram@10080020 {
170 compatible = "mmio-sram";
171 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
176 compatible = "rockchip,pmu";
177 reg = <0x20004000 0x4000>;
181 compatible = "rockchip,timer";
182 reg = <0x20038000 0x20>;
183 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
184 rockchip,percpu = <0>;
188 compatible = "rockchip,timer";
189 reg = <0x20038020 0x20>;
190 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
191 rockchip,percpu = <1>;
195 compatible = "rockchip,timer";
196 reg = <0x20038040 0x20>;
197 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
198 rockchip,percpu = <2>;
202 compatible = "rockchip,timer";
203 reg = <0x20038060 0x20>;
204 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
205 rockchip,percpu = <3>;
209 compatible = "rockchip,timer";
210 reg = <0x20038080 0x20>;
211 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
212 rockchip,broadcast = <1>;
216 compatible = "rockchip,timer";
217 reg = <0x200380a0 0x20>;
218 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
219 rockchip,clocksource = <1>;
222 watchdog:wdt@2004c000 {
223 compatible = "rockchip,watch dog";
224 reg = <0x2004c000 0x100>;
225 clocks = <&clk_gates7 15>;
226 clock-names = "pclk_wdt";
227 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
229 rockchip,timeout = <5>;
230 rockchip,atboot = <1>;
231 rockchip,debug = <0>;
236 #address-cells = <1>;
238 compatible = "arm,amba-bus";
239 interrupt-parent = <&gic>;
242 pdma0: pdma@20018000 {
243 compatible = "arm,pl330", "arm,primecell";
244 reg = <0x20018000 0x4000>;
245 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
251 pdma1: pdma@20078000 {
252 compatible = "arm,pl330", "arm,primecell";
253 reg = <0x20078000 0x4000>;
254 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
261 emmc: rksdmmc@1021C000 {
262 compatible = "rockchip,rk_mmc";
263 reg = <0x1021C000 0x4000>;
264 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;/*irq=57*/
265 #address-cells = <1>;
267 //pinctrl-names = "default",,"suspend";
268 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
269 clocks = <&clk_gates2 14>;
276 sdmmc: rksdmmc@10214000 {
277 compatible = "rockchip,rk_mmc";
278 reg = <0x10214000 0x4000>;
279 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; /*irq=55*/
280 #address-cells = <1>;
282 pinctrl-names = "default","suspend";
283 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
284 pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
285 clocks = <&clk_gates2 11>;
288 fifo-depth = <0x100>;
292 sdio: rksdmmc@10218000 {
293 compatible = "rockchip,rk_mmc";
294 reg = <0x10218000 0x4000>;
295 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
296 #address-cells = <1>;
298 pinctrl-names = "default","suspend";
299 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
300 clocks = <&clk_gates2 13>;
303 fifo-depth = <0x100>;
307 uart0: serial@10124000 {
308 compatible = "rockchip,serial";
309 reg = <0x10124000 0x100>;
310 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
311 clock-frequency = <24000000>;
312 clocks = <&clk_uart0>, <&clk_gates8 0>;
313 clock-names = "sclk_uart", "pclk_uart";
316 dmas = <&pdma0 0>, <&pdma0 1>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
323 uart1: serial@10126000 {
324 compatible = "rockchip,serial";
325 reg = <0x10126000 0x100>;
326 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
327 clock-frequency = <24000000>;
328 clocks = <&clk_uart1>, <&clk_gates8 1>;
329 clock-names = "sclk_uart", "pclk_uart";
332 dmas = <&pdma0 2>, <&pdma0 3>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
339 uart2: serial@20064000 {
340 compatible = "rockchip,serial";
341 reg = <0x20064000 0x100>;
342 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
343 clock-frequency = <24000000>;
344 clocks = <&clk_uart2>, <&clk_gates8 2>;
345 clock-names = "sclk_uart", "pclk_uart";
346 current-speed = <115200>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&uart2_xfer>;
354 uart3: serial@20068000 {
355 compatible = "rockchip,serial";
356 reg = <0x20068000 0x100>;
357 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
358 clock-frequency = <24000000>;
359 clocks = <&clk_uart3>, <&clk_gates8 3>;
360 clock-names = "sclk_uart", "pclk_uart";
363 dmas = <&pdma1 8>, <&pdma1 9>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
371 compatible = "rockchip,fiq-debugger";
372 rockchip,serial-id = <2>;
373 rockchip,signal-irq = <112>;
374 rockchip,wake-irq = <0>;
379 compatible = "rockchip,rockchip-spi";
380 reg = <0x20070000 0x1000>;
381 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
382 #address-cells = <1>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
386 rockchip,spi-src-clk = <0>;
388 clocks =<&clk_spi0>, <&clk_gates7 12>;
389 clock-names = "spi","pclk_spi0";
390 dmas = <&pdma1 10>, <&pdma1 11>;
392 dma-names = "tx", "rx";
397 compatible = "rockchip,rockchip-spi";
398 reg = <0x20074000 0x1000>;
399 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
400 #address-cells = <1>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0 &spi1_cs1>;
404 rockchip,spi-src-clk = <1>;
406 clocks = <&clk_spi1>, <&clk_gates7 13>;
407 clock-names = "spi","pclk_spi1";
408 dmas = <&pdma1 12>, <&pdma1 13>;
410 dma-names = "tx", "rx";
415 compatible = "rockchip,rk30-i2c";
416 reg = <0x2002d000 0x1000>;
417 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
418 #address-cells = <1>;
420 pinctrl-names = "default", "gpio";
421 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
422 pinctrl-1 = <&i2c0_gpio>;
423 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
424 clocks = <&clk_gates8 4>;
425 rockchip,check-idle = <1>;
430 compatible = "rockchip,rk30-i2c";
431 reg = <0x2002f000 0x1000>;
432 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
433 #address-cells = <1>;
435 pinctrl-names = "default", "gpio";
436 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
437 pinctrl-1 = <&i2c1_gpio>;
438 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
439 clocks = <&clk_gates8 5>;
440 rockchip,check-idle = <1>;
445 compatible = "rockchip,rk30-i2c";
446 reg = <0x20056000 0x1000>;
447 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
448 #address-cells = <1>;
450 pinctrl-names = "default", "gpio";
451 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
452 pinctrl-1 = <&i2c2_gpio>;
453 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
454 clocks = <&clk_gates8 6>;
455 rockchip,check-idle = <1>;
460 compatible = "rockchip,rk30-i2c";
461 reg = <0x2005a000 0x1000>;
462 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
463 #address-cells = <1>;
465 pinctrl-names = "default", "gpio";
466 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
467 pinctrl-1 = <&i2c3_gpio>;
468 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
469 clocks = <&clk_gates8 7>;
470 rockchip,check-idle = <1>;
475 compatible = "rockchip,rk30-i2c";
476 reg = <0x2005e000 0x1000>;
477 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
478 #address-cells = <1>;
480 pinctrl-names = "default", "gpio";
481 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
482 pinctrl-1 = <&i2c4_gpio>;
483 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
484 clocks = <&clk_gates8 8>;
485 rockchip,check-idle = <1>;
490 compatible = "rockchip,clocks-init";
491 rockchip,clocks-init-parent =
492 <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll>,
493 <&aclk_peri &clk_gpll>, <&clk_i2s_pll_mux &clk_cpll>,
494 <&clk_uart_pll_mux &clk_gpll>;
495 rockchip,clocks-init-rate =
496 <&clk_core 792000000>, <&clk_gpll 768000000>,
497 <&clk_cpll 594000000>, <&aclk_cpu 192000000>,
498 <&hclk_cpu 96000000>, <&pclk_cpu 48000000>,
499 <&pclk_ahb2apb 48000000>, <&aclk_peri 192000000>,
500 <&hclk_peri 96000000>, <&pclk_peri 48000000>,
501 <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
502 <&aclk_lcdc1 300000000>;
505 //compatible = "rockchip,rkpm_suspend";
506 // define value is in dt-bindint/suspend/rockchip-pm.h
516 rockchip,pmic-gpios=<
517 RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
518 RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
523 compatible = "rockchip,rk-fb";
524 rockchip,disp-mode = <DUAL>;
527 rk_screen: rk_screen{
528 compatible = "rockchip,screen";
532 compatible = "rockchip,rk-nandc";
533 reg = <0x10050000 0x4000>;
534 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
537 lcdc0:lcdc@1010c000 {
538 compatible = "rockchip,rk3188-lcdc";
539 rockchip,prop = <PRMRY>;
540 rochchip,pwr18 = <0>;
541 reg = <0x1010c000 0x1000>;
542 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
546 lcdc1:lcdc@1010e000 {
547 compatible = "rockchip,rk3188-lcdc";
548 rockchip,prop = <EXTEND>;
549 rockchip,pwr18 = <0>;
550 reg = <0x1010e000 0x1000>;
551 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
552 pinctrl-names = "default", "gpio";
553 pinctrl-0 = <&lcdc1_lcdc>;
554 pinctrl-1 = <&lcdc1_gpio>;
559 compatible = "rockchip,rga";
560 reg = <0x10114000 0x1000>;
561 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
563 clock-names = "hclk_rga", "aclk_rga";
567 compatible = "rockchip,saradc";
568 reg = <0x2006c000 0x100>;
569 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
570 #io-channel-cells = <1>;
572 rockchip,adc-vref = <1800>;
573 clock-frequency = <1000000>;
574 clocks = <&clk_saradc>, <&clk_gates7 14>;
575 clock-names = "saradc", "pclk_saradc";
579 spdif: rockchip-spdif@0x1011e000 {
580 compatible = "rockchip-spdif";
581 reg = <0x1011e000 0x2000>;
582 clocks = <&clk_spdif>;
583 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&spdif_tx>;
590 i2s0: rockchip-i2s@0x1011a000 {
591 compatible = "rockchip-i2s";
592 reg = <0x1011a000 0x2000>;
595 clock-names = "i2s_clk";
596 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
599 dma-names = "tx", "rx";
600 pinctrl-names = "default", "sleep";
601 pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
602 pinctrl-1 = <&i2s0_gpio>;
606 compatible = "rockchip,pwm";
607 reg = <0x20030000 0x10>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&pwm0_pin>;
616 compatible = "rockchip,pwm";
617 reg = <0x20030010 0x10>; /*0x20030000*/
619 pinctrl-names = "default";
620 pinctrl-0 = <&pwm1_pin>;
625 compatible = "rockchip,pwm";
626 reg = <0x20050020 0x10>; /*0x20030000*/
628 pinctrl-names = "default";
629 pinctrl-0 = <&pwm2_pin>;
635 compatible = "rockchip,pwm";
636 reg = <0x20050030 0x10>; /*0x20030000*/
638 pinctrl-names = "default";
639 pinctrl-0 = <&pwm3_pin>;
646 regulator_name="vdd_arm";
647 suspend_volt=<1000>; //mV
667 regulator_name="vdd_logic";
668 suspend_volt=<1000>; //mV
696 compatible = "rockchip,ion";
697 #address-cells = <1>;
699 rockchip,ion-heap@1 { /* CMA HEAP */
700 compatible = "rockchip,ion-reserve";
702 memory-reservation = <0x00000000 0x10000000>; /* 256MB */
704 rockchip,ion-heap@3 { /* SYSTEM HEAP */
709 dwc_control_usb: dwc-control-usb@200080ac {
710 compatible = "rockchip,rk3188-dwc-control-usb";
711 reg = <0x200080ac 0x4>,
716 reg-names = "GRF_SOC_STATUS0",
721 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
722 interrupt-names = "otg_bvalid";
723 gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
724 clocks = <&clk_gates4 5>;
725 clock-names = "hclk_usb_peri";
728 compatible = "rockchip,ctrl";
729 rk_usb,bvalid = <0xac 10 1>;
730 rk_usb,line = <0xac 11 2>;
731 rk_usb,softctrl = <0x114 2 1>;
732 rk_usb,opmode = <0x118 1 2>;
733 rk_usb,xcvrsel = <0x118 3 2>;
734 rk_usb,termsel = <0x118 5 1>;
740 compatible = "rockchip,rk3188_usb20_otg";
741 reg = <0x10180000 0x40000>;
742 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;
744 clock-names = "otgphy0", "hclk_otg0";
748 compatible = "rockchip,rk3188_usb20_host";
749 reg = <0x101c0000 0x40000>;
750 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;
752 clock-names = "otgphy1", "hclk_otg1";
756 compatible = "rockchip,rk3188_rk_hsic_host";
757 reg = <0x10240000 0x40000>;
758 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
760 <&clk_hsicphy12m>, <&clk_otgphy1_480m>;
761 clock-names = "hsicphy480m", "hclk_hsic",
762 "hsicphy12m", "hsic_otgphy1";
766 compatible = "rockchip,vmac";
767 reg = <0x10204000 0x4000>;
768 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
769 pinctrl-names = "default", "gpio";
770 pinctrl-0 = <&rmii_clkoutpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
771 pinctrl-1 = <&rmii_clkinpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
774 ap0_vcc_domain: ap0-vcc-domain {
775 compatible = "rockchip,io_vol_domain";
776 pinctrl-names = "default", "1.8V", "3.3V";
777 pinctrl-0 = <&ap0_vcc >;
778 pinctrl-1 = <&ap0_vcc_18>;
779 pinctrl-2 = <&ap0_vcc_33>;
781 ap1_vcc_domain: ap1-vcc-domain{
782 compatible = "rockchip,io_vol_domain";
783 pinctrl-names = "default", "1.8V", "3.3V";
784 pinctrl-0 = <&ap1_vcc >;
785 pinctrl-1 = <&ap1_vcc_18>;
786 pinctrl-2 = <&ap1_vcc_33>;
788 cif_vcc_domain: cif-vcc-domain{
789 compatible = "rockchip,io_vol_domain";
790 pinctrl-names = "default", "1.8V", "3.3V";
791 pinctrl-0 = <&cif_vcc>;
792 pinctrl-1 = <&cif_vcc_18>;
793 pinctrl-2 = <&cif_vcc_33>;
795 flash_vcc_domain: flash-vcc-domain{
796 compatible = "rockchip,io_vol_domain";
797 pinctrl-names = "default", "1.8V", "3.3V";
798 pinctrl-0 = <&flash_vcc>;
799 pinctrl-1 = <&flash_vcc_18>;
800 pinctrl-2 = <&flash_vcc_33>;
802 vccio0_vcc_domain: vccio0-vcc-domain{
803 compatible = "rockchip,io_vol_domain";
804 pinctrl-names = "default", "1.8V", "3.3V";
805 pinctrl-0 = <&vccio0_vcc>;
806 pinctrl-1 = <&vccio0_vcc_18>;
807 pinctrl-2 = <&vccio0_vcc_33>;
809 vccio1_vcc_domain: vccio1-vcc-domain{
810 compatible = "rockchip,io_vol_domain";
811 pinctrl-names = "default", "1.8V", "3.3V";
812 pinctrl-0 = <&vccio1_vcc>;
813 pinctrl-1 = <&vccio1_vcc_18>;
814 pinctrl-2 = <&vccio1_vcc_33>;
816 lcdc0_vcc_domain: lcdc0-vcc-domain{
817 compatible = "rockchip,io_vol_domain";
818 pinctrl-names = "default", "1.8V", "3.3V";
819 pinctrl-0 = <&lcdc0_vcc>;
820 pinctrl-1 = <&lcdc0_vcc_18>;
821 pinctrl-2 = <&lcdc0_vcc_33>;
823 lcdc1_vcc_domain: lcdc1-vcc-domain{
824 compatible = "rockchip,io_vol_domain";
825 pinctrl-names = "default", "1.8V", "3.3V";
826 pinctrl-0 = <&lcdc1_vcc>;
827 pinctrl-1 = <&lcdc1_vcc_18>;
828 pinctrl-2 = <&lcdc1_vcc_33>;