arch/arm/boot/dts/rk3188.dtsi

   1
   2 #include "skeleton.dtsi"
   3 #include "rk3188-pinctrl.dtsi"
   4
   5
   6 / {
   7         compatible = "rockchip,rk3188";
   8         interrupt-parent = <&gic>;
   9
  10         aliases {
  11                 serial0 = &uart0;
  12                 serial1 = &uart1;
  13                 serial2 = &uart2;
  14                 serial3 = &uart3;
  15                 i2c0 = &i2c0;
  16                 i2c1 = &i2c1;
  17                 i2c2 = &i2c2;
  18                 i2c3 = &i2c3;
  19                 i2c4 = &i2c4;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a9";
  29                         reg = <0>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a9";
  34                         reg = <1>;
  35                 };
  36                 cpu@2 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a9";
  39                         reg = <2>;
  40                 };
  41                 cpu@3 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <3>;
  45                 };
  46         };
  47
  48         twd-wdt@1013c620 {
  49                 compatible = "arm,cortex-a9-twd-wdt";
  50                 reg = <0x1013c620 0x20>;
  51                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  52         };
  53
  54         gic: interrupt-controller@1013d000 {
  55                 compatible = "arm,cortex-a9-gic";
  56                 interrupt-controller;
  57                 #interrupt-cells = <3>;
  58                 reg = <0x1013d000 0x1000>,
  59                       <0x1013c100 0x0100>;
  60         };
  61
  62         L2: cache-controller@10138000 {
  63                 compatible = "arm,pl310-cache";
  64                 reg = <0x10138000 0x1000>;
  65                 cache-unified;
  66                 cache-level = <2>;
  67                 arm,tag-latency = <1 1 1>;
  68                 arm,data-latency = <2 3 1>;
  69                 rockchip,prefetch-ctrl = <0x70000003>;
  70                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  71                 rockchip,power-ctrl = <0x3>;
  72 /*
  73                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  74                 (0x1 << 25) |   // Round-robin replacement
  75                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  76                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  77                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  78 */
  79                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  80         };
  81
  82         cpu_axi_bus: cpu_axi_bus@10128000 {
  83                 compatible = "rockchip,cpu_axi_bus";
  84                 reg = <0x10128000 0x8000>;
  85                 qos {
  86                         dmac {
  87                                 rockchip,offset = <0x1000>;
  88                                 rockchip,priority = <0 0>;
  89                         };
  90                         cpu0 {
  91                                 rockchip,offset = <0x2000>;
  92                                 rockchip,priority = <0 0>;
  93                         };
  94                         cpu1r {
  95                                 rockchip,offset = <0x2080>;
  96                                 rockchip,priority = <0 0>;
  97                         };
  98                         cpu1w {
  99                                 rockchip,offset = <0x2100>;
 100                                 rockchip,priority = <0 0>;
 101                         };
 102                         peri {
 103                                 rockchip,offset = <0x4000>;
 104                                 rockchip,priority = <2 2>;
 105                         };
 106                         gpu {
 107                                 rockchip,offset = <0x5000>;
 108                                 rockchip,priority = <2 1>;
 109                         };
 110                         vpu {
 111                                 rockchip,offset = <0x6000>;
 112                         };
 113                         vop0 {
 114                                 rockchip,offset = <0x7000>;
 115                                 rockchip,priority = <3 3>;
 116                         };
 117                         cif0 {
 118                                 rockchip,offset = <0x7080>;
 119                         };
 120                         ipp {
 121                                 rockchip,offset = <0x7100>;
 122                         };
 123                         vop1 {
 124                                 rockchip,offset = <0x7180>;
 125                                 rockchip,priority = <3 3>;
 126                         };
 127                         cif1 {
 128                                 rockchip,offset = <0x7200>;
 129                         };
 130                         rga {
 131                                 rockchip,offset = <0x7280>;
 132                         };
 133                 };
 134         };
 135
 136         bootrom@10120000 {
 137                 compatible = "rockchip,bootrom";
 138                 reg = <0x10120000 0x4000>;
 139         };
 140
 141         bootram@10080000 {
 142                 compatible = "rockchip,bootram";
 143                 reg = <0x10080000 0x20>; /* 32 bytes */
 144         };
 145
 146         sram@10080020 {
 147                 compatible = "mmio-sram";
 148                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 149                 map-exec;
 150         };
 151
 152         pmu@20004000 {
 153                 compatible = "rockchip,pmu";
 154                 reg = <0x20004000 0x4000>;
 155         };
 156
 157         timer@200380a0 {
 158                 compatible = "rockchip,timer";
 159                 reg = <0x200380a0 0x20>;
 160                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 161         };
 162
 163         timer@20038000 {
 164                 compatible = "rockchip,timer";
 165                 reg = <0x20038000 0x20>;
 166                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 167         };
 168
 169         timer@20038020 {
 170                 compatible = "rockchip,timer";
 171                 reg = <0x20038020 0x20>;
 172                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 173         };
 174
 175         timer@20038060 {
 176                 compatible = "rockchip,timer";
 177                 reg = <0x20038060 0x20>;
 178                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 179         };
 180
 181         timer@20038080 {
 182                 compatible = "rockchip,timer";
 183                 reg = <0x20038080 0x20>;
 184                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 185         };
 186
 187         uart0: serial@10124000 {
 188                 compatible = "rockchip,serial";
 189                 reg = <0x10124000 0x100>;
 190                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 191                 clock-frequency = <24000000>;
 192                 reg-shift = <2>;
 193                 reg-io-width = <4>;
 194                 pinctrl-names = "default";
 195                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 196                 status = "disabled";
 197         };
 198
 199         uart1: serial@10126000 {
 200                 compatible = "rockchip,serial";
 201                 reg = <0x10126000 0x100>;
 202                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 203                 clock-frequency = <24000000>;
 204                 reg-shift = <2>;
 205                 reg-io-width = <4>;
 206                 pinctrl-names = "default";
 207                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 208                 status = "disabled";
 209         };
 210
 211         uart2: serial@20064000 {
 212                 compatible = "rockchip,serial";
 213                 reg = <0x20064000 0x100>;
 214                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 215                 clock-frequency = <24000000>;
 216                 current-speed = <115200>;
 217                 reg-shift = <2>;
 218                 reg-io-width = <4>;
 219                 pinctrl-names = "default";
 220                 pinctrl-0 = <&uart2_xfer>;
 221                 status = "disabled";
 222         };
 223
 224         uart3: serial@20068000 {
 225                 compatible = "rockchip,serial";
 226                 reg = <0x20068000 0x100>;
 227                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 228                 clock-frequency = <24000000>;
 229                 reg-shift = <2>;
 230                 reg-io-width = <4>;
 231                 pinctrl-names = "default";
 232                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 233                 status = "disabled";
 234         };
 235
 236         fiq-debugger {
 237                 compatible = "rockchip,fiq-debugger";
 238                 rockchip,serial-id = <2>;
 239                 rockchip,signal-irq = <112>;
 240                 rockchip,wake-irq = <0>;
 241                 status = "disabled";
 242         };
 243
 244         i2c0: i2c@2002d000 {
 245                 compatible = "rockchip,rk30-i2c";
 246                 reg = <0x2002d000 0x1000>;
 247                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 252                 status = "disabled";
 253         };
 254
 255         i2c1: i2c@2002f000 {
 256                 compatible = "rockchip,rk30-i2c";
 257                 reg = <0x2002f000 0x1000>;
 258                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 259                 #address-cells = <1>;
 260                 #size-cells = <0>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 263                 status = "disabled";
 264         };
 265
 266         i2c2: i2c@20055000 {
 267                 compatible = "rockchip,rk30-i2c";
 268                 reg = <0x20055000 0x1000>;
 269                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 270                 #address-cells = <1>;
 271                 #size-cells = <0>;
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 274                 status = "disabled";
 275         };
 276
 277         i2c3: i2c@20059000 {
 278                 compatible = "rockchip,rk30-i2c";
 279                 reg = <0x20059000 0x1000>;
 280                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 pinctrl-names = "default";
 284                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 285                 status = "disabled";
 286         };
 287
 288         i2c4: i2c@2005d000 {
 289                 compatible = "rockchip,rk30-i2c";
 290                 reg = <0x2005d000 0x1000>;
 291                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 pinctrl-names = "default";
 295                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 296                 status = "disabled";
 297         };
 298
 299         clocks-init{
 300                 compatible = "rockchip,clocks-init";
 301                 rockchip,clocks-init-rate =<&clk_cpll 768000000>,<&clk_gpll 594000000>;
 302                 rockchip,clocks-init-parent =<&aclk_peri_mux &clk_gpll>,<&aclk_cpu &clk_gpll>;
 303         };
 304
 305 };
 306
 307
 308