arch/arm/boot/dts/rk3188.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/rkfb/rk_fb.h>
   3 #include <dt-bindings/suspend/rockchip-pm.h>
   4 #include <dt-bindings/sensor-dev.h>
   5
   6 #include "skeleton.dtsi"
   7 #include "rk3188-pinctrl.dtsi"
   8 #include "rk3188-clocks.dtsi"
   9 #include "rk3188_io_vol_domain.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk3188";
  13         interrupt-parent = <&gic>;
  14         rockchip,sram = <&sram>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18                 serial1 = &uart1;
  19                 serial2 = &uart2;
  20                 serial3 = &uart3;
  21                 i2c0 = &i2c0;
  22                 i2c1 = &i2c1;
  23                 i2c2 = &i2c2;
  24                 i2c3 = &i2c3;
  25                 i2c4 = &i2c4;
  26                 lcdc0 = &lcdc0;
  27                 lcdc1 = &lcdc1;
  28                 spi0 = &spi0;
  29                 spi1 = &spi1;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a9";
  39                         reg = <0>;
  40                 };
  41                 cpu@1 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <1>;
  45                 };
  46                 cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a9";
  49                         reg = <2>;
  50                 };
  51                 cpu@3 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a9";
  54                         reg = <3>;
  55                 };
  56         };
  57
  58         twd-wdt@1013c620 {
  59                 compatible = "arm,cortex-a9-twd-wdt";
  60                 reg = <0x1013c620 0x20>;
  61                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  62         };
  63
  64         gic: interrupt-controller@1013d000 {
  65                 compatible = "arm,cortex-a9-gic";
  66                 interrupt-controller;
  67                 #interrupt-cells = <3>;
  68                 reg = <0x1013d000 0x1000>,
  69                       <0x1013c100 0x0100>;
  70         };
  71
  72         L2: cache-controller@10138000 {
  73                 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
  74                 reg = <0x10138000 0x1000>;
  75                 cache-unified;
  76                 cache-level = <2>;
  77                 arm,tag-latency = <1 1 1>;
  78                 arm,data-latency = <3 1 2>;
  79                 rockchip,prefetch-ctrl = <0x70000003>;
  80                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  81                 rockchip,power-ctrl = <0x3>;
  82 /*
  83                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  84                 (0x1 << 25) |   // Round-robin replacement
  85                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  86                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  87                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  88 */
  89                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  90         };
  91
  92         cpu_axi_bus: cpu_axi_bus {
  93                 compatible = "rockchip,cpu_axi_bus";
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 ranges;
  97                 qos {
  98                         #address-cells = <1>;
  99                         #size-cells = <1>;
 100                         ranges;
 101                         dmac {
 102                                 reg = <0x10129000 0x20>;
 103                                 rockchip,priority = <0 0>;
 104                         };
 105                         cpu0 {
 106                                 reg = <0x1012a000 0x20>;
 107                                 rockchip,priority = <0 0>;
 108                         };
 109                         cpu1_r {
 110                                 reg = <0x1012a080 0x20>;
 111                                 rockchip,priority = <0 0>;
 112                         };
 113                         cpu1_w {
 114                                 reg = <0x1012a100 0x20>;
 115                                 rockchip,priority = <0 0>;
 116                         };
 117                         peri {
 118                                 reg = <0x1012c000 0x20>;
 119                                 rockchip,priority = <2 2>;
 120                         };
 121                         gpu {
 122                                 reg = <0x1012d000 0x20>;
 123                                 rockchip,priority = <2 1>;
 124                         };
 125                         vpu {
 126                                 reg = <0x1012e000 0x20>;
 127                         };
 128                         vop0 {
 129                                 reg = <0x1012f000 0x20>;
 130                                 rockchip,priority = <3 3>;
 131                         };
 132                         cif0 {
 133                                 reg = <0x1012f080 0x20>;
 134                         };
 135                         ipp {
 136                                 reg = <0x1012f100 0x20>;
 137                         };
 138                         vop1 {
 139                                 reg = <0x1012f180 0x20>;
 140                                 rockchip,priority = <3 3>;
 141                         };
 142                         cif1 {
 143                                 reg = <0x1012f200 0x20>;
 144                         };
 145                         rga {
 146                                 reg = <0x1012f280 0x20>;
 147                         };
 148                 };
 149                 msch {
 150                         #address-cells = <1>;
 151                         #size-cells = <1>;
 152                         ranges;
 153                         msch {
 154                                 reg = <0x10128000 0x18>;
 155                                 rockchip,read-latency = <0x3f>;
 156                         };
 157                 };
 158         };
 159
 160         bootrom@10120000 {
 161                 compatible = "rockchip,bootrom";
 162                 reg = <0x10120000 0x4000>;
 163         };
 164
 165         bootram@10080000 {
 166                 compatible = "rockchip,bootram";
 167                 reg = <0x10080000 0x20>; /* 32 bytes */
 168         };
 169
 170         sram: sram@10080020 {
 171                 compatible = "mmio-sram";
 172                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 173                 map-exec;
 174         };
 175
 176         pmu@20004000 {
 177                 compatible = "rockchip,pmu";
 178                 reg = <0x20004000 0x4000>;
 179         };
 180
 181         timer@20038000 {
 182                 compatible = "rockchip,timer";
 183                 reg = <0x20038000 0x20>;
 184                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 185                 rockchip,percpu = <0>;
 186         };
 187
 188         timer@20038020 {
 189                 compatible = "rockchip,timer";
 190                 reg = <0x20038020 0x20>;
 191                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 192                 rockchip,percpu = <1>;
 193         };
 194
 195         timer@20038040 {
 196                 compatible = "rockchip,timer";
 197                 reg = <0x20038040 0x20>;
 198                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 199                 rockchip,percpu = <2>;
 200         };
 201
 202         timer@20038060 {
 203                 compatible = "rockchip,timer";
 204                 reg = <0x20038060 0x20>;
 205                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 206                 rockchip,percpu = <3>;
 207         };
 208
 209         timer@20038080 {
 210                 compatible = "rockchip,timer";
 211                 reg = <0x20038080 0x20>;
 212                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 213                 rockchip,broadcast = <1>;
 214         };
 215
 216         timer@200380a0 {
 217                 compatible = "rockchip,timer";
 218                 reg = <0x200380a0 0x20>;
 219                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 220                 rockchip,clocksource = <1>;
 221         };
 222
 223         watchdog:wdt@2004c000 {
 224                 compatible = "rockchip,watch dog";
 225                 reg = <0x2004c000 0x100>;
 226                 clocks = <&clk_gates7 15>;
 227                 clock-names = "pclk_wdt";
 228                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 229                 rockchip,irq = <1>;
 230                 rockchip,timeout = <5>;
 231                 rockchip,atboot = <1>;
 232                 rockchip,debug = <0>;
 233                 status = "disabled";
 234         };
 235
 236         amba {
 237                 #address-cells = <1>;
 238                 #size-cells = <1>;
 239                 compatible = "arm,amba-bus";
 240                 interrupt-parent = <&gic>;
 241                 ranges;
 242
 243                 pdma0: pdma@20018000 {
 244                         compatible = "arm,pl330", "arm,primecell";
 245                         reg = <0x20018000 0x4000>;
 246                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 248                         #dma-cells = <1>;
 249
 250                 };
 251
 252                 pdma1: pdma@20078000 {
 253                         compatible = "arm,pl330", "arm,primecell";
 254                         reg = <0x20078000 0x4000>;
 255                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 256                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 257                         #dma-cells = <1>;
 258
 259                 };
 260         };
 261
 262         emmc: rksdmmc@1021C000 {
 263                 compatible = "rockchip,rk_mmc";
 264                 reg = <0x1021C000 0x4000>;
 265                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;/*irq=57*/
 266                 #address-cells = <1>;
 267                 #size-cells = <0>;
 268                 //pinctrl-names = "default",,"suspend";
 269                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 270                 clocks = <&clk_gates2 14>;
 271                 num-slots = <1>;
 272
 273                 fifo-depth = <0x80>;
 274                 bus-width = <4>;
 275         };
 276
 277         sdmmc: rksdmmc@10214000 {
 278                 compatible = "rockchip,rk_mmc";
 279                 reg = <0x10214000 0x4000>;
 280                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; /*irq=55*/
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 pinctrl-names = "default","suspend";
 284                 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 285                 pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
 286                 clocks = <&clk_gates2 11>;
 287                 num-slots = <1>;
 288
 289                 fifo-depth = <0x100>;
 290                 bus-width = <4>;
 291         };
 292
 293         sdio: rksdmmc@10218000 {
 294                 compatible = "rockchip,rk_mmc";
 295                 reg = <0x10218000 0x4000>;
 296                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299                 pinctrl-names = "default","suspend";
 300                 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 301                 clocks = <&clk_gates2 13>;
 302                 num-slots = <1>;
 303
 304                 fifo-depth = <0x100>;
 305                 bus-width = <4>;
 306         };
 307
 308         uart0: serial@10124000 {
 309                 compatible = "rockchip,serial";
 310                 reg = <0x10124000 0x100>;
 311                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 312                 clock-frequency = <24000000>;
 313                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 314                 clock-names = "sclk_uart", "pclk_uart";
 315                 reg-shift = <2>;
 316                 reg-io-width = <4>;
 317                 dmas = <&pdma0 0>, <&pdma0 1>;
 318                 #dma-cells = <2>;
 319                 pinctrl-names = "default";
 320                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 321                 status = "disabled";
 322         };
 323
 324         uart1: serial@10126000 {
 325                 compatible = "rockchip,serial";
 326                 reg = <0x10126000 0x100>;
 327                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 328                 clock-frequency = <24000000>;
 329                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 330                 clock-names = "sclk_uart", "pclk_uart";
 331                 reg-shift = <2>;
 332                 reg-io-width = <4>;
 333                 dmas = <&pdma0 2>, <&pdma0 3>;
 334                 #dma-cells = <2>;
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 337                 status = "disabled";
 338         };
 339
 340         uart2: serial@20064000 {
 341                 compatible = "rockchip,serial";
 342                 reg = <0x20064000 0x100>;
 343                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 344                 clock-frequency = <24000000>;
 345                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 346                 clock-names = "sclk_uart", "pclk_uart";
 347                 current-speed = <115200>;
 348                 reg-shift = <2>;
 349                 reg-io-width = <4>;
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&uart2_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         uart3: serial@20068000 {
 356                 compatible = "rockchip,serial";
 357                 reg = <0x20068000 0x100>;
 358                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 359                 clock-frequency = <24000000>;
 360                 clocks = <&clk_uart3>, <&clk_gates8 3>;
 361                 clock-names = "sclk_uart", "pclk_uart";
 362                 reg-shift = <2>;
 363                 reg-io-width = <4>;
 364                 dmas = <&pdma1 8>, <&pdma1 9>;
 365                 #dma-cells = <2>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 368                 status = "disabled";
 369         };
 370
 371         fiq-debugger {
 372                 compatible = "rockchip,fiq-debugger";
 373                 rockchip,serial-id = <2>;
 374                 rockchip,signal-irq = <112>;
 375                 rockchip,wake-irq = <0>;
 376                 status = "disabled";
 377         };
 378
 379         spi0: spi@20070000 {
 380                 compatible = "rockchip,rockchip-spi";
 381                 reg = <0x20070000 0x1000>;
 382                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 387                 rockchip,spi-src-clk = <0>;
 388                 num-cs = <2>;
 389                 clocks =<&clk_spi0>, <&clk_gates7 12>;
 390                 clock-names = "spi","pclk_spi0";
 391                 dmas = <&pdma1 10>, <&pdma1 11>;
 392                 #dma-cells = <2>;
 393                 dma-names = "tx", "rx";
 394                 status = "disabled";
 395         };
 396
 397         spi1: spi@20074000 {
 398                 compatible = "rockchip,rockchip-spi";
 399                 reg = <0x20074000 0x1000>;
 400                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0 &spi1_cs1>;
 405                 rockchip,spi-src-clk = <1>;
 406                 num-cs = <2>;
 407                 clocks = <&clk_spi1>, <&clk_gates7 13>;
 408                 clock-names = "spi","pclk_spi1";
 409                 dmas = <&pdma1 12>, <&pdma1 13>;
 410                 #dma-cells = <2>;
 411                 dma-names = "tx", "rx";
 412                 status = "disabled";
 413         };
 414
 415         i2c0: i2c@2002d000 {
 416                 compatible = "rockchip,rk30-i2c";
 417                 reg = <0x2002d000 0x1000>;
 418                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 419                 #address-cells = <1>;
 420                 #size-cells = <0>;
 421                 pinctrl-names = "default", "gpio";
 422                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 423                 pinctrl-1 = <&i2c0_gpio>;
 424                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 425                 clocks = <&clk_gates8 4>;
 426                 rockchip,check-idle = <1>;
 427                 status = "disabled";
 428         };
 429
 430         i2c1: i2c@2002f000 {
 431                 compatible = "rockchip,rk30-i2c";
 432                 reg = <0x2002f000 0x1000>;
 433                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 pinctrl-names = "default", "gpio";
 437                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 438                 pinctrl-1 = <&i2c1_gpio>;
 439                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 440                 clocks = <&clk_gates8 5>;
 441                 rockchip,check-idle = <1>;
 442                 status = "disabled";
 443         };
 444
 445         i2c2: i2c@20056000 {
 446                 compatible = "rockchip,rk30-i2c";
 447                 reg = <0x20056000 0x1000>;
 448                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 pinctrl-names = "default", "gpio";
 452                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 453                 pinctrl-1 = <&i2c2_gpio>;
 454                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 455                 clocks = <&clk_gates8 6>;
 456                 rockchip,check-idle = <1>;
 457                 status = "disabled";
 458         };
 459
 460         i2c3: i2c@2005a000 {
 461                 compatible = "rockchip,rk30-i2c";
 462                 reg = <0x2005a000 0x1000>;
 463                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 464                 #address-cells = <1>;
 465                 #size-cells = <0>;
 466                 pinctrl-names = "default", "gpio";
 467                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 468                 pinctrl-1 = <&i2c3_gpio>;
 469                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 470                 clocks = <&clk_gates8 7>;
 471                 rockchip,check-idle = <1>;
 472                 status = "disabled";
 473         };
 474
 475         i2c4: i2c@2005e000 {
 476                 compatible = "rockchip,rk30-i2c";
 477                 reg = <0x2005e000 0x1000>;
 478                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 479                 #address-cells = <1>;
 480                 #size-cells = <0>;
 481                 pinctrl-names = "default", "gpio";
 482                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 483                 pinctrl-1 = <&i2c4_gpio>;
 484                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 485                 clocks = <&clk_gates8 8>;
 486                 rockchip,check-idle = <1>;
 487                 status = "disabled";
 488         };
 489
 490         clocks-init{
 491                 compatible = "rockchip,clocks-init";
 492                 rockchip,clocks-init-parent =
 493                         <&clk_core &clk_apll>,  <&aclk_cpu &clk_gpll>,
 494                         <&aclk_peri &clk_gpll>, <&clk_i2s_pll_mux &clk_cpll>,
 495                         <&clk_uart_pll_mux &clk_gpll>;
 496                 rockchip,clocks-init-rate =
 497                         <&clk_core 792000000>,  <&clk_gpll 768000000>,
 498                         <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
 499                         <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
 500                         <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
 501                         <&hclk_peri 96000000>,  <&pclk_peri 48000000>,
 502                         <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
 503                         <&aclk_lcdc1 300000000>;
 504         };
 505         rkpm_suspend {
 506                 compatible = "rockchip,rkpm_suspend";
 507
 508                 // define value is in dt-bindint/suspend/rockchip-pm.h
 509                 rockchip,ctrbits = <
 510                                                 (
 511                                                 RKPM_CTR_PWR_DMNS
 512                                                 |RKPM_CTR_GTCLKS
 513                                                 |RKPM_CTR_PLLS
 514                                                 |RKPM_CTR_SYSCLK_DIV
 515                                                 |RKPM_CTR_NORIDLE_MD
 516                                                 )
 517                                         >;
 518               rockchip,pmic-gpios=<
 519                                                 RKPM_GPIOS_SETTING(GPIO0_A0,RKPM_GPIOS_OUTPUT,RKPM_GPIOS_OUT_H)
 520                                                 RKPM_GPIOS_SETTING(GPIO0_A1,RKPM_GPIOS_OUTPUT,RKPM_GPIOS_OUT_H)
 521                                                 >;
 522
 523         };
 524         fb: fb{
 525                 compatible = "rockchip,rk-fb";
 526                 rockchip,disp-mode = <DUAL>;
 527         };
 528
 529         rk_screen: rk_screen{
 530                 compatible = "rockchip,screen";
 531         };
 532
 533         nandc: nandc {
 534                 compatible = "rockchip,rk-nandc";
 535                 reg = <0x10050000 0x4000>;
 536                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 537         };
 538
 539         lcdc0:lcdc@1010c000 {
 540                 compatible = "rockchip,rk3188-lcdc";
 541                 rockchip,prop = <PRMRY>;
 542                 rochchip,pwr18 = <0>;
 543                 reg = <0x1010c000 0x1000>;
 544                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 545                 status = "disabled";
 546         };
 547
 548         lcdc1:lcdc@1010e000 {
 549                 compatible = "rockchip,rk3188-lcdc";
 550                 rockchip,prop = <EXTEND>;
 551                 rockchip,pwr18 = <0>;
 552                 reg = <0x1010e000 0x1000>;
 553                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 554                 pinctrl-names = "default", "gpio";
 555                 pinctrl-0 = <&lcdc1_lcdc>;
 556                 pinctrl-1 = <&lcdc1_gpio>;
 557                 status = "disabled";
 558         };
 559
 560         rga@10114000 {
 561                 compatible = "rockchip,rga";
 562                 reg = <0x10114000 0x1000>;
 563                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 564                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 565                 clock-names = "hclk_rga", "aclk_rga";
 566         };
 567
 568         adc: adc@2006c000 {
 569                 compatible = "rockchip,saradc";
 570                 reg = <0x2006c000 0x100>;
 571                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 572                 #io-channel-cells = <1>;
 573                 io-channel-ranges;
 574                 rockchip,adc-vref = <1800>;
 575                 clock-frequency = <1000000>;
 576                 clocks = <&clk_saradc>, <&clk_gates7 14>;
 577                 clock-names = "saradc", "pclk_saradc";
 578                 status = "disabled";
 579         };
 580
 581         spdif: rockchip-spdif@0x1011e000 {
 582                 compatible = "rockchip-spdif";
 583                 reg = <0x1011e000 0x2000>;
 584                 clocks = <&clk_spdif>;
 585                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 586                 dmas = <&pdma0 8>;
 587                 dma-names = "tx";
 588                 pinctrl-names = "default";
 589                 pinctrl-0 = <&spdif_tx>;
 590         };
 591
 592         i2s0: rockchip-i2s@0x1011a000 {
 593                 compatible = "rockchip-i2s";
 594                 reg = <0x1011a000 0x2000>;
 595                 i2s-id = <0>;
 596                 clocks = <&clk_i2s>;
 597                 clock-names = "i2s_clk";
 598                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 599                 dmas = <&pdma0 6>,
 600                         <&pdma0 7>;
 601                 dma-names = "tx", "rx";
 602                 pinctrl-names = "default", "sleep";
 603                 pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 604                 pinctrl-1 = <&i2s0_gpio>;
 605         };
 606
 607         pwm0: pwm@20030000{
 608                 compatible = "rockchip,pwm";
 609                 reg = <0x20030000 0x10>;
 610                 #pwm-cells = <2>;
 611                 pinctrl-names = "default";
 612                 pinctrl-0 = <&pwm0_pin>;
 613                 status = "disabled";
 614
 615         };
 616
 617         pwm1: pwm@20030010{
 618                 compatible = "rockchip,pwm";
 619                 reg = <0x20030010 0x10>; /*0x20030000*/
 620                 #pwm-cells = <2>;
 621                 pinctrl-names = "default";
 622                 pinctrl-0 = <&pwm1_pin>;
 623                 status = "disabled";
 624
 625         };
 626         pwm2: pwm@20050020{
 627                 compatible = "rockchip,pwm";
 628                 reg = <0x20050020 0x10>; /*0x20030000*/
 629                 #pwm-cells = <2>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&pwm2_pin>;
 632                 status = "disabled";
 633
 634         };
 635
 636         pwm3: pwm@20050030{
 637                 compatible = "rockchip,pwm";
 638                 reg = <0x20050030 0x10>; /*0x20030000*/
 639                 #pwm-cells = <2>;
 640                 pinctrl-names = "default";
 641                 pinctrl-0 = <&pwm3_pin>;
 642                 status = "disabled";
 643
 644         };
 645         dvfs {
 646                 vd_cpu:
 647                 vd_cpu {
 648                         regulator_name="vdd_arm";
 649                         suspend_volt=<1000>; //mV
 650                         pd_a9 {
 651                                 clk_core_dvfs_table:
 652                                 clk_core {
 653                                         operating-points = <
 654                                                 /* KHz    uV */
 655                                                 312000 900000
 656                                                 504000 950000
 657                                                 816000 1000000
 658                                                 1008000 1100000
 659                                                 1200000 1200000
 660                                                 1416000 1300000
 661                                                 1608000 1350000
 662                                                 >;
 663                                 };
 664                         };
 665                 };
 666
 667                 vd_core:
 668                 vd_core {
 669                         regulator_name="vdd_logic";
 670                         suspend_volt=<1000>; //mV
 671
 672                         pd_gpu {
 673                                 clk_gpu_dvfs_table:
 674                                 clk_gpu {
 675                                         operating-points = <
 676                                                 /* KHz    uV */
 677                                                 200000 1200000
 678                                                 300000 1200000
 679                                                 400000 1200000
 680                                                 >;
 681                                 };
 682                         };
 683
 684                         pd_ddr {
 685                                 clk_ddr_dvfs_table:
 686                                 clk_ddr {
 687                                         operating-points = <
 688                                                 /* KHz    uV */
 689                                                 200000 1200000
 690                                                 300000 1200000
 691                                                 400000 1200000
 692                                                 >;
 693                                 };
 694                         };
 695                 };
 696         };
 697         ion{
 698                 compatible = "rockchip,ion";
 699                 #address-cells = <1>;
 700                 #size-cells = <0>;
 701                 rockchip,ion-heap@1 { /* CMA HEAP */
 702                         compatible = "rockchip,ion-reserve";
 703                         reg = <1>;
 704                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 705                 };
 706                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 707                         reg = <3>;
 708                 };
 709         };
 710
 711         dwc_control_usb: dwc-control-usb@200080ac {
 712                 compatible = "rockchip,rk3188-dwc-control-usb";
 713                 reg = <0x200080ac 0x4>,
 714                       <0x2000810c 0x10>,
 715                       <0x2000811c 0x10>,
 716                       <0x2000812c 0x8>,
 717                       <0x20008138 0x8>;
 718                 reg-names = "GRF_SOC_STATUS0",
 719                             "GRF_UOC0_BASE",
 720                             "GRF_UOC1_BASE",
 721                             "GRF_UOC2_BASE",
 722                             "GRF_UOC3_BASE";
 723                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 724                 interrupt-names = "otg_bvalid";
 725                 gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 726                 clocks = <&clk_gates4 5>;
 727                 clock-names = "hclk_usb_peri";
 728
 729                 usb_bc{
 730                         compatible = "rockchip,ctrl";
 731                         rk_usb,bvalid   = <0xac 10 1>;
 732                         rk_usb,line     = <0xac 11 2>;
 733                         rk_usb,softctrl = <0x114 2 1>;
 734                         rk_usb,opmode   = <0x118 1 2>;
 735                         rk_usb,xcvrsel  = <0x118 3 2>;
 736                         rk_usb,termsel  = <0x118 5 1>;
 737                 };
 738         };
 739
 740
 741         usb@10180000 {
 742                 compatible = "rockchip,rk3188_usb20_otg";
 743                 reg = <0x10180000 0x40000>;
 744                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 745                 clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;
 746                 clock-names = "otgphy0", "hclk_otg0";
 747         };
 748
 749         usb@101c0000 {
 750                 compatible = "rockchip,rk3188_usb20_host";
 751                 reg = <0x101c0000 0x40000>;
 752                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 753                 clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;
 754                 clock-names = "otgphy1", "hclk_otg1";
 755         };
 756
 757         hsic@10240000 {
 758                 compatible = "rockchip,rk3188_rk_hsic_host";
 759                 reg = <0x10240000 0x40000>;
 760                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 761                 clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
 762                          <&clk_hsicphy12m>, <&clk_otgphy1_480m>;
 763                 clock-names = "hsicphy480m", "hclk_hsic",
 764                               "hsicphy12m", "hsic_otgphy1";
 765         };
 766
 767         vmac@10204000 {
 768                 compatible = "rockchip,vmac";
 769                 reg = <0x10204000 0x4000>;
 770                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 771                 pinctrl-names = "default", "gpio";
 772                 pinctrl-0 = <&rmii_clkoutpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
 773                 pinctrl-1 = <&rmii_clkinpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
 774         };
 775 };