2 #include "skeleton.dtsi"
3 #include "rk3188-pinctrl.dtsi"
4 #include <dt-bindings/rkfb/rk_fb.h>
8 compatible = "rockchip,rk3188";
9 interrupt-parent = <&gic>;
10 rockchip,sram = <&sram>;
32 compatible = "arm,cortex-a9";
37 compatible = "arm,cortex-a9";
42 compatible = "arm,cortex-a9";
47 compatible = "arm,cortex-a9";
53 compatible = "arm,cortex-a9-twd-wdt";
54 reg = <0x1013c620 0x20>;
55 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
58 gic: interrupt-controller@1013d000 {
59 compatible = "arm,cortex-a9-gic";
61 #interrupt-cells = <3>;
62 reg = <0x1013d000 0x1000>,
66 L2: cache-controller@10138000 {
67 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
68 reg = <0x10138000 0x1000>;
71 arm,tag-latency = <1 1 1>;
72 arm,data-latency = <2 3 1>;
73 rockchip,prefetch-ctrl = <0x70000003>;
74 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
75 rockchip,power-ctrl = <0x3>;
77 (0x1 << 0) | // Full line of write zero behavior Enabled
78 (0x1 << 25) | // Round-robin replacement
79 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
80 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
81 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
83 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
86 cpu_axi_bus: cpu_axi_bus@10128000 {
87 compatible = "rockchip,cpu_axi_bus";
88 reg = <0x10128000 0x8000>;
91 rockchip,offset = <0x1000>;
92 rockchip,priority = <0 0>;
95 rockchip,offset = <0x2000>;
96 rockchip,priority = <0 0>;
99 rockchip,offset = <0x2080>;
100 rockchip,priority = <0 0>;
103 rockchip,offset = <0x2100>;
104 rockchip,priority = <0 0>;
107 rockchip,offset = <0x4000>;
108 rockchip,priority = <2 2>;
111 rockchip,offset = <0x5000>;
112 rockchip,priority = <2 1>;
115 rockchip,offset = <0x6000>;
118 rockchip,offset = <0x7000>;
119 rockchip,priority = <3 3>;
122 rockchip,offset = <0x7080>;
125 rockchip,offset = <0x7100>;
128 rockchip,offset = <0x7180>;
129 rockchip,priority = <3 3>;
132 rockchip,offset = <0x7200>;
135 rockchip,offset = <0x7280>;
141 compatible = "rockchip,bootrom";
142 reg = <0x10120000 0x4000>;
146 compatible = "rockchip,bootram";
147 reg = <0x10080000 0x20>; /* 32 bytes */
150 sram: sram@10080020 {
151 compatible = "mmio-sram";
152 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
157 compatible = "rockchip,pmu";
158 reg = <0x20004000 0x4000>;
162 compatible = "rockchip,timer";
163 reg = <0x20038000 0x20>;
164 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
165 rockchip,percpu = <0>;
169 compatible = "rockchip,timer";
170 reg = <0x20038020 0x20>;
171 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
172 rockchip,percpu = <1>;
176 compatible = "rockchip,timer";
177 reg = <0x20038040 0x20>;
178 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
179 rockchip,percpu = <2>;
183 compatible = "rockchip,timer";
184 reg = <0x20038060 0x20>;
185 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
186 rockchip,percpu = <3>;
190 compatible = "rockchip,timer";
191 reg = <0x20038080 0x20>;
192 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
193 rockchip,broadcast = <1>;
197 compatible = "rockchip,timer";
198 reg = <0x200380a0 0x20>;
199 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
200 rockchip,clocksource = <1>;
203 uart0: serial@10124000 {
204 compatible = "rockchip,serial";
205 reg = <0x10124000 0x100>;
206 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
207 clock-frequency = <24000000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
215 uart1: serial@10126000 {
216 compatible = "rockchip,serial";
217 reg = <0x10126000 0x100>;
218 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
219 clock-frequency = <24000000>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
227 uart2: serial@20064000 {
228 compatible = "rockchip,serial";
229 reg = <0x20064000 0x100>;
230 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
231 clock-frequency = <24000000>;
232 current-speed = <115200>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&uart2_xfer>;
240 uart3: serial@20068000 {
241 compatible = "rockchip,serial";
242 reg = <0x20068000 0x100>;
243 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
244 clock-frequency = <24000000>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
253 compatible = "rockchip,fiq-debugger";
254 rockchip,serial-id = <2>;
255 rockchip,signal-irq = <112>;
256 rockchip,wake-irq = <0>;
261 compatible = "rockchip,rk30-i2c";
262 reg = <0x2002d000 0x1000>;
263 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
264 #address-cells = <1>;
266 pinctrl-names = "default", "gpio";
267 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
268 pinctrl-1 = <&i2c0_gpio>;
269 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
270 clocks = <&clk_gates8 4>;
271 rockchip,check-idle = <1>;
276 compatible = "rockchip,rk30-i2c";
277 reg = <0x2002f000 0x1000>;
278 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
279 #address-cells = <1>;
281 pinctrl-names = "default", "gpio";
282 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
283 pinctrl-1 = <&i2c1_gpio>;
284 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
285 clocks = <&clk_gates8 5>;
286 rockchip,check-idle = <1>;
291 compatible = "rockchip,rk30-i2c";
292 reg = <0x20055000 0x1000>;
293 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
294 #address-cells = <1>;
296 pinctrl-names = "default", "gpio";
297 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
298 pinctrl-1 = <&i2c2_gpio>;
299 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
300 clocks = <&clk_gates8 6>;
301 rockchip,check-idle = <1>;
306 compatible = "rockchip,rk30-i2c";
307 reg = <0x20059000 0x1000>;
308 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
309 #address-cells = <1>;
311 pinctrl-names = "default", "gpio";
312 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
313 pinctrl-1 = <&i2c3_gpio>;
314 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
315 clocks = <&clk_gates8 7>;
316 rockchip,check-idle = <1>;
321 compatible = "rockchip,rk30-i2c";
322 reg = <0x2005d000 0x1000>;
323 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
324 #address-cells = <1>;
326 pinctrl-names = "default", "gpio";
327 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
328 pinctrl-1 = <&i2c4_gpio>;
329 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
330 clocks = <&clk_gates8 8>;
331 rockchip,check-idle = <1>;
336 compatible = "rockchip,clocks-init";
337 rockchip,clocks-init-parent =
338 <&clk_core &clk_apll>, <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
339 <&aclk_peri_mux &clk_gpll>, <&clk_i2s_pll_mux &clk_cpll>,
340 <&clk_uart_pll_mux &clk_gpll>;
341 rockchip,clocks-init-rate =
342 <&clk_core 594000000>, <&clk_gpll 768000000>,
343 <&clk_cpll 594000000>, <&aclk_cpu 192000000>,
344 <&hclk_cpu 96000000>, <&pclk_cpu 48000000>,
345 <&pclk_ahb2apb 48000000>, <&aclk_peri 192000000>,
346 <&hclk_peri 96000000>, <&pclk_peri 48000000>;
350 compatible = "rockchip,rk-fb";
351 rockchip,disp-mode = <DUAL>;
354 lcdc0:lcdc@1010c000 {
355 compatible = "rockchip,rk3188-lcdc";
356 rockchip,prop = <PRMRY>;
357 rochchip,pwr18 = <0>;
358 reg = <0x1010c000 0x1000>;
359 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
363 lcdc1:lcdc@1010e000 {
364 compatible = "rockchip,rk3188-lcdc";
365 rockchip,prop = <EXTEND>;
366 rockchip,pwr18 = <0>;
367 reg = <0x1010e000 0x1000>;
368 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
369 pinctrl-names = "default", "gpio";
370 pinctrl-0 = <&lcdc1_lcdc>;
371 pinctrl-1 = <&lcdc1_gpio>;
376 compatible = "rockchip,pwm";
377 reg = <0x20030000 0x10>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&pwm0_pin>;
386 compatible = "rockchip,pwm";
387 reg = <0x20030010 0x10>; /*0x20030000*/
389 pinctrl-names = "default";
390 pinctrl-0 = <&pwm1_pin>;
395 compatible = "rockchip,pwm";
396 reg = <0x20050020 0x10>; /*0x20030000*/
398 pinctrl-names = "default";
399 pinctrl-0 = <&pwm2_pin>;
405 compatible = "rockchip,pwm";
406 reg = <0x20050030 0x10>; /*0x20030000*/
408 pinctrl-names = "default";
409 pinctrl-0 = <&pwm3_pin>;