arch/arm/boot/dts/rk3188.dtsi

   1
   2 #include "skeleton.dtsi"
   3 #include "rk3188-pinctrl.dtsi"
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5
   6
   7 / {
   8         compatible = "rockchip,rk3188";
   9         interrupt-parent = <&gic>;
  10         rockchip,sram = <&sram>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 serial2 = &uart2;
  16                 serial3 = &uart3;
  17                 i2c0 = &i2c0;
  18                 i2c1 = &i2c1;
  19                 i2c2 = &i2c2;
  20                 i2c3 = &i2c3;
  21                 i2c4 = &i2c4;
  22                 lcdc0 = &lcdc0;
  23                 lcdc1 = &lcdc1;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         reg = <0>;
  34                 };
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         reg = <1>;
  39                 };
  40                 cpu@2 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a9";
  43                         reg = <2>;
  44                 };
  45                 cpu@3 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a9";
  48                         reg = <3>;
  49                 };
  50         };
  51
  52         twd-wdt@1013c620 {
  53                 compatible = "arm,cortex-a9-twd-wdt";
  54                 reg = <0x1013c620 0x20>;
  55                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  56         };
  57
  58         gic: interrupt-controller@1013d000 {
  59                 compatible = "arm,cortex-a9-gic";
  60                 interrupt-controller;
  61                 #interrupt-cells = <3>;
  62                 reg = <0x1013d000 0x1000>,
  63                       <0x1013c100 0x0100>;
  64         };
  65
  66         L2: cache-controller@10138000 {
  67                 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
  68                 reg = <0x10138000 0x1000>;
  69                 cache-unified;
  70                 cache-level = <2>;
  71                 arm,tag-latency = <1 1 1>;
  72                 arm,data-latency = <2 3 1>;
  73                 rockchip,prefetch-ctrl = <0x70000003>;
  74                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  75                 rockchip,power-ctrl = <0x3>;
  76 /*
  77                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  78                 (0x1 << 25) |   // Round-robin replacement
  79                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  80                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  81                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  82 */
  83                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  84         };
  85
  86         cpu_axi_bus: cpu_axi_bus@10128000 {
  87                 compatible = "rockchip,cpu_axi_bus";
  88                 reg = <0x10128000 0x8000>;
  89                 qos {
  90                         dmac {
  91                                 rockchip,offset = <0x1000>;
  92                                 rockchip,priority = <0 0>;
  93                         };
  94                         cpu0 {
  95                                 rockchip,offset = <0x2000>;
  96                                 rockchip,priority = <0 0>;
  97                         };
  98                         cpu1r {
  99                                 rockchip,offset = <0x2080>;
 100                                 rockchip,priority = <0 0>;
 101                         };
 102                         cpu1w {
 103                                 rockchip,offset = <0x2100>;
 104                                 rockchip,priority = <0 0>;
 105                         };
 106                         peri {
 107                                 rockchip,offset = <0x4000>;
 108                                 rockchip,priority = <2 2>;
 109                         };
 110                         gpu {
 111                                 rockchip,offset = <0x5000>;
 112                                 rockchip,priority = <2 1>;
 113                         };
 114                         vpu {
 115                                 rockchip,offset = <0x6000>;
 116                         };
 117                         vop0 {
 118                                 rockchip,offset = <0x7000>;
 119                                 rockchip,priority = <3 3>;
 120                         };
 121                         cif0 {
 122                                 rockchip,offset = <0x7080>;
 123                         };
 124                         ipp {
 125                                 rockchip,offset = <0x7100>;
 126                         };
 127                         vop1 {
 128                                 rockchip,offset = <0x7180>;
 129                                 rockchip,priority = <3 3>;
 130                         };
 131                         cif1 {
 132                                 rockchip,offset = <0x7200>;
 133                         };
 134                         rga {
 135                                 rockchip,offset = <0x7280>;
 136                         };
 137                 };
 138         };
 139
 140         bootrom@10120000 {
 141                 compatible = "rockchip,bootrom";
 142                 reg = <0x10120000 0x4000>;
 143         };
 144
 145         bootram@10080000 {
 146                 compatible = "rockchip,bootram";
 147                 reg = <0x10080000 0x20>; /* 32 bytes */
 148         };
 149
 150         sram: sram@10080020 {
 151                 compatible = "mmio-sram";
 152                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 153                 map-exec;
 154         };
 155
 156         pmu@20004000 {
 157                 compatible = "rockchip,pmu";
 158                 reg = <0x20004000 0x4000>;
 159         };
 160
 161         timer@20038000 {
 162                 compatible = "rockchip,timer";
 163                 reg = <0x20038000 0x20>;
 164                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 165                 rockchip,percpu = <0>;
 166         };
 167
 168         timer@20038020 {
 169                 compatible = "rockchip,timer";
 170                 reg = <0x20038020 0x20>;
 171                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 172                 rockchip,percpu = <1>;
 173         };
 174
 175         timer@20038040 {
 176                 compatible = "rockchip,timer";
 177                 reg = <0x20038040 0x20>;
 178                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 179                 rockchip,percpu = <2>;
 180         };
 181
 182         timer@20038060 {
 183                 compatible = "rockchip,timer";
 184                 reg = <0x20038060 0x20>;
 185                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 186                 rockchip,percpu = <3>;
 187         };
 188
 189         timer@20038080 {
 190                 compatible = "rockchip,timer";
 191                 reg = <0x20038080 0x20>;
 192                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 193                 rockchip,broadcast = <1>;
 194         };
 195
 196         timer@200380a0 {
 197                 compatible = "rockchip,timer";
 198                 reg = <0x200380a0 0x20>;
 199                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 200                 rockchip,clocksource = <1>;
 201         };
 202
 203         uart0: serial@10124000 {
 204                 compatible = "rockchip,serial";
 205                 reg = <0x10124000 0x100>;
 206                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 207                 clock-frequency = <24000000>;
 208                 reg-shift = <2>;
 209                 reg-io-width = <4>;
 210                 pinctrl-names = "default";
 211                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 212                 status = "disabled";
 213         };
 214
 215         uart1: serial@10126000 {
 216                 compatible = "rockchip,serial";
 217                 reg = <0x10126000 0x100>;
 218                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 219                 clock-frequency = <24000000>;
 220                 reg-shift = <2>;
 221                 reg-io-width = <4>;
 222                 pinctrl-names = "default";
 223                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 224                 status = "disabled";
 225         };
 226
 227         uart2: serial@20064000 {
 228                 compatible = "rockchip,serial";
 229                 reg = <0x20064000 0x100>;
 230                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 231                 clock-frequency = <24000000>;
 232                 current-speed = <115200>;
 233                 reg-shift = <2>;
 234                 reg-io-width = <4>;
 235                 pinctrl-names = "default";
 236                 pinctrl-0 = <&uart2_xfer>;
 237                 status = "disabled";
 238         };
 239
 240         uart3: serial@20068000 {
 241                 compatible = "rockchip,serial";
 242                 reg = <0x20068000 0x100>;
 243                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 244                 clock-frequency = <24000000>;
 245                 reg-shift = <2>;
 246                 reg-io-width = <4>;
 247                 pinctrl-names = "default";
 248                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 249                 status = "disabled";
 250         };
 251
 252         fiq-debugger {
 253                 compatible = "rockchip,fiq-debugger";
 254                 rockchip,serial-id = <2>;
 255                 rockchip,signal-irq = <112>;
 256                 rockchip,wake-irq = <0>;
 257                 status = "disabled";
 258         };
 259
 260         i2c0: i2c@2002d000 {
 261                 compatible = "rockchip,rk30-i2c";
 262                 reg = <0x2002d000 0x1000>;
 263                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 pinctrl-names = "default", "gpio";
 267                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 268                 pinctrl-1 = <&i2c0_gpio>;
 269                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 270                 clocks = <&clk_gates8 4>;
 271                 rockchip,check-idle = <1>;
 272                 status = "disabled";
 273         };
 274
 275         i2c1: i2c@2002f000 {
 276                 compatible = "rockchip,rk30-i2c";
 277                 reg = <0x2002f000 0x1000>;
 278                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 279                 #address-cells = <1>;
 280                 #size-cells = <0>;
 281                 pinctrl-names = "default", "gpio";
 282                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 283                 pinctrl-1 = <&i2c1_gpio>;
 284                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 285                 clocks = <&clk_gates8 5>;
 286                 rockchip,check-idle = <1>;
 287                 status = "disabled";
 288         };
 289
 290         i2c2: i2c@20055000 {
 291                 compatible = "rockchip,rk30-i2c";
 292                 reg = <0x20055000 0x1000>;
 293                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296                 pinctrl-names = "default", "gpio";
 297                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 298                 pinctrl-1 = <&i2c2_gpio>;
 299                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 300                 clocks = <&clk_gates8 6>;
 301                 rockchip,check-idle = <1>;
 302                 status = "disabled";
 303         };
 304
 305         i2c3: i2c@20059000 {
 306                 compatible = "rockchip,rk30-i2c";
 307                 reg = <0x20059000 0x1000>;
 308                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 pinctrl-names = "default", "gpio";
 312                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 313                 pinctrl-1 = <&i2c3_gpio>;
 314                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 315                 clocks = <&clk_gates8 7>;
 316                 rockchip,check-idle = <1>;
 317                 status = "disabled";
 318         };
 319
 320         i2c4: i2c@2005d000 {
 321                 compatible = "rockchip,rk30-i2c";
 322                 reg = <0x2005d000 0x1000>;
 323                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 pinctrl-names = "default", "gpio";
 327                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 328                 pinctrl-1 = <&i2c4_gpio>;
 329                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 330                 clocks = <&clk_gates8 8>;
 331                 rockchip,check-idle = <1>;
 332                 status = "disabled";
 333         };
 334
 335         clocks-init{
 336                 compatible = "rockchip,clocks-init";
 337                 rockchip,clocks-init-parent =
 338                         <&clk_core &clk_apll>,  <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
 339                         <&aclk_peri_mux &clk_gpll>,     <&clk_i2s_pll_mux &clk_cpll>,
 340                         <&clk_uart_pll_mux &clk_gpll>;
 341                 rockchip,clocks-init-rate =
 342                         <&clk_core 792000000>,  <&clk_gpll 768000000>,
 343                         <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
 344                         <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
 345                         <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
 346                         <&hclk_peri 96000000>,  <&pclk_peri 48000000>;
 347         };
 348
 349         fb: fb{
 350                 compatible = "rockchip,rk-fb";
 351                 rockchip,disp-mode = <DUAL>;
 352         };
 353
 354         lcdc0:lcdc@1010c000 {
 355                 compatible = "rockchip,rk3188-lcdc";
 356                 rockchip,prop = <PRMRY>;
 357                 reg = <0x1010c000 0x1000>;
 358                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 359                 status = "disabled";
 360         };
 361
 362         lcdc1:lcdc@1010e000 {
 363                 compatible = "rockchip,rk3188-lcdc";
 364                 rockchip,prop = <EXTEND>;
 365                 reg = <0x1010e000 0x1000>;
 366                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 367                 status = "disabled";
 368         };
 369
 370         pwm0: pwm@20030000{
 371                 compatible = "rockchip,pwm";
 372                 reg = <0x20030000 0x10>;
 373                 #pwm-cells = <2>;
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&pwm0_pin>;
 376                 status = "disabled";
 377
 378         };
 379
 380         pwm1: pwm@20030010{
 381                 compatible = "rockchip,pwm";
 382                 reg = <0x20030010 0x10>; /*0x20030000*/
 383                 #pwm-cells = <2>;
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&pwm1_pin>;
 386                 status = "disabled";
 387
 388         };
 389         pwm2: pwm@20050020{
 390                 compatible = "rockchip,pwm";
 391                 reg = <0x20050020 0x10>; /*0x20030000*/
 392                 #pwm-cells = <2>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&pwm2_pin>;
 395                 status = "disabled";
 396
 397         };
 398
 399         pwm3: pwm@20050030{
 400                 compatible = "rockchip,pwm";
 401                 reg = <0x20050030 0x10>; /*0x20030000*/
 402                 #pwm-cells = <2>;
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&pwm3_pin>;
 405                 status = "disabled";
 406
 407         };
 408 };