arch/arm/boot/dts/rk3188.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/rkfb/rk_fb.h>
   3 #include <dt-bindings/suspend/rockchip-pm.h>
   4 #include <dt-bindings/sensor-dev.h>
   5
   6 #include "skeleton.dtsi"
   7 #include "rk3188-pinctrl.dtsi"
   8 #include "rk3188-clocks.dtsi"
   9 #include "rk3188_io_vol_domain.dtsi"
  10 #include "rk3188-mmc.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3188";
  14         interrupt-parent = <&gic>;
  15         rockchip,sram = <&sram>;
  16
  17         aliases {
  18                 serial0 = &uart0;
  19                 serial1 = &uart1;
  20                 serial2 = &uart2;
  21                 serial3 = &uart3;
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 lcdc0 = &lcdc0;
  28                 lcdc1 = &lcdc1;
  29                 spi0 = &spi0;
  30                 spi1 = &spi1;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a9";
  40                         reg = <0>;
  41                 };
  42                 cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a9";
  45                         reg = <1>;
  46                 };
  47                 cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         reg = <2>;
  51                 };
  52                 cpu@3 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a9";
  55                         reg = <3>;
  56                 };
  57         };
  58
  59         twd-wdt@1013c620 {
  60                 compatible = "arm,cortex-a9-twd-wdt";
  61                 reg = <0x1013c620 0x20>;
  62                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  63         };
  64
  65         gic: interrupt-controller@1013d000 {
  66                 compatible = "arm,cortex-a9-gic";
  67                 interrupt-controller;
  68                 #interrupt-cells = <3>;
  69                 reg = <0x1013d000 0x1000>,
  70                       <0x1013c100 0x0100>;
  71         };
  72
  73         L2: cache-controller@10138000 {
  74                 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
  75                 reg = <0x10138000 0x1000>;
  76                 cache-unified;
  77                 cache-level = <2>;
  78                 arm,tag-latency = <1 1 1>;
  79                 arm,data-latency = <3 1 2>;
  80                 rockchip,prefetch-ctrl = <0x70000003>;
  81                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  82                 rockchip,power-ctrl = <0x3>;
  83 /*
  84                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  85                 (0x1 << 25) |   // Round-robin replacement
  86                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  87                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  88                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  89 */
  90                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  91         };
  92
  93         cpu_axi_bus: cpu_axi_bus@10128000 {
  94                 compatible = "rockchip,cpu_axi_bus";
  95                 reg = <0x10128000 0x8000>;
  96                 qos {
  97                         dmac {
  98                                 rockchip,offset = <0x1000>;
  99                                 rockchip,priority = <0 0>;
 100                         };
 101                         cpu0 {
 102                                 rockchip,offset = <0x2000>;
 103                                 rockchip,priority = <0 0>;
 104                         };
 105                         cpu1r {
 106                                 rockchip,offset = <0x2080>;
 107                                 rockchip,priority = <0 0>;
 108                         };
 109                         cpu1w {
 110                                 rockchip,offset = <0x2100>;
 111                                 rockchip,priority = <0 0>;
 112                         };
 113                         peri {
 114                                 rockchip,offset = <0x4000>;
 115                                 rockchip,priority = <2 2>;
 116                         };
 117                         gpu {
 118                                 rockchip,offset = <0x5000>;
 119                                 rockchip,priority = <2 1>;
 120                         };
 121                         vpu {
 122                                 rockchip,offset = <0x6000>;
 123                         };
 124                         vop0 {
 125                                 rockchip,offset = <0x7000>;
 126                                 rockchip,priority = <3 3>;
 127                         };
 128                         cif0 {
 129                                 rockchip,offset = <0x7080>;
 130                         };
 131                         ipp {
 132                                 rockchip,offset = <0x7100>;
 133                         };
 134                         vop1 {
 135                                 rockchip,offset = <0x7180>;
 136                                 rockchip,priority = <3 3>;
 137                         };
 138                         cif1 {
 139                                 rockchip,offset = <0x7200>;
 140                         };
 141                         rga {
 142                                 rockchip,offset = <0x7280>;
 143                         };
 144                 };
 145         };
 146
 147         bootrom@10120000 {
 148                 compatible = "rockchip,bootrom";
 149                 reg = <0x10120000 0x4000>;
 150         };
 151
 152         bootram@10080000 {
 153                 compatible = "rockchip,bootram";
 154                 reg = <0x10080000 0x20>; /* 32 bytes */
 155         };
 156
 157         sram: sram@10080020 {
 158                 compatible = "mmio-sram";
 159                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 160                 map-exec;
 161         };
 162
 163         pmu@20004000 {
 164                 compatible = "rockchip,pmu";
 165                 reg = <0x20004000 0x4000>;
 166         };
 167
 168         timer@20038000 {
 169                 compatible = "rockchip,timer";
 170                 reg = <0x20038000 0x20>;
 171                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 172                 rockchip,percpu = <0>;
 173         };
 174
 175         timer@20038020 {
 176                 compatible = "rockchip,timer";
 177                 reg = <0x20038020 0x20>;
 178                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 179                 rockchip,percpu = <1>;
 180         };
 181
 182         timer@20038040 {
 183                 compatible = "rockchip,timer";
 184                 reg = <0x20038040 0x20>;
 185                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 186                 rockchip,percpu = <2>;
 187         };
 188
 189         timer@20038060 {
 190                 compatible = "rockchip,timer";
 191                 reg = <0x20038060 0x20>;
 192                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 193                 rockchip,percpu = <3>;
 194         };
 195
 196         timer@20038080 {
 197                 compatible = "rockchip,timer";
 198                 reg = <0x20038080 0x20>;
 199                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 200                 rockchip,broadcast = <1>;
 201         };
 202
 203         timer@200380a0 {
 204                 compatible = "rockchip,timer";
 205                 reg = <0x200380a0 0x20>;
 206                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 207                 rockchip,clocksource = <1>;
 208         };
 209
 210         watchdog:wdt@2004c000 {
 211                 compatible = "rockchip,watch dog";
 212                 reg = <0x2004c000 0x100>;
 213                 clocks = <&clk_gates7 15>;
 214                 clock-names = "pclk_wdt";
 215                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 216                 rockchip,irq = <1>;
 217                 rockchip,timeout = <5>;
 218                 rockchip,atboot = <1>;
 219                 rockchip,debug = <0>;
 220                 status = "disabled";
 221         };
 222
 223         amba {
 224                 #address-cells = <1>;
 225                 #size-cells = <1>;
 226                 compatible = "arm,amba-bus";
 227                 interrupt-parent = <&gic>;
 228                 ranges;
 229
 230                 pdma0: pdma@20018000 {
 231                         compatible = "arm,pl330", "arm,primecell";
 232                         reg = <0x20018000 0x4000>;
 233                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 235                         #dma-cells = <1>;
 236
 237                 };
 238
 239                 pdma1: pdma@20078000 {
 240                         compatible = "arm,pl330", "arm,primecell";
 241                         reg = <0x20078000 0x4000>;
 242                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 244                         #dma-cells = <1>;
 245
 246                 };
 247         };
 248
 249
 250         uart0: serial@10124000 {
 251                 compatible = "rockchip,serial";
 252                 reg = <0x10124000 0x100>;
 253                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 254                 clock-frequency = <24000000>;
 255                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 256                 clock-names = "sclk_uart", "pclk_uart";
 257                 reg-shift = <2>;
 258                 reg-io-width = <4>;
 259                 dmas = <&pdma0 0>, <&pdma0 1>;
 260                 #dma-cells = <2>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 263                 status = "disabled";
 264         };
 265
 266         uart1: serial@10126000 {
 267                 compatible = "rockchip,serial";
 268                 reg = <0x10126000 0x100>;
 269                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 270                 clock-frequency = <24000000>;
 271                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 272                 clock-names = "sclk_uart", "pclk_uart";
 273                 reg-shift = <2>;
 274                 reg-io-width = <4>;
 275                 dmas = <&pdma0 2>, <&pdma0 3>;
 276                 #dma-cells = <2>;
 277                 pinctrl-names = "default";
 278                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 279                 status = "disabled";
 280         };
 281
 282         uart2: serial@20064000 {
 283                 compatible = "rockchip,serial";
 284                 reg = <0x20064000 0x100>;
 285                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 286                 clock-frequency = <24000000>;
 287                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 288                 clock-names = "sclk_uart", "pclk_uart";
 289                 current-speed = <115200>;
 290                 reg-shift = <2>;
 291                 reg-io-width = <4>;
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&uart2_xfer>;
 294                 status = "disabled";
 295         };
 296
 297         uart3: serial@20068000 {
 298                 compatible = "rockchip,serial";
 299                 reg = <0x20068000 0x100>;
 300                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 301                 clock-frequency = <24000000>;
 302                 clocks = <&clk_uart3>, <&clk_gates8 3>;
 303                 clock-names = "sclk_uart", "pclk_uart";
 304                 reg-shift = <2>;
 305                 reg-io-width = <4>;
 306                 dmas = <&pdma1 8>, <&pdma1 9>;
 307                 #dma-cells = <2>;
 308                 pinctrl-names = "default";
 309                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 310                 status = "disabled";
 311         };
 312
 313         fiq-debugger {
 314                 compatible = "rockchip,fiq-debugger";
 315                 rockchip,serial-id = <2>;
 316                 rockchip,signal-irq = <112>;
 317                 rockchip,wake-irq = <0>;
 318                 status = "disabled";
 319         };
 320
 321         spi0: spi@20070000 {
 322                 compatible = "rockchip,rockchip-spi";
 323                 reg = <0x20070000 0x1000>;
 324                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 329                 rockchip,spi-src-clk = <0>;
 330                 num-cs = <2>;
 331                 clocks =<&clk_spi0>, <&clk_gates7 12>;
 332                 clock-names = "spi","pclk_spi0";
 333                 dmas = <&pdma1 10>, <&pdma1 11>;
 334                 #dma-cells = <2>;
 335                 dma-names = "tx", "rx";
 336                 status = "disabled";
 337         };
 338
 339         spi1: spi@20074000 {
 340                 compatible = "rockchip,rockchip-spi";
 341                 reg = <0x20074000 0x1000>;
 342                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0 &spi1_cs1>;
 347                 rockchip,spi-src-clk = <1>;
 348                 num-cs = <2>;
 349                 clocks = <&clk_spi1>, <&clk_gates7 13>;
 350                 clock-names = "spi","pclk_spi1";
 351                 dmas = <&pdma1 12>, <&pdma1 13>;
 352                 #dma-cells = <2>;
 353                 dma-names = "tx", "rx";
 354                 status = "disabled";
 355         };
 356
 357         i2c0: i2c@2002d000 {
 358                 compatible = "rockchip,rk30-i2c";
 359                 reg = <0x2002d000 0x1000>;
 360                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 pinctrl-names = "default", "gpio";
 364                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 365                 pinctrl-1 = <&i2c0_gpio>;
 366                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 367                 clocks = <&clk_gates8 4>;
 368                 rockchip,check-idle = <1>;
 369                 status = "disabled";
 370         };
 371
 372         i2c1: i2c@2002f000 {
 373                 compatible = "rockchip,rk30-i2c";
 374                 reg = <0x2002f000 0x1000>;
 375                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 pinctrl-names = "default", "gpio";
 379                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 380                 pinctrl-1 = <&i2c1_gpio>;
 381                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 382                 clocks = <&clk_gates8 5>;
 383                 rockchip,check-idle = <1>;
 384                 status = "disabled";
 385         };
 386
 387         i2c2: i2c@20056000 {
 388                 compatible = "rockchip,rk30-i2c";
 389                 reg = <0x20056000 0x1000>;
 390                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 pinctrl-names = "default", "gpio";
 394                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 395                 pinctrl-1 = <&i2c2_gpio>;
 396                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 397                 clocks = <&clk_gates8 6>;
 398                 rockchip,check-idle = <1>;
 399                 status = "disabled";
 400         };
 401
 402         i2c3: i2c@2005a000 {
 403                 compatible = "rockchip,rk30-i2c";
 404                 reg = <0x2005a000 0x1000>;
 405                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 pinctrl-names = "default", "gpio";
 409                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 410                 pinctrl-1 = <&i2c3_gpio>;
 411                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 412                 clocks = <&clk_gates8 7>;
 413                 rockchip,check-idle = <1>;
 414                 status = "disabled";
 415         };
 416
 417         i2c4: i2c@2005e000 {
 418                 compatible = "rockchip,rk30-i2c";
 419                 reg = <0x2005e000 0x1000>;
 420                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 pinctrl-names = "default", "gpio";
 424                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 425                 pinctrl-1 = <&i2c4_gpio>;
 426                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 427                 clocks = <&clk_gates8 8>;
 428                 rockchip,check-idle = <1>;
 429                 status = "disabled";
 430         };
 431
 432         clocks-init{
 433                 compatible = "rockchip,clocks-init";
 434                 rockchip,clocks-init-parent =
 435                         <&clk_core &clk_apll>,  <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
 436                         <&aclk_peri_mux &clk_gpll>,     <&clk_i2s_pll_mux &clk_cpll>,
 437                         <&clk_uart_pll_mux &clk_gpll>;
 438                 rockchip,clocks-init-rate =
 439                         <&clk_core 792000000>,  <&clk_gpll 768000000>,
 440                         <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
 441                         <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
 442                         <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
 443                         <&hclk_peri 96000000>,  <&pclk_peri 48000000>,
 444                         <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
 445                         <&aclk_lcdc1 300000000>;
 446         };
 447         rkpm_suspend {
 448                 compatible = "rockchip,rkpm_suspend";
 449
 450                 // define value is in dt-bindint/suspend/rockchip-pm.h
 451                 rockchip,ctrbits = <
 452                                                 (
 453                                                 RKPM_CTR_PWR_DMNS
 454                                                 |RKPM_CTR_GTCLKS
 455                                                 |RKPM_CTR_PLLS
 456                                                 |RKPM_CTR_SYSCLK_DIV
 457                                                 |RKPM_CTR_NORIDLE_MD
 458                                                 )
 459                                         >;
 460               rockchip,pmic-gpios=<
 461                                                 RKPM_GPIOS_SETTING(GPIO0_A0,RKPM_GPIOS_OUTPUT,RKPM_GPIOS_OUT_H)
 462                                                 RKPM_GPIOS_SETTING(GPIO0_A1,RKPM_GPIOS_OUTPUT,RKPM_GPIOS_OUT_H)
 463                                                 >;
 464
 465         };
 466         fb: fb{
 467                 compatible = "rockchip,rk-fb";
 468                 rockchip,disp-mode = <DUAL>;
 469         };
 470
 471         rk_screen: rk_screen{
 472                 compatible = "rockchip,screen";
 473         };
 474
 475         nandc: nandc {
 476                 compatible = "rockchip,rk-nandc";
 477                 reg = <0x10050000 0x4000>;
 478                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 479         };
 480
 481         lcdc0:lcdc@1010c000 {
 482                 compatible = "rockchip,rk3188-lcdc";
 483                 rockchip,prop = <PRMRY>;
 484                 rochchip,pwr18 = <0>;
 485                 reg = <0x1010c000 0x1000>;
 486                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 487                 status = "disabled";
 488         };
 489
 490         lcdc1:lcdc@1010e000 {
 491                 compatible = "rockchip,rk3188-lcdc";
 492                 rockchip,prop = <EXTEND>;
 493                 rockchip,pwr18 = <0>;
 494                 reg = <0x1010e000 0x1000>;
 495                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 496                 pinctrl-names = "default", "gpio";
 497                 pinctrl-0 = <&lcdc1_lcdc>;
 498                 pinctrl-1 = <&lcdc1_gpio>;
 499                 status = "disabled";
 500         };
 501
 502         rga@10114000 {
 503                 compatible = "rockchip,rga";
 504                 reg = <0x10114000 0x1000>;
 505                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 506                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 507                 clock-names = "hclk_rga", "aclk_rga";
 508         };
 509
 510         adc: adc@2006c000 {
 511                 compatible = "rockchip,saradc";
 512                 reg = <0x2006c000 0x100>;
 513                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 514                 #io-channel-cells = <1>;
 515                 io-channel-ranges;
 516                 rockchip,adc-vref = <1800>;
 517                 clock-frequency = <1000000>;
 518                 clocks = <&clk_saradc>, <&clk_gates7 14>;
 519                 clock-names = "saradc", "pclk_saradc";
 520                 status = "disabled";
 521         };
 522
 523         spdif: rockchip-spdif@0x1011e000 {
 524                 compatible = "rockchip-spdif";
 525                 reg = <0x1011e000 0x2000>;
 526                 clocks = <&clk_spdif>;
 527                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 528                 dmas = <&pdma0 8>;
 529                 dma-names = "tx";
 530                 pinctrl-names = "default";
 531                 pinctrl-0 = <&spdif_tx>;
 532         };
 533
 534         i2s0: rockchip-i2s@0x1011a000 {
 535                 compatible = "rockchip-i2s";
 536                 reg = <0x1011a000 0x2000>;
 537                 i2s-id = <0>;
 538                 clocks = <&clk_i2s>;
 539                 clock-names = "i2s_clk";
 540                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 541                 dmas = <&pdma0 6>,
 542                         <&pdma0 7>;
 543                 dma-names = "tx", "rx";
 544                 pinctrl-names = "default", "sleep";
 545                 pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 546                 pinctrl-1 = <&i2s0_gpio>;
 547         };
 548
 549         pwm0: pwm@20030000{
 550                 compatible = "rockchip,pwm";
 551                 reg = <0x20030000 0x10>;
 552                 #pwm-cells = <2>;
 553                 pinctrl-names = "default";
 554                 pinctrl-0 = <&pwm0_pin>;
 555                 status = "disabled";
 556
 557         };
 558
 559         pwm1: pwm@20030010{
 560                 compatible = "rockchip,pwm";
 561                 reg = <0x20030010 0x10>; /*0x20030000*/
 562                 #pwm-cells = <2>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&pwm1_pin>;
 565                 status = "disabled";
 566
 567         };
 568         pwm2: pwm@20050020{
 569                 compatible = "rockchip,pwm";
 570                 reg = <0x20050020 0x10>; /*0x20030000*/
 571                 #pwm-cells = <2>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&pwm2_pin>;
 574                 status = "disabled";
 575
 576         };
 577
 578         pwm3: pwm@20050030{
 579                 compatible = "rockchip,pwm";
 580                 reg = <0x20050030 0x10>; /*0x20030000*/
 581                 #pwm-cells = <2>;
 582                 pinctrl-names = "default";
 583                 pinctrl-0 = <&pwm3_pin>;
 584                 status = "disabled";
 585
 586         };
 587         dvfs {
 588                 vd_cpu:
 589                 vd_cpu {
 590                         regulator_name="vdd_arm";
 591                         suspend_volt=<1000>; //mV
 592                         pd_a9 {
 593                                 clk_core_dvfs_table:
 594                                 clk_core {
 595                                         operating-points = <
 596                                                 /* KHz    uV */
 597                                                 312000 900000
 598                                                 504000 950000
 599                                                 816000 1000000
 600                                                 1008000 1100000
 601                                                 1200000 1200000
 602                                                 1416000 1300000
 603                                                 1608000 1350000
 604                                                 >;
 605                                 };
 606                         };
 607                 };
 608
 609                 vd_core:
 610                 vd_core {
 611                         regulator_name="vdd_logic";
 612                         suspend_volt=<1000>; //mV
 613
 614                         pd_gpu {
 615                                 clk_gpu_dvfs_table:
 616                                 clk_gpu {
 617                                         operating-points = <
 618                                                 /* KHz    uV */
 619                                                 200000 1200000
 620                                                 300000 1200000
 621                                                 400000 1200000
 622                                                 >;
 623                                 };
 624                         };
 625
 626                         pd_ddr {
 627                                 clk_ddr_dvfs_table:
 628                                 clk_ddr {
 629                                         operating-points = <
 630                                                 /* KHz    uV */
 631                                                 200000 1200000
 632                                                 300000 1200000
 633                                                 400000 1200000
 634                                                 >;
 635                                 };
 636                         };
 637                 };
 638         };
 639         ion{
 640                 compatible = "rockchip,ion";
 641                 #address-cells = <1>;
 642                 #size-cells = <0>;
 643                 rockchip,ion-heap@1 { /* CMA HEAP */
 644                         compatible = "rockchip,ion-reserve";
 645                         reg = <1>;
 646                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 647                 };
 648                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 649                         reg = <3>;
 650                 };
 651         };
 652
 653         dwc_control_usb: dwc-control-usb@200080ac {
 654                 compatible = "rockchip,rk3188-dwc-control-usb";
 655                 reg = <0x200080ac 0x4>,
 656                       <0x2000810c 0x10>,
 657                       <0x2000811c 0x10>,
 658                       <0x2000812c 0x8>,
 659                       <0x20008138 0x8>;
 660                 reg-names = "GRF_SOC_STATUS0",
 661                             "GRF_UOC0_BASE",
 662                             "GRF_UOC1_BASE",
 663                             "GRF_UOC2_BASE",
 664                             "GRF_UOC3_BASE";
 665                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 666                 interrupt-names = "otg_bvalid";
 667                 gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 668                 clocks = <&clk_gates4 5>;
 669                 clock-names = "hclk_usb_peri";
 670         };
 671
 672         usb@10180000 {
 673                 compatible = "rockchip,rk3188_usb20_otg";
 674                 reg = <0x10180000 0x40000>;
 675                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 676                 clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;
 677                 clock-names = "otgphy0", "hclk_otg0";
 678         };
 679
 680         usb@101c0000 {
 681                 compatible = "rockchip,rk3188_usb20_host";
 682                 reg = <0x101c0000 0x40000>;
 683                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 684                 clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;
 685                 clock-names = "otgphy1", "hclk_otg1";
 686         };
 687
 688         hsic@10240000 {
 689                 compatible = "rockchip,rk3188_rk_hsic_host";
 690                 reg = <0x10240000 0x40000>;
 691                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 692                 clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
 693                          <&clk_hsicphy12m>, <&clk_otgphy1_480m>;
 694                 clock-names = "hsicphy480m", "hclk_hsic",
 695                               "hsicphy12m", "hsic_otgphy1";
 696         };
 697
 698         vmac@10204000 {
 699                 compatible = "rockchip,vmac";
 700                 reg = <0x10204000 0x4000>;
 701                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 702                 pinctrl-names = "default", "gpio";
 703                 pinctrl-0 = <&rmii_clkoutpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
 704                 pinctrl-1 = <&rmii_clkinpin &rmii_txpins &rmii_rxpins &rmii_mdpins>;
 705         };
 706 };