arch/arm/boot/dts/rk3188.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4
   5 / {
   6         compatible = "rockchip,rk3188";
   7         interrupt-parent = <&gic>;
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         device_type = "cpu";
  15                         compatible = "arm,cortex-a9";
  16                         reg = <0>;
  17                 };
  18                 cpu@1 {
  19                         device_type = "cpu";
  20                         compatible = "arm,cortex-a9";
  21                         reg = <1>;
  22                 };
  23                 cpu@2 {
  24                         device_type = "cpu";
  25                         compatible = "arm,cortex-a9";
  26                         reg = <2>;
  27                 };
  28                 cpu@3 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a9";
  31                         reg = <3>;
  32                 };
  33         };
  34
  35         twd-wdt@1013c620 {
  36                 compatible = "arm,cortex-a9-twd-wdt";
  37                 reg = <0x1013c620 0x20>;
  38                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  39         };
  40
  41         gic: interrupt-controller@1013d000 {
  42                 compatible = "arm,cortex-a9-gic";
  43                 interrupt-controller;
  44                 #interrupt-cells = <3>;
  45                 reg = <0x1013d000 0x1000>,
  46                       <0x1013c100 0x0100>;
  47         };
  48
  49         L2: cache-controller@10138000 {
  50                 compatible = "arm,pl310-cache";
  51                 reg = <0x10138000 0x1000>;
  52                 cache-unified;
  53                 cache-level = <2>;
  54                 arm,tag-latency = <1 1 1>;
  55                 arm,data-latency = <2 3 1>;
  56         };
  57
  58         bootrom@10120000 {
  59                 compatible = "rockchip,bootrom";
  60                 reg = <0x10120000 0x4000>;
  61         };
  62
  63         bootram@10080000 {
  64                 compatible = "rockchip,bootram";
  65                 reg = <0x10080000 0x20>; /* 32 bytes */
  66         };
  67
  68         sram@10080020 {
  69                 compatible = "mmio-sram";
  70                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
  71                 map-exec;
  72         };
  73
  74         pmu@20004000 {
  75                 compatible = "rockchip,pmu";
  76                 reg = <0x20004000 0x4000>;
  77         };
  78
  79         timer@200380a0 {
  80                 compatible = "rockchip,timer";
  81                 reg = <0x200380a0 0x20>;
  82                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  83         };
  84
  85         timer@20038000 {
  86                 compatible = "rockchip,timer";
  87                 reg = <0x20038000 0x20>;
  88                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  89         };
  90
  91         timer@20038020 {
  92                 compatible = "rockchip,timer";
  93                 reg = <0x20038020 0x20>;
  94                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  95         };
  96
  97         timer@20038060 {
  98                 compatible = "rockchip,timer";
  99                 reg = <0x20038060 0x20>;
 100                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 101         };
 102
 103         timer@20038080 {
 104                 compatible = "rockchip,timer";
 105                 reg = <0x20038080 0x20>;
 106                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 107         };
 108
 109         uart0: serial@10124000 {
 110                 compatible = "rockchip,serial";
 111                 reg = <0x10124000 0x100>;
 112                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 113                 clock-frequency = <24000000>;
 114                 reg-shift = <2>;
 115                 reg-io-width = <4>;
 116                 id = <0>;
 117                 status = "disabled";
 118         };
 119
 120         uart1: serial@10126000 {
 121                 compatible = "rockchip,serial";
 122                 reg = <0x10126000 0x100>;
 123                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 124                 clock-frequency = <24000000>;
 125                 reg-shift = <2>;
 126                 reg-io-width = <4>;
 127                 id = <1>;
 128                 status = "disabled";
 129         };
 130
 131         uart2: serial@20064000 {
 132                 compatible = "rockchip,serial";
 133                 reg = <0x20064000 0x100>;
 134                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 135                 clock-frequency = <24000000>;
 136                 current-speed = <115200>;
 137                 reg-shift = <2>;
 138                 reg-io-width = <4>;
 139                 id = <2>;
 140                 status = "disabled";
 141         };
 142
 143         uart3: serial@20068000 {
 144                 compatible = "rockchip,serial";
 145                 reg = <0x20068000 0x100>;
 146                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 147                 clock-frequency = <24000000>;
 148                 reg-shift = <2>;
 149                 reg-io-width = <4>;
 150                 id = <3>;
 151                 status = "disabled";
 152         };
 153 };