arch/arm/boot/dts/rk3188.dtsi

   1
   2 #include "skeleton.dtsi"
   3 #include "rk3188-pinctrl.dtsi"
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5
   6
   7 / {
   8         compatible = "rockchip,rk3188";
   9         interrupt-parent = <&gic>;
  10         rockchip,sram = <&sram>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 serial2 = &uart2;
  16                 serial3 = &uart3;
  17                 i2c0 = &i2c0;
  18                 i2c1 = &i2c1;
  19                 i2c2 = &i2c2;
  20                 i2c3 = &i2c3;
  21                 i2c4 = &i2c4;
  22                 lcdc0 = &lcdc0;
  23                 lcdc1 = &lcdc1;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         reg = <0>;
  34                 };
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         reg = <1>;
  39                 };
  40                 cpu@2 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a9";
  43                         reg = <2>;
  44                 };
  45                 cpu@3 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a9";
  48                         reg = <3>;
  49                 };
  50         };
  51
  52         twd-wdt@1013c620 {
  53                 compatible = "arm,cortex-a9-twd-wdt";
  54                 reg = <0x1013c620 0x20>;
  55                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  56         };
  57
  58         gic: interrupt-controller@1013d000 {
  59                 compatible = "arm,cortex-a9-gic";
  60                 interrupt-controller;
  61                 #interrupt-cells = <3>;
  62                 reg = <0x1013d000 0x1000>,
  63                       <0x1013c100 0x0100>;
  64         };
  65
  66         L2: cache-controller@10138000 {
  67                 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
  68                 reg = <0x10138000 0x1000>;
  69                 cache-unified;
  70                 cache-level = <2>;
  71                 arm,tag-latency = <1 1 1>;
  72                 arm,data-latency = <3 1 2>;
  73                 rockchip,prefetch-ctrl = <0x70000003>;
  74                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  75                 rockchip,power-ctrl = <0x3>;
  76 /*
  77                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  78                 (0x1 << 25) |   // Round-robin replacement
  79                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  80                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  81                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  82 */
  83                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  84         };
  85
  86         cpu_axi_bus: cpu_axi_bus@10128000 {
  87                 compatible = "rockchip,cpu_axi_bus";
  88                 reg = <0x10128000 0x8000>;
  89                 qos {
  90                         dmac {
  91                                 rockchip,offset = <0x1000>;
  92                                 rockchip,priority = <0 0>;
  93                         };
  94                         cpu0 {
  95                                 rockchip,offset = <0x2000>;
  96                                 rockchip,priority = <0 0>;
  97                         };
  98                         cpu1r {
  99                                 rockchip,offset = <0x2080>;
 100                                 rockchip,priority = <0 0>;
 101                         };
 102                         cpu1w {
 103                                 rockchip,offset = <0x2100>;
 104                                 rockchip,priority = <0 0>;
 105                         };
 106                         peri {
 107                                 rockchip,offset = <0x4000>;
 108                                 rockchip,priority = <2 2>;
 109                         };
 110                         gpu {
 111                                 rockchip,offset = <0x5000>;
 112                                 rockchip,priority = <2 1>;
 113                         };
 114                         vpu {
 115                                 rockchip,offset = <0x6000>;
 116                         };
 117                         vop0 {
 118                                 rockchip,offset = <0x7000>;
 119                                 rockchip,priority = <3 3>;
 120                         };
 121                         cif0 {
 122                                 rockchip,offset = <0x7080>;
 123                         };
 124                         ipp {
 125                                 rockchip,offset = <0x7100>;
 126                         };
 127                         vop1 {
 128                                 rockchip,offset = <0x7180>;
 129                                 rockchip,priority = <3 3>;
 130                         };
 131                         cif1 {
 132                                 rockchip,offset = <0x7200>;
 133                         };
 134                         rga {
 135                                 rockchip,offset = <0x7280>;
 136                         };
 137                 };
 138         };
 139
 140         bootrom@10120000 {
 141                 compatible = "rockchip,bootrom";
 142                 reg = <0x10120000 0x4000>;
 143         };
 144
 145         bootram@10080000 {
 146                 compatible = "rockchip,bootram";
 147                 reg = <0x10080000 0x20>; /* 32 bytes */
 148         };
 149
 150         sram: sram@10080020 {
 151                 compatible = "mmio-sram";
 152                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 153                 map-exec;
 154         };
 155
 156         pmu@20004000 {
 157                 compatible = "rockchip,pmu";
 158                 reg = <0x20004000 0x4000>;
 159         };
 160
 161         timer@20038000 {
 162                 compatible = "rockchip,timer";
 163                 reg = <0x20038000 0x20>;
 164                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 165                 rockchip,percpu = <0>;
 166         };
 167
 168         timer@20038020 {
 169                 compatible = "rockchip,timer";
 170                 reg = <0x20038020 0x20>;
 171                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 172                 rockchip,percpu = <1>;
 173         };
 174
 175         timer@20038040 {
 176                 compatible = "rockchip,timer";
 177                 reg = <0x20038040 0x20>;
 178                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 179                 rockchip,percpu = <2>;
 180         };
 181
 182         timer@20038060 {
 183                 compatible = "rockchip,timer";
 184                 reg = <0x20038060 0x20>;
 185                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 186                 rockchip,percpu = <3>;
 187         };
 188
 189         timer@20038080 {
 190                 compatible = "rockchip,timer";
 191                 reg = <0x20038080 0x20>;
 192                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 193                 rockchip,broadcast = <1>;
 194         };
 195
 196         timer@200380a0 {
 197                 compatible = "rockchip,timer";
 198                 reg = <0x200380a0 0x20>;
 199                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 200                 rockchip,clocksource = <1>;
 201         };
 202
 203     amba {
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 compatible = "arm,amba-bus";
 207                 interrupt-parent = <&gic>;
 208                 ranges;
 209
 210         pdma0: pdma@20018000 {
 211             compatible = "arm,pl330", "arm,primecell";
 212             reg = <0x20018000 0x4000>;
 213             interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 214                          <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 215             #dma-cells = <1>;
 216                         #dma-channels = <9>;
 217                         #dma-requests = <10>;
 218         };
 219
 220         pdma1: pdma@20078000 {
 221             compatible = "arm,pl330", "arm,primecell";
 222             reg = <0x20078000 0x4000>;
 223             interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 224                          <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 225             #dma-cells = <1>;
 226                         #dma-channels = <7>;
 227                         #dma-requests = <14>;
 228         };
 229     };
 230
 231         uart0: serial@10124000 {
 232                 compatible = "rockchip,serial";
 233                 reg = <0x10124000 0x100>;
 234                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 235                 clock-frequency = <24000000>;
 236                 reg-shift = <2>;
 237                 reg-io-width = <4>;
 238                 pinctrl-names = "default";
 239                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 240                 status = "disabled";
 241         };
 242
 243         uart1: serial@10126000 {
 244                 compatible = "rockchip,serial";
 245                 reg = <0x10126000 0x100>;
 246                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 247                 clock-frequency = <24000000>;
 248                 reg-shift = <2>;
 249                 reg-io-width = <4>;
 250                 pinctrl-names = "default";
 251                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 252                 status = "disabled";
 253         };
 254
 255         uart2: serial@20064000 {
 256                 compatible = "rockchip,serial";
 257                 reg = <0x20064000 0x100>;
 258                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 259                 clock-frequency = <24000000>;
 260                 current-speed = <115200>;
 261                 reg-shift = <2>;
 262                 reg-io-width = <4>;
 263                 pinctrl-names = "default";
 264                 pinctrl-0 = <&uart2_xfer>;
 265                 status = "disabled";
 266         };
 267
 268         uart3: serial@20068000 {
 269                 compatible = "rockchip,serial";
 270                 reg = <0x20068000 0x100>;
 271                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 272                 clock-frequency = <24000000>;
 273                 reg-shift = <2>;
 274                 reg-io-width = <4>;
 275                 pinctrl-names = "default";
 276                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 277                 status = "disabled";
 278         };
 279
 280         fiq-debugger {
 281                 compatible = "rockchip,fiq-debugger";
 282                 rockchip,serial-id = <2>;
 283                 rockchip,signal-irq = <112>;
 284                 rockchip,wake-irq = <0>;
 285                 status = "disabled";
 286         };
 287
 288         i2c0: i2c@2002d000 {
 289                 compatible = "rockchip,rk30-i2c";
 290                 reg = <0x2002d000 0x1000>;
 291                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 pinctrl-names = "default", "gpio";
 295                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 296                 pinctrl-1 = <&i2c0_gpio>;
 297                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 298                 clocks = <&clk_gates8 4>;
 299                 rockchip,check-idle = <1>;
 300                 status = "disabled";
 301         };
 302
 303         i2c1: i2c@2002f000 {
 304                 compatible = "rockchip,rk30-i2c";
 305                 reg = <0x2002f000 0x1000>;
 306                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 pinctrl-names = "default", "gpio";
 310                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 311                 pinctrl-1 = <&i2c1_gpio>;
 312                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 313                 clocks = <&clk_gates8 5>;
 314                 rockchip,check-idle = <1>;
 315                 status = "disabled";
 316         };
 317
 318         i2c2: i2c@20055000 {
 319                 compatible = "rockchip,rk30-i2c";
 320                 reg = <0x20055000 0x1000>;
 321                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 pinctrl-names = "default", "gpio";
 325                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 326                 pinctrl-1 = <&i2c2_gpio>;
 327                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 328                 clocks = <&clk_gates8 6>;
 329                 rockchip,check-idle = <1>;
 330                 status = "disabled";
 331         };
 332
 333         i2c3: i2c@20059000 {
 334                 compatible = "rockchip,rk30-i2c";
 335                 reg = <0x20059000 0x1000>;
 336                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 pinctrl-names = "default", "gpio";
 340                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 341                 pinctrl-1 = <&i2c3_gpio>;
 342                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 343                 clocks = <&clk_gates8 7>;
 344                 rockchip,check-idle = <1>;
 345                 status = "disabled";
 346         };
 347
 348         i2c4: i2c@2005d000 {
 349                 compatible = "rockchip,rk30-i2c";
 350                 reg = <0x2005d000 0x1000>;
 351                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 pinctrl-names = "default", "gpio";
 355                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 356                 pinctrl-1 = <&i2c4_gpio>;
 357                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 358                 clocks = <&clk_gates8 8>;
 359                 rockchip,check-idle = <1>;
 360                 status = "disabled";
 361         };
 362
 363         clocks-init{
 364                 compatible = "rockchip,clocks-init";
 365                 rockchip,clocks-init-parent =
 366                         <&clk_core &clk_apll>,  <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
 367                         <&aclk_peri_mux &clk_gpll>,     <&clk_i2s_pll_mux &clk_cpll>,
 368                         <&clk_uart_pll_mux &clk_gpll>;
 369                 rockchip,clocks-init-rate =
 370                         <&clk_core 594000000>,  <&clk_gpll 768000000>,
 371                         <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
 372                         <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
 373                         <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
 374                         <&hclk_peri 96000000>,  <&pclk_peri 48000000>,
 375                         <&clk_gpu 200000000>;
 376         };
 377
 378         fb: fb{
 379                 compatible = "rockchip,rk-fb";
 380                 rockchip,disp-mode = <DUAL>;
 381         };
 382
 383         nandc: nandc {
 384                 compatible = "rockchip,rk-nandc";
 385                 reg = <0x10050000 0x4000>;
 386                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 387         };
 388
 389         lcdc0:lcdc@1010c000 {
 390                 compatible = "rockchip,rk3188-lcdc";
 391                 rockchip,prop = <PRMRY>;
 392                 rochchip,pwr18 = <0>;
 393                 reg = <0x1010c000 0x1000>;
 394                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 395                 status = "disabled";
 396         };
 397
 398         lcdc1:lcdc@1010e000 {
 399                 compatible = "rockchip,rk3188-lcdc";
 400                 rockchip,prop = <EXTEND>;
 401                 rockchip,pwr18 = <0>;
 402                 reg = <0x1010e000 0x1000>;
 403                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 404                 pinctrl-names = "default", "gpio";
 405                 pinctrl-0 = <&lcdc1_lcdc>;
 406                 pinctrl-1 = <&lcdc1_gpio>;
 407                 status = "disabled";
 408         };
 409
 410         pwm0: pwm@20030000{
 411                 compatible = "rockchip,pwm";
 412                 reg = <0x20030000 0x10>;
 413                 #pwm-cells = <2>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&pwm0_pin>;
 416                 status = "disabled";
 417
 418         };
 419
 420         pwm1: pwm@20030010{
 421                 compatible = "rockchip,pwm";
 422                 reg = <0x20030010 0x10>; /*0x20030000*/
 423                 #pwm-cells = <2>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&pwm1_pin>;
 426                 status = "disabled";
 427
 428         };
 429         pwm2: pwm@20050020{
 430                 compatible = "rockchip,pwm";
 431                 reg = <0x20050020 0x10>; /*0x20030000*/
 432                 #pwm-cells = <2>;
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&pwm2_pin>;
 435                 status = "disabled";
 436
 437         };
 438
 439         pwm3: pwm@20050030{
 440                 compatible = "rockchip,pwm";
 441                 reg = <0x20050030 0x10>; /*0x20030000*/
 442                 #pwm-cells = <2>;
 443                 pinctrl-names = "default";
 444                 pinctrl-0 = <&pwm3_pin>;
 445                 status = "disabled";
 446
 447         };
 448         dvfs {
 449                 vd_cpu:
 450                 vd_cpu {
 451                         regulator_name="vdd_arm";
 452                         suspend_volt=<1000>; //mV
 453                         pd_a9 {
 454                                 clk_core_dvfs_table:
 455                                 clk_core {
 456                                         operating-points = <
 457                                                 /* KHz    uV */
 458                                                 312000 900000
 459                                                 504000 950000
 460                                                 816000 1000000
 461                                                 1008000 1100000
 462                                                 1200000 1200000
 463                                                 1416000 1300000
 464                                                 1608000 1350000
 465                                                 >;
 466                                 };
 467                         };
 468                 };
 469
 470                 vd_core:
 471                 vd_core {
 472                         regulator_name="vdd_logic";
 473                         suspend_volt=<1000>; //mV
 474
 475                         pd_gpu {
 476                                 clk_gpu_dvfs_table:
 477                                 clk_gpu {
 478                                         operating-points = <
 479                                                 /* KHz    uV */
 480                                                 200000 1200000
 481                                                 300000 1200000
 482                                                 400000 1200000
 483                                                 >;
 484                                 };
 485                         };
 486
 487                         pd_ddr {
 488                                 clk_ddr_dvfs_table:
 489                                 clk_ddr {
 490                                         operating-points = <
 491                                                 /* KHz    uV */
 492                                                 200000 1200000
 493                                                 300000 1200000
 494                                                 400000 1200000
 495                                                 >;
 496                                 };
 497                         };
 498                 };
 499         };
 500 };