2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/rockchip.h>
18 #include "rk3xxx.dtsi"
19 #include "rk3188-clocks.dtsi"
22 compatible = "rockchip,rk3188";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
42 compatible = "arm,cortex-a9";
43 next-level-cache = <&L2>;
48 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
55 global-timer@1013c200 {
56 interrupts = <GIC_PPI 11 0xf04>;
59 local-timer@1013c600 {
60 interrupts = <GIC_PPI 13 0xf04>;
64 compatible = "mmio-sram";
65 reg = <0x10080000 0x8000>;
68 ranges = <0 0x10080000 0x8000>;
71 compatible = "rockchip,rk3066-smp-sram";
77 compatible = "rockchip,rk3188-pinctrl";
78 rockchip,grf = <&grf>;
79 rockchip,pmu = <&pmu>;
85 gpio0: gpio0@0x2000a000 {
86 compatible = "rockchip,rk3188-gpio-bank0";
87 reg = <0x2000a000 0x100>;
88 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&clk_gates8 9>;
95 #interrupt-cells = <2>;
98 gpio1: gpio1@0x2003c000 {
99 compatible = "rockchip,gpio-bank";
100 reg = <0x2003c000 0x100>;
101 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&clk_gates8 10>;
107 interrupt-controller;
108 #interrupt-cells = <2>;
111 gpio2: gpio2@2003e000 {
112 compatible = "rockchip,gpio-bank";
113 reg = <0x2003e000 0x100>;
114 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&clk_gates8 11>;
120 interrupt-controller;
121 #interrupt-cells = <2>;
124 gpio3: gpio3@20080000 {
125 compatible = "rockchip,gpio-bank";
126 reg = <0x20080000 0x100>;
127 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&clk_gates8 12>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
137 pcfg_pull_up: pcfg_pull_up {
141 pcfg_pull_down: pcfg_pull_down {
145 pcfg_pull_none: pcfg_pull_none {
150 uart0_xfer: uart0-xfer {
151 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
152 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
155 uart0_cts: uart0-cts {
156 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
159 uart0_rts: uart0-rts {
160 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
165 uart1_xfer: uart1-xfer {
166 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
167 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
170 uart1_cts: uart1-cts {
171 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
174 uart1_rts: uart1-rts {
175 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
180 uart2_xfer: uart2-xfer {
181 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
182 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
184 /* no rts / cts for uart2 */
188 uart3_xfer: uart3-xfer {
189 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
190 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
193 uart3_cts: uart3-cts {
194 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
197 uart3_rts: uart3-rts {
198 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
204 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
208 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
212 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
216 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
220 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
223 sd0_bus1: sd0-bus-width1 {
224 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
227 sd0_bus4: sd0-bus-width4 {
228 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
229 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
230 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
231 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
237 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
241 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
245 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
249 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
252 sd1_bus1: sd1-bus-width1 {
253 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
256 sd1_bus4: sd1-bus-width4 {
257 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
258 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
259 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
260 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;