arch/arm/boot/dts/rk3188.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/pinctrl/rockchip.h>
  18 #include <dt-bindings/clock/rk3188-cru.h>
  19 #include "rk3xxx.dtsi"
  20 #include "rk3188-clocks.dtsi"
  21
  22 / {
  23         compatible = "rockchip,rk3188";
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28                 enable-method = "rockchip,rk3066-smp";
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         next-level-cache = <&L2>;
  34                         reg = <0x0>;
  35                 };
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a9";
  39                         next-level-cache = <&L2>;
  40                         reg = <0x1>;
  41                 };
  42                 cpu@2 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a9";
  45                         next-level-cache = <&L2>;
  46                         reg = <0x2>;
  47                 };
  48                 cpu@3 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a9";
  51                         next-level-cache = <&L2>;
  52                         reg = <0x3>;
  53                 };
  54         };
  55
  56         soc {
  57                 global-timer@1013c200 {
  58                         interrupts = <GIC_PPI 11 0xf04>;
  59                 };
  60
  61                 local-timer@1013c600 {
  62                         interrupts = <GIC_PPI 13 0xf04>;
  63                 };
  64
  65                 sram: sram@10080000 {
  66                         compatible = "mmio-sram";
  67                         reg = <0x10080000 0x8000>;
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         ranges = <0 0x10080000 0x8000>;
  71
  72                         smp-sram@0 {
  73                                 compatible = "rockchip,rk3066-smp-sram";
  74                                 reg = <0x0 0x50>;
  75                         };
  76                 };
  77
  78                 cru: clock-controller@20000000 {
  79                         compatible = "rockchip,rk3188-cru";
  80                         reg = <0x20000000 0x1000>;
  81                         rockchip,grf = <&grf>;
  82
  83                         #clock-cells = <1>;
  84                         #reset-cells = <1>;
  85                 };
  86
  87                 pinctrl@20008000 {
  88                         compatible = "rockchip,rk3188-pinctrl";
  89                         rockchip,grf = <&grf>;
  90                         rockchip,pmu = <&pmu>;
  91
  92                         #address-cells = <1>;
  93                         #size-cells = <1>;
  94                         ranges;
  95
  96                         gpio0: gpio0@0x2000a000 {
  97                                 compatible = "rockchip,rk3188-gpio-bank0";
  98                                 reg = <0x2000a000 0x100>;
  99                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 100                                 clocks = <&cru PCLK_GPIO0>;
 101
 102                                 gpio-controller;
 103                                 #gpio-cells = <2>;
 104
 105                                 interrupt-controller;
 106                                 #interrupt-cells = <2>;
 107                         };
 108
 109                         gpio1: gpio1@0x2003c000 {
 110                                 compatible = "rockchip,gpio-bank";
 111                                 reg = <0x2003c000 0x100>;
 112                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 113                                 clocks = <&cru PCLK_GPIO1>;
 114
 115                                 gpio-controller;
 116                                 #gpio-cells = <2>;
 117
 118                                 interrupt-controller;
 119                                 #interrupt-cells = <2>;
 120                         };
 121
 122                         gpio2: gpio2@2003e000 {
 123                                 compatible = "rockchip,gpio-bank";
 124                                 reg = <0x2003e000 0x100>;
 125                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 126                                 clocks = <&cru PCLK_GPIO2>;
 127
 128                                 gpio-controller;
 129                                 #gpio-cells = <2>;
 130
 131                                 interrupt-controller;
 132                                 #interrupt-cells = <2>;
 133                         };
 134
 135                         gpio3: gpio3@20080000 {
 136                                 compatible = "rockchip,gpio-bank";
 137                                 reg = <0x20080000 0x100>;
 138                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 139                                 clocks = <&cru PCLK_GPIO3>;
 140
 141                                 gpio-controller;
 142                                 #gpio-cells = <2>;
 143
 144                                 interrupt-controller;
 145                                 #interrupt-cells = <2>;
 146                         };
 147
 148                         pcfg_pull_up: pcfg_pull_up {
 149                                 bias-pull-up;
 150                         };
 151
 152                         pcfg_pull_down: pcfg_pull_down {
 153                                 bias-pull-down;
 154                         };
 155
 156                         pcfg_pull_none: pcfg_pull_none {
 157                                 bias-disable;
 158                         };
 159
 160                         uart0 {
 161                                 uart0_xfer: uart0-xfer {
 162                                         rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 163                                                         <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 164                                 };
 165
 166                                 uart0_cts: uart0-cts {
 167                                         rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 168                                 };
 169
 170                                 uart0_rts: uart0-rts {
 171                                         rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 172                                 };
 173                         };
 174
 175                         uart1 {
 176                                 uart1_xfer: uart1-xfer {
 177                                         rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 178                                                         <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 179                                 };
 180
 181                                 uart1_cts: uart1-cts {
 182                                         rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 183                                 };
 184
 185                                 uart1_rts: uart1-rts {
 186                                         rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 187                                 };
 188                         };
 189
 190                         uart2 {
 191                                 uart2_xfer: uart2-xfer {
 192                                         rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 193                                                         <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 194                                 };
 195                                 /* no rts / cts for uart2 */
 196                         };
 197
 198                         uart3 {
 199                                 uart3_xfer: uart3-xfer {
 200                                         rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 201                                                         <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 202                                 };
 203
 204                                 uart3_cts: uart3-cts {
 205                                         rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 206                                 };
 207
 208                                 uart3_rts: uart3-rts {
 209                                         rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 210                                 };
 211                         };
 212
 213                         sd0 {
 214                                 sd0_clk: sd0-clk {
 215                                         rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 216                                 };
 217
 218                                 sd0_cmd: sd0-cmd {
 219                                         rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 220                                 };
 221
 222                                 sd0_cd: sd0-cd {
 223                                         rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 224                                 };
 225
 226                                 sd0_wp: sd0-wp {
 227                                         rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 228                                 };
 229
 230                                 sd0_pwr: sd0-pwr {
 231                                         rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 232                                 };
 233
 234                                 sd0_bus1: sd0-bus-width1 {
 235                                         rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 236                                 };
 237
 238                                 sd0_bus4: sd0-bus-width4 {
 239                                         rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 240                                                         <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 241                                                         <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 242                                                         <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 243                                 };
 244                         };
 245
 246                         sd1 {
 247                                 sd1_clk: sd1-clk {
 248                                         rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 249                                 };
 250
 251                                 sd1_cmd: sd1-cmd {
 252                                         rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 253                                 };
 254
 255                                 sd1_cd: sd1-cd {
 256                                         rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 257                                 };
 258
 259                                 sd1_wp: sd1-wp {
 260                                         rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 261                                 };
 262
 263                                 sd1_bus1: sd1-bus-width1 {
 264                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 265                                 };
 266
 267                                 sd1_bus4: sd1-bus-width4 {
 268                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 269                                                         <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 270                                                         <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 271                                                         <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 272                                 };
 273                         };
 274                 };
 275         };
 276 };