arch/arm/boot/dts/rk3188.dtsi

   1
   2 #include "skeleton.dtsi"
   3 #include "rk3188-pinctrl.dtsi"
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5 #include "rk3188_io_vol_domain.dtsi"
   6
   7 #include <dt-bindings/sensor-dev.h>
   8
   9 / {
  10         compatible = "rockchip,rk3188";
  11         interrupt-parent = <&gic>;
  12         rockchip,sram = <&sram>;
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 serial1 = &uart1;
  17                 serial2 = &uart2;
  18                 serial3 = &uart3;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 lcdc0 = &lcdc0;
  25                 lcdc1 = &lcdc1;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a9";
  35                         reg = <0>;
  36                 };
  37                 cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a9";
  40                         reg = <1>;
  41                 };
  42                 cpu@2 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a9";
  45                         reg = <2>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         reg = <3>;
  51                 };
  52         };
  53
  54         twd-wdt@1013c620 {
  55                 compatible = "arm,cortex-a9-twd-wdt";
  56                 reg = <0x1013c620 0x20>;
  57                 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  58         };
  59
  60         gic: interrupt-controller@1013d000 {
  61                 compatible = "arm,cortex-a9-gic";
  62                 interrupt-controller;
  63                 #interrupt-cells = <3>;
  64                 reg = <0x1013d000 0x1000>,
  65                       <0x1013c100 0x0100>;
  66         };
  67
  68         L2: cache-controller@10138000 {
  69                 compatible = "rockchip,pl310-cache", "arm,pl310-cache";
  70                 reg = <0x10138000 0x1000>;
  71                 cache-unified;
  72                 cache-level = <2>;
  73                 arm,tag-latency = <1 1 1>;
  74                 arm,data-latency = <3 1 2>;
  75                 rockchip,prefetch-ctrl = <0x70000003>;
  76                 /* L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN */
  77                 rockchip,power-ctrl = <0x3>;
  78 /*
  79                 (0x1 << 0) |    // Full line of write zero behavior Enabled
  80                 (0x1 << 25) |   // Round-robin replacement
  81                 (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
  82                 (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
  83                 (0x1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)
  84 */
  85                 rockchip,aux-ctrl = <0x72000001 (~0x72000001)>;
  86         };
  87
  88         cpu_axi_bus: cpu_axi_bus@10128000 {
  89                 compatible = "rockchip,cpu_axi_bus";
  90                 reg = <0x10128000 0x8000>;
  91                 qos {
  92                         dmac {
  93                                 rockchip,offset = <0x1000>;
  94                                 rockchip,priority = <0 0>;
  95                         };
  96                         cpu0 {
  97                                 rockchip,offset = <0x2000>;
  98                                 rockchip,priority = <0 0>;
  99                         };
 100                         cpu1r {
 101                                 rockchip,offset = <0x2080>;
 102                                 rockchip,priority = <0 0>;
 103                         };
 104                         cpu1w {
 105                                 rockchip,offset = <0x2100>;
 106                                 rockchip,priority = <0 0>;
 107                         };
 108                         peri {
 109                                 rockchip,offset = <0x4000>;
 110                                 rockchip,priority = <2 2>;
 111                         };
 112                         gpu {
 113                                 rockchip,offset = <0x5000>;
 114                                 rockchip,priority = <2 1>;
 115                         };
 116                         vpu {
 117                                 rockchip,offset = <0x6000>;
 118                         };
 119                         vop0 {
 120                                 rockchip,offset = <0x7000>;
 121                                 rockchip,priority = <3 3>;
 122                         };
 123                         cif0 {
 124                                 rockchip,offset = <0x7080>;
 125                         };
 126                         ipp {
 127                                 rockchip,offset = <0x7100>;
 128                         };
 129                         vop1 {
 130                                 rockchip,offset = <0x7180>;
 131                                 rockchip,priority = <3 3>;
 132                         };
 133                         cif1 {
 134                                 rockchip,offset = <0x7200>;
 135                         };
 136                         rga {
 137                                 rockchip,offset = <0x7280>;
 138                         };
 139                 };
 140         };
 141
 142         bootrom@10120000 {
 143                 compatible = "rockchip,bootrom";
 144                 reg = <0x10120000 0x4000>;
 145         };
 146
 147         bootram@10080000 {
 148                 compatible = "rockchip,bootram";
 149                 reg = <0x10080000 0x20>; /* 32 bytes */
 150         };
 151
 152         sram: sram@10080020 {
 153                 compatible = "mmio-sram";
 154                 reg = <0x10080020 (0x8000 - 0x20)>; /* 32k - 32 */
 155                 map-exec;
 156         };
 157
 158         pmu@20004000 {
 159                 compatible = "rockchip,pmu";
 160                 reg = <0x20004000 0x4000>;
 161         };
 162
 163         timer@20038000 {
 164                 compatible = "rockchip,timer";
 165                 reg = <0x20038000 0x20>;
 166                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 167                 rockchip,percpu = <0>;
 168         };
 169
 170         timer@20038020 {
 171                 compatible = "rockchip,timer";
 172                 reg = <0x20038020 0x20>;
 173                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 174                 rockchip,percpu = <1>;
 175         };
 176
 177         timer@20038040 {
 178                 compatible = "rockchip,timer";
 179                 reg = <0x20038040 0x20>;
 180                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 181                 rockchip,percpu = <2>;
 182         };
 183
 184         timer@20038060 {
 185                 compatible = "rockchip,timer";
 186                 reg = <0x20038060 0x20>;
 187                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 188                 rockchip,percpu = <3>;
 189         };
 190
 191         timer@20038080 {
 192                 compatible = "rockchip,timer";
 193                 reg = <0x20038080 0x20>;
 194                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 195                 rockchip,broadcast = <1>;
 196         };
 197
 198         timer@200380a0 {
 199                 compatible = "rockchip,timer";
 200                 reg = <0x200380a0 0x20>;
 201                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 202                 rockchip,clocksource = <1>;
 203         };
 204
 205         watchdog:wdt@2004c000 {
 206                 compatible = "rockchip,watch dog";
 207                 reg = <0x2004c000 0x100>;
 208                 clocks = <&clk_gates7 15>;
 209                 clock-names = "pclk_wdt";
 210                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 211                 rockchip,irq = <1>;
 212                 rockchip,timeout = <5>;
 213                 rockchip,atboot = <1>;
 214                 rockchip,debug = <0>;
 215                 status = "disabled";
 216         };
 217
 218         amba {
 219                 #address-cells = <1>;
 220                 #size-cells = <1>;
 221                 compatible = "arm,amba-bus";
 222                 interrupt-parent = <&gic>;
 223                 ranges;
 224
 225                 pdma0: pdma@20018000 {
 226                         compatible = "arm,pl330", "arm,primecell";
 227                         reg = <0x20018000 0x4000>;
 228                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 230                         #dma-cells = <1>;
 231                 };
 232
 233                 pdma1: pdma@20078000 {
 234                         compatible = "arm,pl330", "arm,primecell";
 235                         reg = <0x20078000 0x4000>;
 236                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 238                         #dma-cells = <1>;
 239                 };
 240         };
 241
 242         uart0: serial@10124000 {
 243                 compatible = "rockchip,serial";
 244                 reg = <0x10124000 0x100>;
 245                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 246                 clock-frequency = <24000000>;
 247                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 248                 clock-names = "sclk_uart", "pclk_uart";
 249                 reg-shift = <2>;
 250                 reg-io-width = <4>;
 251                 dmas = <&pdma0 0>, <&pdma0 1>;
 252                 #dma-cells = <2>;
 253                 pinctrl-names = "default";
 254                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 255                 status = "disabled";
 256         };
 257
 258         uart1: serial@10126000 {
 259                 compatible = "rockchip,serial";
 260                 reg = <0x10126000 0x100>;
 261                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 262                 clock-frequency = <24000000>;
 263                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 264                 clock-names = "sclk_uart", "pclk_uart";
 265                 reg-shift = <2>;
 266                 reg-io-width = <4>;
 267                 dmas = <&pdma0 2>, <&pdma0 3>;
 268                 #dma-cells = <2>;
 269                 pinctrl-names = "default";
 270                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 271                 status = "disabled";
 272         };
 273
 274         uart2: serial@20064000 {
 275                 compatible = "rockchip,serial";
 276                 reg = <0x20064000 0x100>;
 277                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 278                 clock-frequency = <24000000>;
 279                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 280                 clock-names = "sclk_uart", "pclk_uart";
 281                 current-speed = <115200>;
 282                 reg-shift = <2>;
 283                 reg-io-width = <4>;
 284                 pinctrl-names = "default";
 285                 pinctrl-0 = <&uart2_xfer>;
 286                 status = "disabled";
 287         };
 288
 289         uart3: serial@20068000 {
 290                 compatible = "rockchip,serial";
 291                 reg = <0x20068000 0x100>;
 292                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 293                 clock-frequency = <24000000>;
 294                 clocks = <&clk_uart3>, <&clk_gates8 3>;
 295                 clock-names = "sclk_uart", "pclk_uart";
 296                 reg-shift = <2>;
 297                 reg-io-width = <4>;
 298                 dmas = <&pdma1 8>, <&pdma1 9>;
 299                 #dma-cells = <2>;
 300                 pinctrl-names = "default";
 301                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 302                 status = "disabled";
 303         };
 304
 305         fiq-debugger {
 306                 compatible = "rockchip,fiq-debugger";
 307                 rockchip,serial-id = <2>;
 308                 rockchip,signal-irq = <112>;
 309                 rockchip,wake-irq = <0>;
 310                 status = "disabled";
 311         };
 312
 313         i2c0: i2c@2002d000 {
 314                 compatible = "rockchip,rk30-i2c";
 315                 reg = <0x2002d000 0x1000>;
 316                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319                 pinctrl-names = "default", "gpio";
 320                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 321                 pinctrl-1 = <&i2c0_gpio>;
 322                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 323                 clocks = <&clk_gates8 4>;
 324                 rockchip,check-idle = <1>;
 325                 status = "disabled";
 326         };
 327
 328         i2c1: i2c@2002f000 {
 329                 compatible = "rockchip,rk30-i2c";
 330                 reg = <0x2002f000 0x1000>;
 331                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334                 pinctrl-names = "default", "gpio";
 335                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 336                 pinctrl-1 = <&i2c1_gpio>;
 337                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 338                 clocks = <&clk_gates8 5>;
 339                 rockchip,check-idle = <1>;
 340                 status = "disabled";
 341         };
 342
 343         i2c2: i2c@20056000 {
 344                 compatible = "rockchip,rk30-i2c";
 345                 reg = <0x20056000 0x1000>;
 346                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 pinctrl-names = "default", "gpio";
 350                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 351                 pinctrl-1 = <&i2c2_gpio>;
 352                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 353                 clocks = <&clk_gates8 6>;
 354                 rockchip,check-idle = <1>;
 355                 status = "disabled";
 356         };
 357
 358         i2c3: i2c@2005a000 {
 359                 compatible = "rockchip,rk30-i2c";
 360                 reg = <0x2005a000 0x1000>;
 361                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 pinctrl-names = "default", "gpio";
 365                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 366                 pinctrl-1 = <&i2c3_gpio>;
 367                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 368                 clocks = <&clk_gates8 7>;
 369                 rockchip,check-idle = <1>;
 370                 status = "disabled";
 371         };
 372
 373         i2c4: i2c@2005e000 {
 374                 compatible = "rockchip,rk30-i2c";
 375                 reg = <0x2005e000 0x1000>;
 376                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 pinctrl-names = "default", "gpio";
 380                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 381                 pinctrl-1 = <&i2c4_gpio>;
 382                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 383                 clocks = <&clk_gates8 8>;
 384                 rockchip,check-idle = <1>;
 385                 status = "disabled";
 386         };
 387
 388         clocks-init{
 389                 compatible = "rockchip,clocks-init";
 390                 rockchip,clocks-init-parent =
 391                         <&clk_core &clk_apll>,  <&aclk_cpu_mux &clk_gpll>,/*FIXME*/
 392                         <&aclk_peri_mux &clk_gpll>,     <&clk_i2s_pll_mux &clk_cpll>,
 393                         <&clk_uart_pll_mux &clk_gpll>;
 394                 rockchip,clocks-init-rate =
 395                         <&clk_core 792000000>,  <&clk_gpll 768000000>,
 396                         <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
 397                         <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
 398                         <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
 399                         <&hclk_peri 96000000>,  <&pclk_peri 48000000>,
 400                         <&clk_gpu 200000000>, <&aclk_lcdc0 300000000>,
 401                         <&aclk_lcdc1 300000000>;
 402         };
 403
 404         fb: fb{
 405                 compatible = "rockchip,rk-fb";
 406                 rockchip,disp-mode = <DUAL>;
 407         };
 408
 409         nandc: nandc {
 410                 compatible = "rockchip,rk-nandc";
 411                 reg = <0x10050000 0x4000>;
 412                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 413         };
 414
 415         lcdc0:lcdc@1010c000 {
 416                 compatible = "rockchip,rk3188-lcdc";
 417                 rockchip,prop = <PRMRY>;
 418                 rochchip,pwr18 = <0>;
 419                 reg = <0x1010c000 0x1000>;
 420                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 421                 status = "disabled";
 422         };
 423
 424         lcdc1:lcdc@1010e000 {
 425                 compatible = "rockchip,rk3188-lcdc";
 426                 rockchip,prop = <EXTEND>;
 427                 rockchip,pwr18 = <0>;
 428                 reg = <0x1010e000 0x1000>;
 429                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 430                 pinctrl-names = "default", "gpio";
 431                 pinctrl-0 = <&lcdc1_lcdc>;
 432                 pinctrl-1 = <&lcdc1_gpio>;
 433                 status = "disabled";
 434   };
 435   rga@10114000 {
 436                 compatible = "rockchip,rga";
 437                 reg = <0x10114000 0x1000>;
 438                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 439                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 440     clock-names = "hclk_rga", "aclk_rga";
 441   };
 442
 443     adc: adc@2006c000 {
 444            compatible = "rockchip,saradc";
 445            reg = <0x2006c000 0x100>;
 446            interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 447            #io-channel-cells = <1>;
 448            io-channel-ranges;
 449            rockchip,adc-vref = <1800>;
 450            clock-frequency = <1000000>;
 451            clocks = <&clk_saradc>, <&clk_gates7 14>;
 452            clock-names = "saradc", "pclk_saradc";
 453            status = "disabled";
 454     };
 455
 456         spdif: rockchip-spdif@0x1011e000 {
 457                 compatible = "rockchip-spdif";
 458                 reg = <0x1011e000 0x2000>;
 459                 clocks = <&clk_spdif>;
 460                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 461                 dmas = <&pdma0 8>;
 462                 #dma-cells = <1>;
 463                 dma-names = "tx";
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&spdif_tx>;
 466         };
 467
 468         i2s0: rockchip-i2s@0x1011a000 {
 469                 compatible = "rockchip-i2s";
 470                 reg = <0x1011a000 0x2000>;
 471                 i2s-id = <0>;
 472                 clocks = <&clk_i2s>;
 473                 clock-names = "i2s_clk";
 474                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 475                 dmas = <&pdma0 6>,
 476                         <&pdma0 7>;
 477                 #dma-cells = <2>;
 478                 dma-names = "tx", "rx";
 479                 pinctrl-names = "default", "sleep";
 480                 pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 481                 pinctrl-1 = <&i2s0_gpio>;
 482         };
 483
 484         pwm0: pwm@20030000{
 485                 compatible = "rockchip,pwm";
 486                 reg = <0x20030000 0x10>;
 487                 #pwm-cells = <2>;
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&pwm0_pin>;
 490                 status = "disabled";
 491
 492         };
 493
 494         pwm1: pwm@20030010{
 495                 compatible = "rockchip,pwm";
 496                 reg = <0x20030010 0x10>; /*0x20030000*/
 497                 #pwm-cells = <2>;
 498                 pinctrl-names = "default";
 499                 pinctrl-0 = <&pwm1_pin>;
 500                 status = "disabled";
 501
 502         };
 503         pwm2: pwm@20050020{
 504                 compatible = "rockchip,pwm";
 505                 reg = <0x20050020 0x10>; /*0x20030000*/
 506                 #pwm-cells = <2>;
 507                 pinctrl-names = "default";
 508                 pinctrl-0 = <&pwm2_pin>;
 509                 status = "disabled";
 510
 511         };
 512
 513         pwm3: pwm@20050030{
 514                 compatible = "rockchip,pwm";
 515                 reg = <0x20050030 0x10>; /*0x20030000*/
 516                 #pwm-cells = <2>;
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&pwm3_pin>;
 519                 status = "disabled";
 520
 521         };
 522         dvfs {
 523                 vd_cpu:
 524                 vd_cpu {
 525                         regulator_name="vdd_arm";
 526                         suspend_volt=<1000>; //mV
 527                         pd_a9 {
 528                                 clk_core_dvfs_table:
 529                                 clk_core {
 530                                         operating-points = <
 531                                                 /* KHz    uV */
 532                                                 312000 900000
 533                                                 504000 950000
 534                                                 816000 1000000
 535                                                 1008000 1100000
 536                                                 1200000 1200000
 537                                                 1416000 1300000
 538                                                 1608000 1350000
 539                                                 >;
 540                                 };
 541                         };
 542                 };
 543
 544                 vd_core:
 545                 vd_core {
 546                         regulator_name="vdd_logic";
 547                         suspend_volt=<1000>; //mV
 548
 549                         pd_gpu {
 550                                 clk_gpu_dvfs_table:
 551                                 clk_gpu {
 552                                         operating-points = <
 553                                                 /* KHz    uV */
 554                                                 200000 1200000
 555                                                 300000 1200000
 556                                                 400000 1200000
 557                                                 >;
 558                                 };
 559                         };
 560
 561                         pd_ddr {
 562                                 clk_ddr_dvfs_table:
 563                                 clk_ddr {
 564                                         operating-points = <
 565                                                 /* KHz    uV */
 566                                                 200000 1200000
 567                                                 300000 1200000
 568                                                 400000 1200000
 569                                                 >;
 570                                 };
 571                         };
 572                 };
 573         };
 574         ion: ion{
 575                 compatible = "rockchip,ion";
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 rockchip,ion-heap@1 { /* CMA HEAP */
 579                         reg = <1>;
 580                 };
 581                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 582                         reg = <3>;
 583                 };
 584         };
 585
 586         dwc_control_usb: dwc-control-usb@0x200080ac {
 587                 compatible = "rockchip,rk3188-dwc-control-usb";
 588                 reg = <0x200080ac 0x4>,
 589                       <0x2000810c 0x10>,
 590                       <0x2000811c 0x10>,
 591                       <0x2000812c 0x8>,
 592                       <0x20008138 0x8>;
 593                 reg-names = "GRF_SOC_STATUS0",
 594                             "GRF_UOC0_BASE",
 595                             "GRF_UOC1_BASE",
 596                             "GRF_UOC2_BASE",
 597                             "GRF_UOC3_BASE";
 598                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 599                 interrupt-names = "bvalid";
 600                 gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 601                 clocks = <&clk_gates4 5>;
 602                 clock-names = "hclk_usb_peri";
 603         };
 604
 605         usb@10180000 {
 606                 compatible = "rockchip,usb20_otg";
 607                 reg = <0x10180000 0x40000>;
 608                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 609                 clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;
 610                 clock-names = "otgphy0", "hclk_otg0";
 611         };
 612
 613         usb@101c0000 {
 614                 compatible = "rockchip,usb20_host";
 615                 reg = <0x101c0000 0x40000>;
 616                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 617                 clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;
 618                 clock-names = "otgphy1", "hclk_otg1";
 619         };
 620
 621         hsic@10240000 {
 622                 compatible = "rockchip,rk_hsic_host";
 623                 reg = <0x10240000 0x40000>;
 624                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 625                 clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,
 626                          <&clk_hsicphy12m>, <&clk_otgphy1_480m>;
 627                 clock-names = "hsicphy480m", "hclk_hsic",
 628                               "hsicphy12m", "hsic_otgphy1";
 629         };
 630
 631 };