arch/arm/boot/dts/rk3188.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/pinctrl/rockchip.h>
  18 #include <dt-bindings/clock/rk3188-cru.h>
  19 #include "rk3xxx.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3188";
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 enable-method = "rockchip,rk3066-smp";
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         next-level-cache = <&L2>;
  33                         reg = <0x0>;
  34                 };
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         next-level-cache = <&L2>;
  39                         reg = <0x1>;
  40                 };
  41                 cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         next-level-cache = <&L2>;
  45                         reg = <0x2>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         next-level-cache = <&L2>;
  51                         reg = <0x3>;
  52                 };
  53         };
  54
  55         global-timer@1013c200 {
  56                 interrupts = <GIC_PPI 11 0xf04>;
  57         };
  58
  59         local-timer@1013c600 {
  60                 interrupts = <GIC_PPI 13 0xf04>;
  61         };
  62
  63         sram: sram@10080000 {
  64                 compatible = "mmio-sram";
  65                 reg = <0x10080000 0x8000>;
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68                 ranges = <0 0x10080000 0x8000>;
  69
  70                 smp-sram@0 {
  71                         compatible = "rockchip,rk3066-smp-sram";
  72                         reg = <0x0 0x50>;
  73                 };
  74         };
  75
  76         cru: clock-controller@20000000 {
  77                 compatible = "rockchip,rk3188-cru";
  78                 reg = <0x20000000 0x1000>;
  79                 rockchip,grf = <&grf>;
  80
  81                 #clock-cells = <1>;
  82                 #reset-cells = <1>;
  83         };
  84
  85         pinctrl: pinctrl@20008000 {
  86                 compatible = "rockchip,rk3188-pinctrl";
  87                 rockchip,grf = <&grf>;
  88                 rockchip,pmu = <&pmu>;
  89
  90                 #address-cells = <1>;
  91                 #size-cells = <1>;
  92                 ranges;
  93
  94                 gpio0: gpio0@0x2000a000 {
  95                         compatible = "rockchip,rk3188-gpio-bank0";
  96                         reg = <0x2000a000 0x100>;
  97                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  98                         clocks = <&cru PCLK_GPIO0>;
  99
 100                         gpio-controller;
 101                         #gpio-cells = <2>;
 102
 103                         interrupt-controller;
 104                         #interrupt-cells = <2>;
 105                 };
 106
 107                 gpio1: gpio1@0x2003c000 {
 108                         compatible = "rockchip,gpio-bank";
 109                         reg = <0x2003c000 0x100>;
 110                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 111                         clocks = <&cru PCLK_GPIO1>;
 112
 113                         gpio-controller;
 114                         #gpio-cells = <2>;
 115
 116                         interrupt-controller;
 117                         #interrupt-cells = <2>;
 118                 };
 119
 120                 gpio2: gpio2@2003e000 {
 121                         compatible = "rockchip,gpio-bank";
 122                         reg = <0x2003e000 0x100>;
 123                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 124                         clocks = <&cru PCLK_GPIO2>;
 125
 126                         gpio-controller;
 127                         #gpio-cells = <2>;
 128
 129                         interrupt-controller;
 130                         #interrupt-cells = <2>;
 131                 };
 132
 133                 gpio3: gpio3@20080000 {
 134                         compatible = "rockchip,gpio-bank";
 135                         reg = <0x20080000 0x100>;
 136                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 137                         clocks = <&cru PCLK_GPIO3>;
 138
 139                         gpio-controller;
 140                         #gpio-cells = <2>;
 141
 142                         interrupt-controller;
 143                         #interrupt-cells = <2>;
 144                 };
 145
 146                 pcfg_pull_up: pcfg_pull_up {
 147                         bias-pull-up;
 148                 };
 149
 150                 pcfg_pull_down: pcfg_pull_down {
 151                         bias-pull-down;
 152                 };
 153
 154                 pcfg_pull_none: pcfg_pull_none {
 155                         bias-disable;
 156                 };
 157
 158                 uart0 {
 159                         uart0_xfer: uart0-xfer {
 160                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 161                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 162                         };
 163
 164                         uart0_cts: uart0-cts {
 165                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 166                         };
 167
 168                         uart0_rts: uart0-rts {
 169                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 170                         };
 171                 };
 172
 173                 uart1 {
 174                         uart1_xfer: uart1-xfer {
 175                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 176                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 177                         };
 178
 179                         uart1_cts: uart1-cts {
 180                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 181                         };
 182
 183                         uart1_rts: uart1-rts {
 184                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 185                         };
 186                 };
 187
 188                 uart2 {
 189                         uart2_xfer: uart2-xfer {
 190                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 191                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 192                         };
 193                         /* no rts / cts for uart2 */
 194                 };
 195
 196                 uart3 {
 197                         uart3_xfer: uart3-xfer {
 198                                 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 199                                                 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 200                         };
 201
 202                         uart3_cts: uart3-cts {
 203                                 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 204                         };
 205
 206                         uart3_rts: uart3-rts {
 207                                 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 208                         };
 209                 };
 210
 211                 sd0 {
 212                         sd0_clk: sd0-clk {
 213                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 214                         };
 215
 216                         sd0_cmd: sd0-cmd {
 217                                 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 218                         };
 219
 220                         sd0_cd: sd0-cd {
 221                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 222                         };
 223
 224                         sd0_wp: sd0-wp {
 225                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 226                         };
 227
 228                         sd0_pwr: sd0-pwr {
 229                                 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 230                         };
 231
 232                         sd0_bus1: sd0-bus-width1 {
 233                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 234                         };
 235
 236                         sd0_bus4: sd0-bus-width4 {
 237                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 238                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 239                                                 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 240                                                 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 241                         };
 242                 };
 243
 244                 sd1 {
 245                         sd1_clk: sd1-clk {
 246                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 247                         };
 248
 249                         sd1_cmd: sd1-cmd {
 250                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 251                         };
 252
 253                         sd1_cd: sd1-cd {
 254                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 255                         };
 256
 257                         sd1_wp: sd1-wp {
 258                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 259                         };
 260
 261                         sd1_bus1: sd1-bus-width1 {
 262                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 263                         };
 264
 265                         sd1_bus4: sd1-bus-width4 {
 266                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 267                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 268                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 269                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 270                         };
 271                 };
 272         };
 273 };