arch/arm/boot/dts/rk3188.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/pinctrl/rockchip.h>
  18 #include <dt-bindings/clock/rk3188-cru.h>
  19 #include "rk3xxx.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3188";
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 enable-method = "rockchip,rk3066-smp";
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         next-level-cache = <&L2>;
  33                         reg = <0x0>;
  34                 };
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         next-level-cache = <&L2>;
  39                         reg = <0x1>;
  40                 };
  41                 cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         next-level-cache = <&L2>;
  45                         reg = <0x2>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a9";
  50                         next-level-cache = <&L2>;
  51                         reg = <0x3>;
  52                 };
  53         };
  54
  55         soc {
  56                 global-timer@1013c200 {
  57                         interrupts = <GIC_PPI 11 0xf04>;
  58                 };
  59
  60                 local-timer@1013c600 {
  61                         interrupts = <GIC_PPI 13 0xf04>;
  62                 };
  63
  64                 sram: sram@10080000 {
  65                         compatible = "mmio-sram";
  66                         reg = <0x10080000 0x8000>;
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69                         ranges = <0 0x10080000 0x8000>;
  70
  71                         smp-sram@0 {
  72                                 compatible = "rockchip,rk3066-smp-sram";
  73                                 reg = <0x0 0x50>;
  74                         };
  75                 };
  76
  77                 cru: clock-controller@20000000 {
  78                         compatible = "rockchip,rk3188-cru";
  79                         reg = <0x20000000 0x1000>;
  80                         rockchip,grf = <&grf>;
  81
  82                         #clock-cells = <1>;
  83                         #reset-cells = <1>;
  84                 };
  85
  86                 pinctrl@20008000 {
  87                         compatible = "rockchip,rk3188-pinctrl";
  88                         rockchip,grf = <&grf>;
  89                         rockchip,pmu = <&pmu>;
  90
  91                         #address-cells = <1>;
  92                         #size-cells = <1>;
  93                         ranges;
  94
  95                         gpio0: gpio0@0x2000a000 {
  96                                 compatible = "rockchip,rk3188-gpio-bank0";
  97                                 reg = <0x2000a000 0x100>;
  98                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  99                                 clocks = <&cru PCLK_GPIO0>;
 100
 101                                 gpio-controller;
 102                                 #gpio-cells = <2>;
 103
 104                                 interrupt-controller;
 105                                 #interrupt-cells = <2>;
 106                         };
 107
 108                         gpio1: gpio1@0x2003c000 {
 109                                 compatible = "rockchip,gpio-bank";
 110                                 reg = <0x2003c000 0x100>;
 111                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 112                                 clocks = <&cru PCLK_GPIO1>;
 113
 114                                 gpio-controller;
 115                                 #gpio-cells = <2>;
 116
 117                                 interrupt-controller;
 118                                 #interrupt-cells = <2>;
 119                         };
 120
 121                         gpio2: gpio2@2003e000 {
 122                                 compatible = "rockchip,gpio-bank";
 123                                 reg = <0x2003e000 0x100>;
 124                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 125                                 clocks = <&cru PCLK_GPIO2>;
 126
 127                                 gpio-controller;
 128                                 #gpio-cells = <2>;
 129
 130                                 interrupt-controller;
 131                                 #interrupt-cells = <2>;
 132                         };
 133
 134                         gpio3: gpio3@20080000 {
 135                                 compatible = "rockchip,gpio-bank";
 136                                 reg = <0x20080000 0x100>;
 137                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 138                                 clocks = <&cru PCLK_GPIO3>;
 139
 140                                 gpio-controller;
 141                                 #gpio-cells = <2>;
 142
 143                                 interrupt-controller;
 144                                 #interrupt-cells = <2>;
 145                         };
 146
 147                         pcfg_pull_up: pcfg_pull_up {
 148                                 bias-pull-up;
 149                         };
 150
 151                         pcfg_pull_down: pcfg_pull_down {
 152                                 bias-pull-down;
 153                         };
 154
 155                         pcfg_pull_none: pcfg_pull_none {
 156                                 bias-disable;
 157                         };
 158
 159                         uart0 {
 160                                 uart0_xfer: uart0-xfer {
 161                                         rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
 162                                                         <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
 163                                 };
 164
 165                                 uart0_cts: uart0-cts {
 166                                         rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
 167                                 };
 168
 169                                 uart0_rts: uart0-rts {
 170                                         rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
 171                                 };
 172                         };
 173
 174                         uart1 {
 175                                 uart1_xfer: uart1-xfer {
 176                                         rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
 177                                                         <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
 178                                 };
 179
 180                                 uart1_cts: uart1-cts {
 181                                         rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
 182                                 };
 183
 184                                 uart1_rts: uart1-rts {
 185                                         rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
 186                                 };
 187                         };
 188
 189                         uart2 {
 190                                 uart2_xfer: uart2-xfer {
 191                                         rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
 192                                                         <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
 193                                 };
 194                                 /* no rts / cts for uart2 */
 195                         };
 196
 197                         uart3 {
 198                                 uart3_xfer: uart3-xfer {
 199                                         rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
 200                                                         <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
 201                                 };
 202
 203                                 uart3_cts: uart3-cts {
 204                                         rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
 205                                 };
 206
 207                                 uart3_rts: uart3-rts {
 208                                         rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
 209                                 };
 210                         };
 211
 212                         sd0 {
 213                                 sd0_clk: sd0-clk {
 214                                         rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
 215                                 };
 216
 217                                 sd0_cmd: sd0-cmd {
 218                                         rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
 219                                 };
 220
 221                                 sd0_cd: sd0-cd {
 222                                         rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
 223                                 };
 224
 225                                 sd0_wp: sd0-wp {
 226                                         rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
 227                                 };
 228
 229                                 sd0_pwr: sd0-pwr {
 230                                         rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 231                                 };
 232
 233                                 sd0_bus1: sd0-bus-width1 {
 234                                         rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
 235                                 };
 236
 237                                 sd0_bus4: sd0-bus-width4 {
 238                                         rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 239                                                         <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
 240                                                         <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
 241                                                         <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
 242                                 };
 243                         };
 244
 245                         sd1 {
 246                                 sd1_clk: sd1-clk {
 247                                         rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
 248                                 };
 249
 250                                 sd1_cmd: sd1-cmd {
 251                                         rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
 252                                 };
 253
 254                                 sd1_cd: sd1-cd {
 255                                         rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
 256                                 };
 257
 258                                 sd1_wp: sd1-wp {
 259                                         rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
 260                                 };
 261
 262                                 sd1_bus1: sd1-bus-width1 {
 263                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
 264                                 };
 265
 266                                 sd1_bus4: sd1-bus-width4 {
 267                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
 268                                                         <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
 269                                                         <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
 270                                                         <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
 271                                 };
 272                         };
 273                 };
 274         };
 275 };