2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/rockchip.h>
18 #include <dt-bindings/clock/rk3188-cru.h>
19 #include "rk3xxx.dtsi"
22 compatible = "rockchip,rk3188";
27 enable-method = "rockchip,rk3066-smp";
31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
43 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
55 global-timer@1013c200 {
56 interrupts = <GIC_PPI 11 0xf04>;
59 local-timer@1013c600 {
60 interrupts = <GIC_PPI 13 0xf04>;
64 compatible = "mmio-sram";
65 reg = <0x10080000 0x8000>;
68 ranges = <0 0x10080000 0x8000>;
71 compatible = "rockchip,rk3066-smp-sram";
76 cru: clock-controller@20000000 {
77 compatible = "rockchip,rk3188-cru";
78 reg = <0x20000000 0x1000>;
79 rockchip,grf = <&grf>;
86 compatible = "rockchip,rk3188-pinctrl";
87 rockchip,grf = <&grf>;
88 rockchip,pmu = <&pmu>;
94 gpio0: gpio0@0x2000a000 {
95 compatible = "rockchip,rk3188-gpio-bank0";
96 reg = <0x2000a000 0x100>;
97 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
98 clocks = <&cru PCLK_GPIO0>;
103 interrupt-controller;
104 #interrupt-cells = <2>;
107 gpio1: gpio1@0x2003c000 {
108 compatible = "rockchip,gpio-bank";
109 reg = <0x2003c000 0x100>;
110 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
111 clocks = <&cru PCLK_GPIO1>;
116 interrupt-controller;
117 #interrupt-cells = <2>;
120 gpio2: gpio2@2003e000 {
121 compatible = "rockchip,gpio-bank";
122 reg = <0x2003e000 0x100>;
123 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&cru PCLK_GPIO2>;
129 interrupt-controller;
130 #interrupt-cells = <2>;
133 gpio3: gpio3@20080000 {
134 compatible = "rockchip,gpio-bank";
135 reg = <0x20080000 0x100>;
136 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&cru PCLK_GPIO3>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
146 pcfg_pull_up: pcfg_pull_up {
150 pcfg_pull_down: pcfg_pull_down {
154 pcfg_pull_none: pcfg_pull_none {
159 uart0_xfer: uart0-xfer {
160 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
161 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
164 uart0_cts: uart0-cts {
165 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
168 uart0_rts: uart0-rts {
169 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
174 uart1_xfer: uart1-xfer {
175 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
176 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
179 uart1_cts: uart1-cts {
180 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
183 uart1_rts: uart1-rts {
184 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
189 uart2_xfer: uart2-xfer {
190 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
191 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
193 /* no rts / cts for uart2 */
197 uart3_xfer: uart3-xfer {
198 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
199 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
202 uart3_cts: uart3-cts {
203 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
206 uart3_rts: uart3-rts {
207 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
213 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
217 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
221 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
225 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
229 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
232 sd0_bus1: sd0-bus-width1 {
233 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
236 sd0_bus4: sd0-bus-width4 {
237 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
238 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
239 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
240 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
246 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
250 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
254 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
258 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
261 sd1_bus1: sd1-bus-width1 {
262 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
265 sd1_bus4: sd1-bus-width4 {
266 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
267 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
268 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
269 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;