2 * Copyright (C) 2013 ROCKCHIP, Inc.
3 * Author: chenxing <chenxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <dt-bindings/clock/rockchip,rk3188.h>
19 compatible = "rockchip,rk-clocks";
22 ranges = <0x0 0x20000000 0x0100>;
25 compatible = "rockchip,rk-fixed-rate-cons";
28 compatible = "fixed-clock";
30 clock-output-names = "xin24m";
31 clock-frequency = <24000000>;
35 compatible = "fixed-clock";
38 clock-output-names = "xin12m";
39 clock-frequency = <12000000>;
43 compatible = "fixed-clock";
45 clock-output-names = "dummy";
46 clock-frequency = <0>;
50 rmii_clkin: rmii_clkin {
51 compatible = "fixed-clock";
53 clock-output-names = "rmii_clkin";
54 clock-frequency = <0>;
57 clk_hsadc_ext: clk_hsadc_ext {
58 compatible = "fixed-clock";
60 clock-output-names = "clk_hsadc_ext";
61 clock-frequency = <0>;
64 clk_cif_in: clk_cif_in {
65 compatible = "fixed-clock";
67 clock-output-names = "clk_cif_in";
68 clock-frequency = <0>;
74 compatible = "rockchip,rk-fixed-factor-cons";
76 otgphy0_480m: otgphy0_480m {
77 compatible = "fixed-factor-clock";
78 clocks = <&clk_gates1 5>;
79 clock-output-names = "otgphy0_480m";
85 otgphy1_480m: otgphy1_480m {
86 compatible = "fixed-factor-clock";
87 clocks = <&clk_gates1 6>;
88 clock-output-names = "otgphy1_480m";
97 compatible = "rockchip,rk-clock-regs";
103 /* PLL control regs */
105 compatible = "rockchip,rk-pll-cons";
106 #address-cells = <1>;
110 clk_apll: pll-clk@0000 {
111 compatible = "rockchip,rk3188-pll-clk";
113 mode-reg = <0x0040 0>;
114 status-reg = <0x00ac 6>;
116 clock-output-names = "clk_apll";
117 rockchip,pll-type = <CLK_PLL_3188_APLL>;
121 clk_dpll: pll-clk@0010 {
122 compatible = "rockchip,rk3188-pll-clk";
124 mode-reg = <0x0040 4>;
125 status-reg = <0x00ac 5>;
127 clock-output-names = "clk_dpll";
128 rockchip,pll-type = <CLK_PLL_3188>;
132 clk_cpll: pll-clk@0020 {
133 compatible = "rockchip,rk3188-pll-clk";
135 mode-reg = <0x0040 8>;
136 status-reg = <0x00ac 7>;
138 clock-output-names = "clk_cpll";
139 rockchip,pll-type = <CLK_PLL_3188>;
141 #clock-init-cells = <1>;
144 clk_gpll: pll-clk@0030 {
145 compatible = "rockchip,rk3188-pll-clk";
147 mode-reg = <0x0040 12>;
148 status-reg = <0x00ac 8>;
150 clock-output-names = "clk_gpll";
151 rockchip,pll-type = <CLK_PLL_3188>;
153 #clock-init-cells = <1>;
157 /* Select control regs */
159 compatible = "rockchip,rk-sel-cons";
160 #address-cells = <1>;
164 clk_sel_con0: sel-con@0044 {
165 compatible = "rockchip,rk3188-selcon";
167 #address-cells = <1>;
170 aclk_cpu_div: aclk_cpu_div {
171 compatible = "rockchip,rk3188-div-con";
172 rockchip,bits = <0 5>;
173 clocks = <&aclk_cpu>;
174 clock-output-names = "aclk_cpu";
176 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
177 rockchip,clkops-idx =
178 <CLKOPS_RATE_MUX_DIV>;
179 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
182 aclk_cpu: aclk_cpu_mux {
183 compatible = "rockchip,rk3188-mux-con";
184 rockchip,bits = <5 1>;
185 clocks = <&clk_apll>, <&clk_gpll>;
186 clock-output-names = "aclk_cpu";
188 #clock-init-cells = <1>;
191 clk_core_peri: clk_core_peri_div {
192 compatible = "rockchip,rk3188-div-con";
193 rockchip,bits = <6 2>;
194 clocks = <&clk_core>;
195 clock-output-names = "clk_core_peri";
196 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
197 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
199 rockchip,div-relations = <0x0 2
205 clk_core: clk_core_mux {
206 compatible = "rockchip,rk3188-mux-con";
207 rockchip,bits = <8 1>;
208 clocks = <&clk_apll>,
210 clock-output-names = "clk_core";
211 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
212 CLK_SET_RATE_NO_REPARENT)>;
214 #clock-init-cells = <1>;
217 clk_core_div: clk_core_div {
218 compatible = "rockchip,rk3188-div-con";
219 rockchip,bits = <9 5>;
220 clocks = <&clk_core>;
221 clock-output-names = "clk_core";
222 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
223 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
227 /* reg[15:14]: reserved */
231 clk_sel_con1: sel-con@0048 {
232 compatible = "rockchip,rk3188-selcon";
234 #address-cells = <1>;
237 /* reg[2:0]: reserved */
239 aclk_core: aclk_core_div {
240 compatible = "rockchip,rk3188-div-con";
241 rockchip,bits = <3 3>;
242 clocks = <&clk_core>;
243 clock-output-names = "aclk_core";
245 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
246 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
247 rockchip,div-relations = <0x0 1
254 /* reg[7:6]: reserved */
256 hclk_cpu: hclk_cpu_div {
257 compatible = "rockchip,rk3188-div-con";
258 rockchip,bits = <8 2>;
259 clocks = <&aclk_cpu>;
260 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
261 clock-output-names = "hclk_cpu";
263 #clock-init-cells = <1>;
266 /* reg[11:10]: reserved */
268 pclk_cpu: pclk_cpu_div {
269 compatible = "rockchip,rk3188-div-con";
270 rockchip,bits = <12 2>;
271 clocks = <&aclk_cpu>;
272 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
273 clock-output-names = "pclk_cpu";
275 #clock-init-cells = <1>;
278 pclk_ahb2apb: pclk_ahb2apb_div {
279 compatible = "rockchip,rk3188-div-con";
280 rockchip,bits = <14 2>;
281 clocks = <&hclk_cpu>;
282 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
283 clock-output-names = "pclk_ahb2apb";
285 #clock-init-cells = <1>;
289 clk_sel_con2: sel-con@004c {
290 compatible = "rockchip,rk3188-selcon";
292 #address-cells = <1>;
295 /* reg[14:0]: reserved */
297 clk_i2s_pll_mux: clk_i2s_pll_mux {
298 compatible = "rockchip,rk3188-mux-con";
299 rockchip,bits = <15 1>;
300 clocks = <&clk_gpll>, <&clk_cpll>;
301 clock-output-names = "clk_i2s_pll";
303 #clock-init-cells = <1>;
307 clk_sel_con3: sel-con@0050 {
308 compatible = "rockchip,rk3188-selcon";
310 #address-cells = <1>;
313 clk_i2s_div: clk_i2s_div {
314 compatible = "rockchip,rk3188-div-con";
315 rockchip,bits = <0 7>;
316 clocks = <&clk_i2s_pll_mux>;
317 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
318 clock-output-names = "clk_i2s_div";
322 /* reg[7]: reserved */
324 clk_i2s: clk_i2s_mux {
325 compatible = "rockchip,rk3188-mux-con";
326 rockchip,bits = <8 2>;
327 clocks = <&clk_i2s_div>, <&clk_i2s_frac>, <&xin12m>;
328 clock-output-names = "clk_i2s";
329 rockchip,clkops-idx = <CLKOPS_RATE_I2S>;
330 rockchip,flags = <CLK_SET_RATE_PARENT>;
334 /* reg[15:10]: reserved */
337 /* clk_sel_con4: reserved */
339 clk_sel_con5: sel-con@0058 {
340 compatible = "rockchip,rk3188-selcon";
342 #address-cells = <1>;
345 clk_spdif_div: clk_spdif_div {
346 compatible = "rockchip,rk3188-div-con";
347 rockchip,bits = <0 7>;
348 clocks = <&clk_i2s_pll_mux>;
349 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
350 clock-output-names = "clk_spdif_div";
351 /* spdif same as i2s */
355 /* reg[7]: reserved */
357 clk_spdif: clk_spdif_mux {
358 compatible = "rockchip,rk3188-mux-con";
359 rockchip,bits = <8 2>;
360 clocks = <&clk_spdif_div>, <&clk_spdif_frac>, <&xin12m>;
361 clock-output-names = "clk_spdif";
362 rockchip,clkops-idx = <CLKOPS_RATE_I2S>;
363 rockchip,flags = <CLK_SET_RATE_PARENT>;
367 /* reg[15:10]: reserved */
370 /* clk_sel_con6: reserved */
372 clk_sel_con7: sel-con@0060 {
373 compatible = "rockchip,rk3188-selcon";
375 #address-cells = <1>;
377 clk_i2s_frac: clk_i2s_frac {
378 compatible = "rockchip,rk3188-frac-con";
379 clocks = <&clk_i2s_div>;
380 clock-output-names = "clk_i2s_frac";
381 /* numerator denominator */
382 rockchip,bits = <0 32>;
384 rockchip,clkops-idx =
385 <CLKOPS_RATE_I2S_FRAC>;
389 /* clk_sel_con8: reserved */
391 clk_sel_con9: sel-con@0068 {
392 compatible = "rockchip,rk3188-selcon";
394 #address-cells = <1>;
396 clk_spdif_frac: clk_spdif_frac {
397 compatible = "rockchip,rk3188-frac-con";
398 clocks = <&clk_spdif_div>;
399 clock-output-names = "clk_spdif_frac";
400 /* numerator denominator */
401 rockchip,bits = <0 32>;
403 rockchip,clkops-idx =
404 <CLKOPS_RATE_I2S_FRAC>;
408 clk_sel_con10: sel-con@006c {
409 compatible = "rockchip,rk3188-selcon";
411 #address-cells = <1>;
414 aclk_peri_div: aclk_peri_div {
415 compatible = "rockchip,rk3188-div-con";
416 rockchip,bits = <0 5>;
417 clocks = <&aclk_peri>;
418 clock-output-names = "aclk_peri";
419 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
421 #clock-init-cells = <1>;
422 rockchip,clkops-idx =
423 <CLKOPS_RATE_MUX_DIV>;
424 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
427 /* reg[7:5]: reserved */
429 hclk_peri: hclk_peri_div {
430 compatible = "rockchip,rk3188-div-con";
431 rockchip,bits = <8 2>;
432 clocks = <&aclk_peri>;
433 clock-output-names = "hclk_peri";
434 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
436 #clock-init-cells = <1>;
439 /* reg[11:10]: reserved */
441 pclk_peri: pclk_peri_div {
442 compatible = "rockchip,rk3188-div-con";
443 rockchip,bits = <12 2>;
444 clocks = <&aclk_peri>;
445 clock-output-names = "pclk_peri";
446 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
448 #clock-init-cells = <1>;
451 /* reg[14]: reserved */
453 aclk_peri: aclk_peri_mux {
454 compatible = "rockchip,rk3188-mux-con";
455 rockchip,bits = <15 1>;
456 clocks = <&clk_cpll>, <&clk_gpll>;
457 clock-output-names = "aclk_peri";
459 #clock-init-cells = <1>;
463 clk_sel_con11: sel-con@0070 {
464 compatible = "rockchip,rk3188-selcon";
466 #address-cells = <1>;
469 clk_sdmmc: clk_sdmmc_div {
470 compatible = "rockchip,rk3188-div-con";
471 rockchip,bits = <0 6>;
472 clocks = <&hclk_peri>;
473 clock-output-names = "clk_sdmmc";
474 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
475 rockchip,clkops-idx =
476 <CLKOPS_RATE_EVENDIV>;
480 /* reg[7:6]: reserved */
482 clk_ehci1phy12m: ehci1_phy_div {
483 compatible = "rockchip,rk3188-div-con";
484 rockchip,bits = <8 6>;
485 clocks = <&clk_ehci1phy480m>;
486 clock-output-names = "clk_ehci1phy12m";
487 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
491 /* reg[15:14]: reserved */
495 clk_sel_con12: sel-con@0074 {
496 compatible = "rockchip,rk3188-selcon";
498 #address-cells = <1>;
501 clk_sdio: clk_sdio_div {
502 compatible = "rockchip,rk3188-div-con";
503 rockchip,bits = <0 6>;
504 clocks = <&hclk_peri>;
505 clock-output-names = "clk_sdio";
506 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
507 rockchip,clkops-idx =
508 <CLKOPS_RATE_EVENDIV>;
512 /* reg[7:6]: reserved */
514 clk_emmc: clk_emmc_div {
515 compatible = "rockchip,rk3188-div-con";
516 rockchip,bits = <8 6>;
517 clocks = <&hclk_peri>;
518 clock-output-names = "clk_emmc";
519 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
520 rockchip,clkops-idx =
521 <CLKOPS_RATE_EVENDIV>;
525 /* reg[14]: reserved */
527 clk_uart_pll_mux: clk_uart_pll_mux {
528 compatible = "rockchip,rk3188-mux-con";
529 rockchip,bits = <15 1>;
530 clocks = <&clk_gpll>, <&clk_cpll>;
531 clock-output-names = "clk_uart_pll";
533 #clock-init-cells = <1>;
537 clk_sel_con13: sel-con@0078 {
538 compatible = "rockchip,rk3188-selcon";
540 #address-cells = <1>;
543 clk_uart0_div: clk_uart0_div {
544 compatible = "rockchip,rk3188-div-con";
545 rockchip,bits = <0 7>;
546 clocks = <&clk_uart_pll_mux>;
547 clock-output-names = "clk_uart0_div";
548 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
552 /* reg[7]: reserved */
554 clk_uart0: clk_uart0_mux {
555 compatible = "rockchip,rk3188-mux-con";
556 rockchip,bits = <8 2>;
557 clocks = <&clk_uart0_div>, <&clk_uart0_frac>,
559 rockchip,clkops-idx =
561 rockchip,flags = <CLK_SET_RATE_PARENT>;
562 clock-output-names = "clk_uart0";
566 /* reg[15:10]: reserved */
570 clk_sel_con14: sel-con@007c {
571 compatible = "rockchip,rk3188-selcon";
573 #address-cells = <1>;
576 clk_uart1_div: clk_uart1_div {
577 compatible = "rockchip,rk3188-div-con";
578 rockchip,bits = <0 7>;
579 clocks = <&clk_uart_pll_mux>;
580 clock-output-names = "clk_uart1_div";
581 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
585 /* reg[7]: reserved */
587 clk_uart1: clk_uart1_mux {
588 compatible = "rockchip,rk3188-mux-con";
589 rockchip,bits = <8 2>;
590 clocks = <&clk_uart1_div>, <&clk_uart1_frac>,
592 rockchip,clkops-idx =
594 rockchip,flags = <CLK_SET_RATE_PARENT>;
595 clock-output-names = "clk_uart1";
599 /* reg[15:10]: reserved */
603 clk_sel_con15: sel-con@0080 {
604 compatible = "rockchip,rk3188-selcon";
606 #address-cells = <1>;
609 clk_uart2_div: clk_uart2_div {
610 compatible = "rockchip,rk3188-div-con";
611 rockchip,bits = <0 7>;
612 clocks = <&clk_uart_pll_mux>;
613 clock-output-names = "clk_uart2_div";
614 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
618 /* reg[7]: reserved */
620 clk_uart2: clk_uart2_mux {
621 compatible = "rockchip,rk3188-mux-con";
622 rockchip,bits = <8 2>;
623 clocks = <&clk_uart2_div>, <&clk_uart2_frac>,
625 rockchip,clkops-idx =
627 rockchip,flags = <CLK_SET_RATE_PARENT>;
628 clock-output-names = "clk_uart2";
632 /* reg[15:10]: reserved */
636 clk_sel_con16: sel-con@0084 {
637 compatible = "rockchip,rk3188-selcon";
639 #address-cells = <1>;
642 clk_uart3_div: clk_uart3_div {
643 compatible = "rockchip,rk3188-div-con";
644 rockchip,bits = <0 7>;
645 clocks = <&clk_uart_pll_mux>;
646 clock-output-names = "clk_uart3_div";
647 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
651 /* reg[7]: reserved */
653 clk_uart3: clk_uart3_mux {
654 compatible = "rockchip,rk3188-mux-con";
655 rockchip,bits = <8 2>;
656 clocks = <&clk_uart3_div>, <&clk_uart3_frac>,
658 rockchip,clkops-idx =
660 rockchip,flags = <CLK_SET_RATE_PARENT>;
661 clock-output-names = "clk_uart3";
665 /* reg[15:10]: reserved */
669 clk_sel_con17: sel-con@0088 {
670 compatible = "rockchip,rk3188-selcon";
672 #address-cells = <1>;
674 clk_uart0_frac: clk_uart0_frac {
675 compatible = "rockchip,rk3188-frac-con";
676 clocks = <&clk_uart0_div>;
677 clock-output-names = "clk_uart0_frac";
678 /* numerator denominator */
679 rockchip,bits = <0 32>;
680 rockchip,clkops-idx =
685 clk_sel_con18: sel-con@008c {
686 compatible = "rockchip,rk3188-selcon";
688 #address-cells = <1>;
690 clk_uart1_frac: clk_uart1_frac {
691 compatible = "rockchip,rk3188-frac-con";
692 clocks = <&clk_uart1_div>;
693 clock-output-names = "clk_uart1_frac";
694 /* numerator denominator */
695 rockchip,bits = <0 32>;
696 rockchip,clkops-idx =
701 clk_sel_con19: sel-con@0090 {
702 compatible = "rockchip,rk3188-selcon";
704 #address-cells = <1>;
706 clk_uart2_frac: clk_uart2_frac {
707 compatible = "rockchip,rk3188-frac-con";
708 clocks = <&clk_uart2_div>;
709 clock-output-names = "clk_uart2_frac";
710 /* numerator denominator */
711 rockchip,bits = <0 32>;
712 rockchip,clkops-idx =
717 clk_sel_con20: sel-con@0094 {
718 compatible = "rockchip,rk3188-selcon";
720 #address-cells = <1>;
722 clk_uart3_frac: clk_uart3_frac {
723 compatible = "rockchip,rk3188-frac-con";
724 clocks = <&clk_uart3_div>;
725 clock-output-names = "clk_uart3_frac";
726 /* numerator denominator */
727 rockchip,bits = <0 32>;
728 rockchip,clkops-idx =
734 clk_sel_con21: sel-con@0098 {
735 compatible = "rockchip,rk3188-selcon";
737 #address-cells = <1>;
740 clk_mac_pll_mux: clk_mac_pll_mux {
741 compatible = "rockchip,rk3188-mux-con";
742 rockchip,bits = <0 1>;
743 clocks = <&clk_gpll>, <&clk_dpll>;
744 clock-output-names = "clk_mac_pll";
748 /* reg[3:1]: reserved */
750 clk_mac: clk_mac_mux {
751 compatible = "rockchip,rk3188-mux-con";
752 rockchip,bits = <4 1>;
753 clocks = <&clk_mac_pll_mux>, <&rmii_clkin>;
754 rockchip,clkops-idx =
755 <CLKOPS_RATE_MAC_REF>;
756 rockchip,flags = <CLK_SET_RATE_PARENT>;
757 clock-output-names = "clk_mac";
761 /* reg[7:5]: reserved */
763 clk_mac_pll_div: clk_mac_pll_div {
764 compatible = "rockchip,rk3188-div-con";
765 rockchip,bits = <8 5>;
766 clocks = <&clk_mac_pll_mux>;
767 clock-output-names = "clk_mac_pll";
768 rockchip,clkops-idx =
769 <CLKOPS_RATE_MUX_DIV>;
770 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
774 /* reg[15:13]: reserved */
777 clk_sel_con22: sel-con@009c {
778 compatible = "rockchip,rk3188-selcon";
780 #address-cells = <1>;
783 clk_hsadc_pll_mux: clk_hsadc_pll_mux {
784 compatible = "rockchip,rk3188-mux-con";
785 rockchip,bits = <0 1>;
786 clocks = <&clk_gpll>, <&clk_cpll>;
787 clock-output-names = "clk_hsadc_pll";
791 /* reg[3:1]: reserved */
793 clk_hsadc: clk_hsadc_mux {
794 compatible = "rockchip,rk3188-mux-con";
795 rockchip,bits = <4 2>;
796 clocks = <&clk_hsadc_pll_mux>, <&clk_hsadc_frac>,
798 rockchip,clkops-idx =
800 rockchip,flags = <CLK_SET_RATE_PARENT>;
801 clock-output-names = "clk_hsadc";
805 /* reg[6]: reserved */
807 clk_hsadc_inv: clk_hsadc_inv {
808 compatible = "rockchip,rk3188-inv-con";
809 rockchip,bits = <7 1>;
810 clocks = <&clk_hsadc>;
813 clk_hsadc_div: clk_hsadc_div {
814 compatible = "rockchip,rk3188-div-con";
815 rockchip,bits = <8 8>;
816 clocks = <&clk_hsadc_pll_mux>;
817 clock-output-names = "clk_hsadc_pll";
818 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
823 clk_sel_con23: sel-con@00a0 {
824 compatible = "rockchip,rk3188-selcon";
826 #address-cells = <1>;
829 clk_hsadc_frac: clk_hsadc_frac{
830 compatible = "rockchip,rk3188-frac-con";
831 clocks = <&clk_hsadc_pll_mux>;
832 clock-output-names = "clk_hsadc_frac";
833 /* numerator denominator */
834 rockchip,bits = <0 32>;
835 rockchip,clkops-idx =
841 clk_sel_con24: sel-con@00a4 {
842 compatible = "rockchip,rk3188-selcon";
844 #address-cells = <1>;
846 clk_saradc: clk_saradc_div {
847 compatible = "rockchip,rk3188-div-con";
848 rockchip,bits = <8 8>;
850 clock-output-names = "clk_saradc";
851 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
856 clk_sel_con25: sel-con@00a8 {
857 compatible = "rockchip,rk3188-selcon";
859 #address-cells = <1>;
862 clk_spi0: clk_spi0_div {
863 compatible = "rockchip,rk3188-div-con";
864 rockchip,bits = <0 7>;
865 clocks = <&pclk_peri>;
866 clock-output-names = "clk_spi0";
867 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
870 /* reg[7]: reserved */
871 clk_spi1: clk_spi1_div {
872 compatible = "rockchip,rk3188-div-con";
873 rockchip,bits = <8 7>;
874 clocks = <&pclk_peri>;
875 clock-output-names = "clk_spi1";
876 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
879 /* reg[15]: reserved */
882 clk_sel_con26: sel-con@00ac {
883 compatible = "rockchip,rk3188-selcon";
885 #address-cells = <1>;
888 clk_ddr_div: clk_ddr_div {
889 compatible = "rockchip,rk3188-div-con";
890 rockchip,bits = <0 2>;
892 clock-output-names = "clk_ddr";
893 rockchip,div-type = <CLK_DIVIDER_POWER_OF_TWO>;
894 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
898 /* reg[7:2]: reserved */
900 clk_ddr: clk_ddr_mux {
901 compatible = "rockchip,rk3188-mux-con";
902 rockchip,bits = <8 1>;
903 clocks = <&clk_dpll>,
905 clock-output-names = "clk_ddr";
906 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
907 CLK_SET_RATE_NO_REPARENT)>;
911 /* reg[15:9]: reserved */
914 clk_sel_con27: sel-con@00b0 {
915 compatible = "rockchip,rk3188-selcon";
917 #address-cells = <1>;
920 dclk_lcdc0: dclk_lcdc0_mux {
921 compatible = "rockchip,rk3188-mux-con";
922 rockchip,bits = <0 1>;
923 clocks = <&clk_cpll>, <&clk_gpll>;
924 clock-output-names = "dclk_lcdc0";
928 /* reg[7:1]: reserved */
930 dclk_lcdc0_div: dclk_lcdc0_div {
931 compatible = "rockchip,rk3188-div-con";
932 rockchip,bits = <8 8>;
933 clocks = <&dclk_lcdc0>;
934 clock-output-names = "dclk_lcdc0";
935 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
936 rockchip,clkops-idx =
937 <CLKOPS_RATE_MUX_EVENDIV>;
943 clk_sel_con28: sel-con@00b4 {
944 compatible = "rockchip,rk3188-selcon";
946 #address-cells = <1>;
949 dclk_lcdc1: dclk_lcdc1_mux {
950 compatible = "rockchip,rk3188-mux-con";
951 rockchip,bits = <0 1>;
952 clocks = <&clk_cpll>, <&clk_gpll>;
953 clock-output-names = "dclk_lcdc1";
957 /* reg[7:1]: reserved */
959 dclk_lcdc1_div: dclk_lcdc1_div {
960 compatible = "rockchip,rk3188-div-con";
961 rockchip,bits = <8 8>;
962 clocks = <&dclk_lcdc1>;
963 clock-output-names = "dclk_lcdc1";
964 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
965 rockchip,clkops-idx =
966 <CLKOPS_RATE_MUX_EVENDIV>;
971 clk_sel_con29: sel-con@00b8 {
972 compatible = "rockchip,rk3188-selcon";
974 #address-cells = <1>;
977 cif_out_pll_mux: cif_out_pll_mux {
978 compatible = "rockchip,rk3188-mux-con";
979 rockchip,bits = <0 1>;
980 clocks = <&clk_cpll>, <&clk_gpll>;
981 clock-output-names = "cif_out_pll";
985 cif0_out_div: cif0_out_div {
986 compatible = "rockchip,rk3188-div-con";
987 rockchip,bits = <1 5>;
988 clocks = <&cif_out_pll_mux>;
989 clock-output-names = "cif_out_pll";
990 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
991 rockchip,clkops-idx =
992 <CLKOPS_RATE_MUX_DIV>;
996 /* reg[6]: reserved */
998 clk_cif0: cif0_out_mux {
999 compatible = "rockchip,rk3188-mux-con";
1000 rockchip,bits = <7 1>;
1001 clocks = <&cif_out_pll_mux>, <&xin24m>;
1002 rockchip,clkops-idx =
1003 <CLKOPS_RATE_CIFOUT>;
1004 rockchip,flags = <CLK_SET_RATE_PARENT>;
1005 clock-output-names = "clk_cif0";
1009 /* reg[15:8]: reserved */
1012 clk_sel_con30: sel-con@00bc {
1013 compatible = "rockchip,rk3188-selcon";
1015 #address-cells = <1>;
1018 clk_ehci1phy480m: clk_ehci1phy480m_mux {
1019 compatible = "rockchip,rk3188-mux-con";
1020 rockchip,bits = <0 2>;
1021 clocks = <&otgphy0_480m>, <&otgphy1_480m>,
1022 <&clk_gpll>, <&clk_cpll>;
1023 clock-output-names = "clk_ehci1phy480m";
1027 /* reg[7:2]: reserved */
1029 /* inv here?????? */
1031 /* reg[15:9]: reserved */
1034 clk_sel_con31: sel-con@00c0 {
1035 compatible = "rockchip,rk3188-selcon";
1037 #address-cells = <1>;
1040 aclk_lcdc0_pre_div: aclk_lcdc0_pre_div {
1041 compatible = "rockchip,rk3188-div-con";
1042 rockchip,bits = <0 5>;
1043 clocks = <&aclk_lcdc0>;
1044 clock-output-names = "aclk_lcdc0";
1045 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1046 rockchip,clkops-idx =
1047 <CLKOPS_RATE_MUX_DIV>;
1051 /* reg[6:5]: reserved */
1053 aclk_lcdc0: aclk_lcdc0_pre_mux {
1054 compatible = "rockchip,rk3188-mux-con";
1055 rockchip,bits = <7 1>;
1056 clocks = <&clk_cpll>, <&clk_gpll>;
1057 clock-output-names = "aclk_lcdc0";
1059 #clock-init-cells = <1>;
1062 aclk_lcdc1_pre_div: aclk_lcdc1_pre_div {
1063 compatible = "rockchip,rk3188-div-con";
1064 rockchip,bits = <8 5>;
1065 clocks = <&aclk_lcdc1>;
1066 clock-output-names = "aclk_lcdc1";
1067 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1068 rockchip,clkops-idx =
1069 <CLKOPS_RATE_MUX_DIV>;
1073 /* reg[14:13]: reserved */
1075 aclk_lcdc1: aclk_lcdc1_pre_mux {
1076 compatible = "rockchip,rk3188-mux-con";
1077 rockchip,bits = <15 1>;
1078 clocks = <&clk_cpll>, <&clk_gpll>;
1079 clock-output-names = "aclk_lcdc1";
1081 #clock-init-cells = <1>;
1085 clk_sel_con32: sel-con@00c4 {
1086 compatible = "rockchip,rk3188-selcon";
1088 #address-cells = <1>;
1091 aclk_vepu_div: aclk_vepu_div {
1092 compatible = "rockchip,rk3188-div-con";
1093 rockchip,bits = <0 5>;
1094 clocks = <&clk_vepu>;
1095 clock-output-names = "clk_vepu";
1096 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1097 rockchip,clkops-idx =
1098 <CLKOPS_RATE_MUX_DIV>;
1102 /* reg[6:5]: reserved */
1104 clk_vepu: aclk_vepu_mux {
1105 compatible = "rockchip,rk3188-mux-con";
1106 rockchip,bits = <7 1>;
1107 clocks = <&clk_cpll>, <&clk_gpll>;
1108 clock-output-names = "clk_vepu";
1112 aclk_vdpu_div: aclk_vdpu_div {
1113 compatible = "rockchip,rk3188-div-con";
1114 rockchip,bits = <8 5>;
1115 clocks = <&clk_vdpu>;
1116 clock-output-names = "clk_vdpu";
1117 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1118 rockchip,clkops-idx =
1119 <CLKOPS_RATE_MUX_DIV>;
1123 /* reg[14:13]: reserved */
1125 clk_vdpu: aclk_vdpu_mux {
1126 compatible = "rockchip,rk3188-mux-con";
1127 rockchip,bits = <15 1>;
1128 clocks = <&clk_cpll>, <&clk_gpll>;
1129 clock-output-names = "clk_vdpu";
1134 clk_sel_con34: sel-con@00cc {
1135 compatible = "rockchip,rk3188-selcon";
1137 #address-cells = <1>;
1140 aclk_gpu_div: aclk_gpu_div {
1141 compatible = "rockchip,rk3188-div-con";
1142 rockchip,bits = <0 5>;
1143 clocks = <&clk_gpu>;
1144 clock-output-names = "clk_gpu";
1145 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1146 rockchip,clkops-idx =
1147 <CLKOPS_RATE_MUX_DIV>;
1151 /* reg[6:5]: reserved */
1153 clk_gpu: aclk_gpu_mux {
1154 compatible = "rockchip,rk3188-mux-con";
1155 rockchip,bits = <7 1>;
1156 clocks = <&clk_cpll>, <&clk_gpll>;
1157 clock-output-names = "clk_gpu";
1159 #clock-init-cells = <1>;
1162 /* reg[15:8]: reserved */
1166 /* Gate control regs */
1168 compatible = "rockchip,rk-gate-cons";
1169 #address-cells = <1>;
1173 clk_gates0: gate-clk@00d0 {
1174 compatible = "rockchip,rk3188-gate-clk";
1176 clocks = <&clk_core_peri>, <&clk_gpll>,
1177 <&clk_dpll>, <&aclk_cpu>,
1179 <&hclk_cpu>, <&pclk_cpu>,
1180 <&pclk_cpu>, <&aclk_core>,
1182 <&dummy>, <&clk_i2s_div>,
1183 <&clk_i2s_frac>, <&dummy>,
1185 <&dummy>, <&clk_spdif_div>,
1186 <&clk_spdif_frac>, <&dummy>;
1188 clock-output-names =
1189 "clk_core_peri", "clk_arm_gpll",
1190 "clk_dpll", "aclk_cpu",
1192 "hclk_cpu", "pclk_cpu",
1193 "g_atclk_cpu", "aclk_core",
1195 "reserved", "clk_i2s_div",
1196 "clk_i2s_frac", "reserved",
1198 "reserved", "clk_spdif_div",
1199 "clk_spdif_frac", "g_testclk";
1200 rockchip,suspend-clkgating-setting=<0x00bf 0x00bf>;
1205 clk_gates1: gate-clk@00d4 {
1206 compatible = "rockchip,rk3188-gate-clk";
1208 clocks = <&xin24m>, <&xin24m>,
1209 <&xin24m>, <&dummy>,
1211 <&aclk_lcdc1>, <&xin24m>,
1212 <&xin24m>, <&clk_gpll>,
1214 <&clk_uart0_div>, <&clk_uart0_frac>,
1215 <&clk_uart1_div>, <&clk_uart1_frac>,
1217 <&clk_uart2_div>, <&clk_uart2_frac>,
1218 <&clk_uart3_div>, <&clk_uart3_frac>;
1220 clock-output-names =
1224 "aclk_lcdc1", "g_otgphy0",
1225 "g_otgphy1", "clk_ddr_gpll",
1227 "clk_uart0_div", "clk_uart0_frac",
1228 "clk_uart1_div", "clk_uart1_frac",
1230 "clk_uart2_div", "clk_uart2_frac",
1231 "clk_uart3_div", "clk_uart3_frac";
1232 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1237 clk_gates2: gate-clk@00d8 {
1238 compatible = "rockchip,rk3188-gate-clk";
1240 clocks = <&aclk_peri>, <&aclk_peri>,
1241 <&hclk_peri>, <&pclk_peri>,
1243 <&hclk_peri>, <&clk_mac_pll_mux>,
1244 <&clk_hsadc_pll_mux>, <&clk_hsadc_frac>,
1246 <&clk_saradc>, <&clk_spi0>,
1247 <&clk_spi1>, <&clk_sdmmc>,
1249 <&dummy>, <&clk_sdio>,
1250 <&clk_emmc>, <&dummy>;
1252 clock-output-names =
1253 "aclk_peri", "g_aclk_peri",
1254 "hclk_peri", "pclk_peri",
1256 "g_smc_src", "clk_mac_pll",
1257 "clk_hsadc_pll", "clk_hsadc_frac",
1259 "clk_saradc", "clk_spi0",
1260 "clk_spi1", "clk_sdmmc",
1262 "g_mac_lbtest", "clk_sdio",
1263 "clk_emmc", "reserved";
1264 //rockchip,suspend-clkgating-setting=<0x1f 0x1b>;
1265 rockchip,suspend-clkgating-setting=<0x1f 0x1b>;
1270 clk_gates3: gate-clk@00dc {
1271 compatible = "rockchip,rk3188-gate-clk";
1273 clocks = <&aclk_lcdc0>, <&dclk_lcdc0>,
1274 <&dclk_lcdc1>, <&clk_cif_in>,
1276 <&xin24m>, <&xin24m>,
1277 <&clk_ehci1phy480m>, <&clk_cif0>,
1279 <&xin24m>, <&clk_vepu>,
1280 <&clk_vepu>, <&clk_vdpu>,
1282 <&clk_vdpu>, <&dummy>,
1283 <&xin24m>, <&clk_gpu>;
1285 clock-output-names =
1286 "aclk_lcdc0", "dclk_lcdc0",
1287 "dclk_lcdc1", "g_clk_cif_in",
1290 * FIXME: cif_out_pll can be set to
1291 * clk_cif as virtual
1294 "clk_ehci1phy480m", "clk_cif0",
1296 "timer5", "clk_vepu",
1297 "g_h_vepu", "clk_vdpu",
1299 "g_h_vdpu", "reserved",
1300 "timer6", "clk_gpu";
1301 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1306 clk_gates4: gate-clk@00e0 {
1307 compatible = "rockchip,rk3188-gate-clk";
1309 clocks = <&hclk_peri>, <&pclk_peri>,
1310 <&aclk_peri>, <&aclk_peri>,
1312 <&aclk_peri>, <&hclk_peri>,
1313 <&hclk_peri>, <&hclk_peri>,
1315 <&hclk_cpu>, <&hclk_cpu>,
1316 <&aclk_cpu>, <&dummy>,
1318 <&aclk_cpu>, <&dummy>,
1319 <&hclk_cpu>, <&hclk_cpu>;
1322 * g_ap: gate_aclk_peri_...
1323 * g_hp: gate_hclk_peri_...
1324 * g_pp: gate_pclk_peri_...
1326 clock-output-names =
1327 "g_hp_axi_matrix", "g_pp_axi_matrix",
1328 "g_a_cpu_peri", "g_ap_axi_matrix",
1330 "g_a_peri_niu", "g_h_usb_peri",
1331 "g_hp_ahb_arbi", "g_h_emem_peri",
1333 "g_h_cpubus", "g_h_ahb2apb",
1334 "g_a_strc_sys", "reserved",
1336 "g_a_intmem", "reserved",
1337 "g_h_imem1", "g_h_imem0";
1339 //rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>;
1340 rockchip,suspend-clkgating-setting=<0xd75e 0xd75e>;
1344 clk_gates5: gate-clk@00e4 {
1345 compatible = "rockchip,rk3188-gate-clk";
1347 clocks = <&aclk_cpu>, <&aclk_peri>,
1348 <&pclk_cpu>, <&pclk_cpu>,
1350 <&pclk_cpu>, <&pclk_cpu>,
1351 <&hclk_cpu>, <&pclk_cpu>,
1353 <&aclk_peri>, <&hclk_peri>,
1354 <&hclk_peri>, <&hclk_peri>,
1356 <&hclk_peri>, <&hclk_peri>;
1358 clock-output-names =
1359 "g_a_dmac1", "g_a_dmac2",
1360 "g_p_efuse", "g_p_tzpc",
1362 "g_p_grf", "g_p_pmu",
1363 "g_h_rom", "g_p_ddrupctl",
1365 "g_a_smc", "g_h_nandc",
1366 "g_h_sdmmc0", "g_h_sdio",
1368 "g_h_emmc", "g_h_otg0";
1369 rockchip,suspend-clkgating-setting=<0x80 0x80>;
1374 clk_gates6: gate-clk@00e8 {
1375 compatible = "rockchip,rk3188-gate-clk";
1377 clocks = <&clk_gates6 13>, <&hclk_cpu>,
1378 <&hclk_cpu>, <&clk_gates9 5>,
1380 <&hclk_cpu>, <&clk_gates6 13>,
1383 <&clk_gates6 13>, <&hclk_cpu>,
1384 <&hclk_cpu>, <&clk_gates9 5>,
1386 <&hclk_cpu>, <&aclk_lcdc0>;
1388 clock-output-names =
1389 "g_a_lcdc0", "g_h_lcdc0",
1390 "g_h_lcdc1", "g_a_lcdc1",
1392 "g_h_cif0", "g_a_cif0",
1393 "reserved", "reserved",
1395 "g_a_ipp", "g_h_ipp",
1396 "g_h_rga", "g_a_rga",
1398 "g_h_vio_bus", "g_a_vio0";
1400 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1404 clk_gates7: gate-clk@00ec {
1405 compatible = "rockchip,rk3188-gate-clk";
1407 clocks = <&hclk_peri>, <&hclk_cpu>,
1408 <&hclk_cpu>, <&hclk_peri>,
1410 <&hclk_peri>, <&hclk_peri>,
1411 <&hclk_peri>, <&pclk_cpu>,
1413 <&dummy>, <&pclk_cpu>,
1414 <&pclk_cpu>, <&pclk_peri>,
1416 <&pclk_peri>, <&pclk_peri>,
1417 <&pclk_peri>, <&pclk_peri>;
1419 clock-output-names =
1420 "g_h_emac", "g_h_spdif",
1421 "g_h_i2s0_2ch", "g_h_otg1",
1423 "g_h_ehci1", "g_h_hsadc",
1424 "g_h_pidf", "g_p_timer0",
1426 "reserved", "g_p_timer2",
1427 "g_p_pwm01", "g_p_pwm23",
1429 "g_p_spi0", "g_p_spi1",
1430 "g_p_saradc", "g_p_wdt";
1431 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1436 clk_gates8: gate-clk@00f0 {
1437 compatible = "rockchip,rk3188-gate-clk";
1439 clocks = <&pclk_ahb2apb>, <&pclk_ahb2apb>,
1440 <&pclk_peri>, <&pclk_peri>,
1442 <&pclk_cpu>, <&pclk_cpu>,
1443 <&pclk_peri>, <&pclk_peri>,
1445 <&pclk_peri>, <&pclk_cpu>,
1446 <&pclk_cpu>, <&pclk_cpu>,
1448 <&pclk_peri>, <&aclk_peri>;
1450 clock-output-names =
1451 "g_p_uart0", "g_p_uart1",
1452 "g_p_uart2", "g_p_uart3",
1454 "g_p_i2c0", "g_p_i2c1",
1455 "g_p_i2c2", "g_p_i2c3",
1457 "g_p_i2c4", "g_p_gpio0",
1458 "g_p_gpio1", "g_p_gpio2",
1460 "g_p_gpio3", "g_a_gps";
1461 rockchip,suspend-clkgating-setting=<0x200 0x200>;
1466 clk_gates9: gate-clk@00f4 {
1467 compatible = "rockchip,rk3188-gate-clk";
1469 clocks = <&clk_core>, <&pclk_cpu>,
1470 <&clk_gates0 6>, <&clk_gates0 6>,
1472 <&clk_core>, <&aclk_lcdc1>,
1473 <&pclk_cpu>, <&clk_gpu>;
1475 clock-output-names =
1476 "g_clk_core_dbg", "g_p_dbg",
1477 "g_clk_trace", "g_atclk",
1479 "g_clk_l2c", "g_a_vio1",
1480 "g_p_ddrpubl", "g_a_gpu";
1481 rockchip,suspend-clkgating-setting=<0x50 0x50>;