arch/arm/boot/dts/rk312x.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/sensor-dev.h>
   4 #include <dt-bindings/clock/rk_system_status.h>
   5 #include <dt-bindings/rkfb/rk_fb.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk312x-clocks.dtsi"
   9 #include "rk312x-pinctrl.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk312x";
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18                 serial1 = &uart1;
  19                 serial2 = &uart2;
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 i2c3 = &i2c3;
  24                 lcdc = &lcdc;
  25                 spi0 = &spi0;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a7";
  35                         reg = <0xf00>;
  36                 };
  37                 cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0xf01>;
  41                 };
  42                 cpu@2 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a7";
  45                         reg = <0xf02>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a7";
  50                         reg = <0xf03>;
  51                 };
  52         };
  53
  54         psci {
  55                 compatible      = "arm,psci";
  56                 method          = "smc";
  57                 cpu_suspend     = <0x84000001>;
  58                 cpu_off         = <0x84000002>;
  59                 cpu_on          = <0x84000003>;
  60                 migrate         = <0x84000005>;
  61         };
  62
  63         gic: interrupt-controller@10139000 {
  64                 compatible = "arm,cortex-a15-gic";
  65                 interrupt-controller;
  66                 #interrupt-cells = <3>;
  67                 #address-cells = <0>;
  68                 reg = <0x10139000 0x1000>,
  69                       <0x1013a000 0x1000>;
  70         };
  71
  72         arm-pmu {
  73                 compatible = "arm,cortex-a7-pmu";
  74                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  77                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  78         };
  79
  80         cpu_axi_bus: cpu_axi_bus {
  81                 compatible = "rockchip,cpu_axi_bus";
  82                 #address-cells = <1>;
  83                 #size-cells = <1>;
  84                 ranges;
  85
  86                 qos {
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         ranges;
  90
  91                         crypto {
  92                                 reg = <0x10128080 0x20>;
  93                         };
  94                         core {
  95                                 reg = <0x1012a000 0x20>;
  96                         };
  97                         peri {
  98                                 reg = <0x1012c000 0x20>;
  99                         };
 100                         gpu {
 101                                 reg = <0x1012d000 0x20>;
 102                         };
 103                         vpu {
 104                                 reg = <0x1012e000 0x20>;
 105                         };
 106                         rga {
 107                                 reg = <0x1012f000 0x20>;
 108                         };
 109                         ebc {
 110                                 reg = <0x1012f080 0x20>;
 111                         };
 112                         iep {
 113                                 reg = <0x1012f100 0x20>;
 114                         };
 115                         lcdc {
 116                                 reg = <0x1012f180 0x20>;
 117                                 rockchip,priority = <3 3>;
 118                         };
 119                         vip {
 120                                 reg = <0x1012f200 0x20>;
 121                                 rockchip,priority = <3 3>;
 122                         };
 123                 };
 124
 125                 msch {
 126                         #address-cells = <1>;
 127                         #size-cells = <1>;
 128                         ranges;
 129
 130                         msch@10128000 {
 131                                 reg = <0x10128000 0x20>;
 132                                 rockchip,read-latency = <0x3f>;
 133                         };
 134                 };
 135         };
 136
 137         sram: sram@10080400 {
 138                 compatible = "mmio-sram";
 139                 reg = <0x10080400 0x1C00>;
 140                 map-exec;
 141                 map-cacheable;
 142         };
 143
 144         timer {
 145                 compatible = "arm,armv7-timer";
 146                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 147                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 148                 clock-frequency = <24000000>;
 149         };
 150
 151         timer@20044000 {
 152                 compatible = "rockchip,timer";
 153                 reg = <0x20044000 0x20>;
 154                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 155                 rockchip,broadcast = <1>;
 156         };
 157
 158         watchdog: wdt@2004c000 {
 159                 compatible = "rockchip,watch dog";
 160                 reg = <0x2004c000 0x100>;
 161         //      clocks = <&clk_gates7 15>;
 162                 clock-names = "pclk_wdt";
 163                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 164                 rockchip,irq = <1>;
 165                 rockchip,timeout = <60>;
 166                 rockchip,atboot = <1>;
 167                 rockchip,debug = <0>;
 168                 status = "disabled";
 169         };
 170
 171         amba {
 172                 #address-cells = <1>;
 173                 #size-cells = <1>;
 174                 compatible = "arm,amba-bus";
 175                 interrupt-parent = <&gic>;
 176                 ranges;
 177
 178                 pdma: pdma@20078000 {
 179                         compatible = "arm,pl330", "arm,primecell";
 180                         reg = <0x20078000 0x4000>;
 181                         clocks = <&clk_gates5 1>;
 182                         clock-names = "apb_pclk";
 183                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 184                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 185                         #dma-cells = <1>;
 186                         arm,pl330-broken-no-flushp;
 187                         peripherals-req-type-burst;
 188                 };
 189         };
 190
 191         reset: reset@20000110 {
 192                 compatible = "rockchip,reset";
 193                 reg = <0x20000110 0x24>;
 194                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 195                 #reset-cells = <1>;
 196         };
 197
 198         nandc: nandc@10500000 {
 199                 compatible = "rockchip,rk-nandc";
 200                 reg = <0x10500000 0x4000>;
 201                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 202                 //pinctrl-names = "default";
 203                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 204                 nandc_id = <0>;
 205                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 15>;
 206                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 207         };
 208
 209         nandc0reg: nandc0@10500000 {
 210                 compatible = "rockchip,rk-nandc";
 211                 reg = <0x10500000 0x4000>;
 212         };
 213         uart0: serial@20060000 {
 214                 compatible = "rockchip,serial";
 215                 reg = <0x20060000 0x100>;
 216                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 217                 clock-frequency = <24000000>;
 218                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 219                 clock-names = "sclk_uart", "pclk_uart";
 220                 reg-shift = <2>;
 221                 reg-io-width = <4>;
 222                 dmas = <&pdma 2>, <&pdma 3>;
 223                 #dma-cells = <2>;
 224                 pinctrl-names = "default";
 225                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 226                 status = "disabled";
 227         };
 228
 229         uart1: serial@20064000 {
 230                 compatible = "rockchip,serial";
 231                 reg = <0x20064000 0x100>;
 232                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 233                 clock-frequency = <24000000>;
 234                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 235                 clock-names = "sclk_uart", "pclk_uart";
 236                 reg-shift = <2>;
 237                 reg-io-width = <4>;
 238                 dmas = <&pdma 4>, <&pdma 5>;
 239                 #dma-cells = <2>;
 240                 pinctrl-names = "default";
 241                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 242                 status = "disabled";
 243         };
 244
 245         uart2: serial@20068000 {
 246                 compatible = "rockchip,serial";
 247                 reg = <0x20068000 0x100>;
 248                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 249                 clock-frequency = <24000000>;
 250                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 251                 clock-names = "sclk_uart", "pclk_uart";
 252                 reg-shift = <2>;
 253                 reg-io-width = <4>;
 254                 dmas = <&pdma 6>, <&pdma 7>;
 255                 #dma-cells = <2>;
 256                 pinctrl-names = "default";
 257                 pinctrl-0 = <&uart2_xfer>;
 258                 status = "disabled";
 259         };
 260
 261         gmac: eth@2008c000 {
 262                 compatible = "rockchip,rk312x-gmac";
 263                 reg = <0x2008c000 0x4000>;
 264                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;  /*irq=88*/
 265                 interrupt-names = "macirq";
 266                 clocks = <&clk_mac_ref>, <&clk_gates2 6>,
 267                         <&clk_gates2 7>, <&clk_gates2 4>,
 268                         <&clk_gates2 5>, <&clk_gates10 10>,
 269                         <&clk_gates10 11>;
 270                 clock-names = "clk_mac", "mac_clk_rx",
 271                         "mac_clk_tx", "clk_mac_ref",
 272                         "clk_mac_refout", "aclk_mac",
 273                         "pclk_mac";
 274                 phy-mode = "rgmii";
 275                 pinctrl-names = "default";
 276                 pinctrl-0 = <&gmac_rxdv &gmac_txclk &gmac_crs &gmac_rxclk &gmac_mdio &gmac_txen &gmac_clk &gmac_rxer &gmac_rxd1 &gmac_rxd0 &gmac_txd1 &gmac_txd0 &gmac_rxd3 &gmac_rxd2 &gmac_txd2 &gmac_txd3 &gmac_col_gpio &gmac_mdc>;
 277         };
 278
 279         fiq-debugger {
 280                 compatible = "rockchip,fiq-debugger";
 281                 rockchip,serial-id = <2>;
 282                 rockchip,signal-irq = <106>;
 283                 rockchip,wake-irq = <0>;
 284                 status = "disabled";
 285         };
 286
 287         rockchip_clocks_init: clocks-init{
 288                 compatible = "rockchip,clocks-init";
 289                 rockchip,clocks-init-parent =
 290                         <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
 291                         <&aclk_peri &clk_gpll_div2>, <&clk_uart0_pll &clk_gpll>,
 292                         <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
 293                         <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 294                         <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
 295                         <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
 296                         <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
 297                         <&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll_div2>,
 298                         <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
 299                         <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
 300                         <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
 301                         <&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
 302                         <&clk_mac_pll &clk_cpll>;
 303                 rockchip,clocks-init-rate =
 304                         <&clk_core 600000000>, <&clk_gpll 594000000>,
 305                         <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
 306                         <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
 307                         <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
 308                         <&pclk_peri_pre 75000000>, <&clk_gpu 300000000>,
 309                         <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
 310                         <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
 311                         <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
 312                         <&clk_mac_ref 125000000>;
 313         /*      rockchip,clocks-uboot-has-init =
 314                         <&aclk_vio1>;*/
 315         };
 316         gpu {
 317                 compatible = "arm,mali400";
 318                 reg = <0x10091000 0x200>,
 319                       <0x10090000 0x100>,
 320                       <0x10093000 0x100>,
 321                       <0x10098000 0x1100>,
 322                       <0x10094000 0x100>,
 323                       <0x1009A000 0x1100>,
 324                       <0x10095000 0x100>;
 325
 326                 reg-names = "Mali_L2",
 327                             "Mali_GP",
 328                             "Mali_GP_MMU",
 329                             "Mali_PP0",
 330                             "Mali_PP0_MMU",
 331                             "Mali_PP1",
 332                             "Mali_PP1_MMU";
 333
 334                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 335                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 336                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 337                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 338                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 339                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 340
 341                 interrupt-names = "Mali_GP_IRQ",
 342                                   "Mali_GP_MMU_IRQ",
 343                                   "Mali_PP0_IRQ",
 344                                   "Mali_PP0_MMU_IRQ",
 345                                   "Mali_PP1_IRQ",
 346                                   "Mali_PP1_MMU_IRQ";
 347           };
 348
 349         clocks-enable {
 350                 compatible = "rockchip,clocks-enable";
 351                 clocks =
 352                                 /*PD_CORE*/
 353                                 <&clk_gates0 6>,<&clk_gates0 0>,
 354                                 <&clk_gates0 7>,
 355
 356                                 /*PD_CPU*/
 357                                 <&clk_gates0 1>, <&clk_gates0 3>,
 358                                 <&clk_gates0 4>, <&clk_gates0 5>,
 359                                 <&clk_gates0 12>,
 360
 361                                 /*TIMER*/
 362                                 <&clk_gates10 3>, <&clk_gates10 4>,
 363                                 <&clk_gates10 5>, <&clk_gates10 6>,
 364                                 <&clk_gates10 7>, <&clk_gates10 8>,
 365
 366                                 /*PD_PERI*/
 367                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 368                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 369
 370                                 /*aclk_cpu_pre*/
 371                                 <&clk_gates4 12>,/*aclk_intmem*/
 372                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 373
 374                                 /*hclk_cpu_pre*/
 375                                 //<&clk_gates5 6>,/*hclk_rom*/
 376                                 <&clk_gates3 5>,/*hclk_crypto*/
 377
 378                                 /*pclk_cpu_pre*/
 379                                 <&clk_gates5 4>,/*pclk_grf*/
 380                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 381                                 //<&clk_gates5 14>,/*pclk_acodec*/
 382                                 //<&clk_gates3 8>,/*pclk_hdmi*/
 383
 384                                 /*aclk_peri_pre*/
 385                                 //<&clk_gates10 10>,/*aclk_gmac*/
 386                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 387                                 //<&clk_gates5 1>,/*aclk_dmac2*/
 388                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 389                                 <&clk_gates9 2>,/*g_pclk_pmu*/
 390                                 <&clk_gates9 3>,/*g_pclk_pmu_noc*/
 391                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 392
 393                                 /*hclk_peri_pre*/
 394                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 395                                 //<&clk_gates9 13>,/*hclk_usb_peri*/
 396                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 397
 398                                 /*pclk_peri_pre*/
 399                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 400
 401                                 /*hclk_vio_pre*/
 402                                 //<&clk_gates6 12>,/*hclk_vio_niu*/
 403                                 //<&clk_gates6 1>,/*hclk_lcdc*/
 404
 405                                 /*aclk_vio0_pre*/
 406                                 //<&clk_gates6 13>,/*aclk_vio*/
 407                                 //<&clk_gates6 0>,/*aclk_lcdc*/
 408
 409                                 /*aclk_vio1_pre*/
 410                                 //<&clk_gates9 10>,/*aclk_vio1_niu*/
 411
 412                                 /*UART*/
 413                                 <&clk_gates1 12>,
 414                                 <&clk_gates1 13>,
 415                                 <&clk_gates8 2>,/*pclk_uart2*/
 416
 417                                 //<&clk_gpu>,
 418
 419                                 /*jtag*/
 420                                 //<&clk_gates1 3>,/*clk_jtag*/
 421
 422                                 /*pmu*/
 423                                 <&clk_gates1 0>;/*pclk_pmu_pre*/
 424         };
 425
 426         i2c0: i2c@20072000 {
 427                 compatible = "rockchip,rk30-i2c";
 428                 reg = <0x20072000 0x1000>;
 429                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 pinctrl-names = "default", "gpio";
 433                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 434                 pinctrl-1 = <&i2c0_gpio>;
 435                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 436                 clocks = <&clk_gates8 4>;
 437                 rockchip,check-idle = <1>;
 438                 status = "disabled";
 439         };
 440
 441         i2c1: i2c@20056000 {
 442                 compatible = "rockchip,rk30-i2c";
 443                 reg = <0x20056000 0x1000>;
 444                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 pinctrl-names = "default", "gpio";
 448                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 449                 pinctrl-1 = <&i2c1_gpio>;
 450                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 451                 clocks = <&clk_gates8 5>;
 452                 rockchip,check-idle = <1>;
 453                 status = "disabled";
 454         };
 455
 456         i2c2: i2c@2005a000 {
 457                 compatible = "rockchip,rk30-i2c";
 458                 reg = <0x2005a000 0x1000>;
 459                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 pinctrl-names = "default", "gpio";
 463                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 464                 pinctrl-1 = <&i2c2_gpio>;
 465                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 466                 clocks = <&clk_gates8 6>;
 467                 rockchip,check-idle = <1>;
 468                 status = "disabled";
 469         };
 470
 471         i2c3: i2c@2005e000 {
 472                 compatible = "rockchip,rk30-i2c";
 473                 reg = <0x2005e000 0x1000>;
 474                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 pinctrl-names = "default", "gpio";
 478                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 479                 pinctrl-1 = <&i2c3_gpio>;
 480                 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
 481                 clocks = <&clk_gates8 7>;
 482                 rockchip,check-idle = <1>;
 483                 status = "disabled";
 484         };
 485
 486         i2s0: i2s0@10220000 {
 487                 compatible = "rockchip-i2s";
 488                 reg = <0x10220000 0x1000>;
 489                 i2s-id = <0>;
 490                 clocks = <&clk_i2s_2ch>, <&clk_i2s_2ch_out>, <&clk_gates7 2>;
 491                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 492                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 493                 dmas = <&pdma 0>, <&pdma 1>;
 494                 //#dma-cells = <2>;
 495                 dma-names = "tx", "rx";
 496                 //pinctrl-names = "default", "sleep";
 497                 //pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 498                 //pinctrl-1 = <&i2s0_gpio>;
 499                 status = "disabled";
 500         };
 501
 502         i2s1: i2s1@10200000 {
 503                 compatible = "rockchip-i2s";
 504                 reg = <0x10200000 0x1000>;
 505                 i2s-id = <1>;
 506                 clocks = <&clk_i2s_8ch>, <&clk_gates7 4>;
 507                 clock-names = "i2s_clk", "i2s_hclk";
 508                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 509                 dmas = <&pdma 14>, <&pdma 15>;
 510                 //#dma-cells = <2>;
 511                 dma-names = "tx", "rx";
 512         };
 513
 514         spdif: spdif@10204000 {
 515                 compatible = "rockchip-spdif";
 516                 reg = <0x10204000 0x1000>;
 517                 clocks = <&clk_spdif>, <&clk_gates10 9>;
 518                 clock-names = "spdif_mclk", "spdif_hclk";
 519                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 520                 dmas = <&pdma 13>;
 521                 //#dma-cells = <1>;
 522                 dma-names = "tx";
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&spdif_tx>;
 525         };
 526
 527         dsihost0: mipi@10110000{
 528                 compatible = "rockchip,rk312x-dsi";
 529                 rockchip,prop = <0>;
 530                 reg = <0x10110000 0x4000>, <0x20038000 0x4000>;
 531                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 532                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 533                 clocks = <&clk_gates2 15>, <&clk_gates5 0>, <&clk_gates9 6>, <&clk_gates9 5>, <&pd_mipidsi>;
 534                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "hclk_vio_h2p", "pd_mipi_dsi";
 535                 status = "okay";
 536         };
 537
 538         emmc: rksdmmc@1021c000 {
 539                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 540                 reg = <0x1021c000 0x4000>;
 541                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 //pinctrl-names = "default",,"suspend";
 545                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 546                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 547                 clock-names = "clk_mmc", "hclk_mmc";
 548                 dmas = <&pdma 12>;
 549                 dma-names = "dw_mci";
 550                 num-slots = <1>;
 551                 fifo-depth = <0x100>;
 552                 bus-width = <8>;
 553                 cru_regsbase = <0x124>;
 554                 cru_reset_offset = <3>;
 555         };
 556
 557
 558         sdmmc: rksdmmc@10214000 {
 559                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 560                 reg = <0x10214000 0x4000>;
 561                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 562                 #address-cells = <1>;
 563                 #size-cells = <0>;
 564                 pinctrl-names = "default", "idle", "udbg";
 565                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd  &sdmmc0_dectn &sdmmc0_bus4>;
 566                 pinctrl-1 = <&sdmmc0_gpio>;
 567                 pinctrl-2 = <&uart2_xfer &sdmmc0_dectn>;
 568                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 569                 clock-names = "clk_mmc", "hclk_mmc";
 570                 dmas = <&pdma 10>;
 571                 dma-names = "dw_mci";
 572                 num-slots = <1>;
 573                 fifo-depth = <0x100>;
 574                 bus-width = <4>;
 575                 cru_regsbase = <0x124>;
 576                 cru_reset_offset = <1>;
 577         };
 578
 579         sdio: rksdmmc@10218000 {
 580                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 581                 reg = <0x10218000 0x4000>;
 582                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 583                 #address-cells = <1>;
 584                 #size-cells = <0>;
 585                 pinctrl-names = "default","idle";
 586                 pinctrl-0 = <&sdio0_pwren &sdio0_cmd &sdio0_clk &sdio0_bus4>;
 587                 pinctrl-1 = <&sdio0_gpio>;
 588                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 589                 clock-names = "clk_mmc", "hclk_mmc";
 590                 dmas = <&pdma 11>;
 591                 dma-names = "dw_mci";
 592                 num-slots = <1>;
 593                 fifo-depth = <0x100>;
 594                 bus-width = <4>;
 595                 cru_regsbase = <0x124>;
 596                 cru_reset_offset = <2>;
 597         };
 598
 599         spi0: spi@20074000 {
 600                 compatible = "rockchip,rockchip-spi";
 601                 reg = <0x20074000 0x1000>;
 602                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 603                 #address-cells = <1>;
 604                 #size-cells = <0>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
 607                 //pinctrl-0 = <&spi0_txd_mux1 &spi0_rxd_mux1 &spi0_clk_mux1 &spi0_cs0_mux1 &spi0_cs1_mux1>;
 608                 //pinctrl-0 = <&spi0_txd_mux2 &spi0_rxd_mux2 &spi0_clk_mux2 &spi0_cs0_mux2>;
 609                 rockchip,spi-src-clk = <0>;
 610                 num-cs = <2>;
 611                 clocks =<&clk_spi0>, <&clk_gates7 12>;
 612                 clock-names = "spi","pclk_spi0";
 613                 dmas = <&pdma 8>, <&pdma 9>;
 614                 #dma-cells = <2>;
 615                 dma-names = "tx", "rx";
 616                 status = "disabled";
 617         };
 618
 619         adc: adc@2006c000 {
 620                 compatible = "rockchip,saradc";
 621                 reg = <0x2006c000 0x100>;
 622                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 623                 #io-channel-cells = <1>;
 624                 io-channel-ranges;
 625                 rockchip,adc-vref = <1800>;
 626                 clock-frequency = <1000000>;
 627                 clocks = <&clk_saradc>, <&clk_gates7 14>;
 628                 clock-names = "saradc", "pclk_saradc";
 629                 status = "disabled";
 630         };
 631
 632         pwm0: pwm@20050000 {
 633                 compatible = "rockchip,rk-pwm";
 634                 reg = <0x20050000 0x10>;
 635                 #pwm-cells = <2>;
 636                 pinctrl-names = "default";
 637                 pinctrl-0 = <&pwm0_pin>;
 638                 clocks = <&clk_gates7 10>;
 639                 clock-names = "pclk_pwm";
 640                 status = "disabled";
 641         };
 642
 643         pwm1: pwm@20050010 {
 644                 compatible = "rockchip,rk-pwm";
 645                 reg = <0x20050010 0x10>;
 646                 #pwm-cells = <2>;
 647                 pinctrl-names = "default";
 648                 pinctrl-0 = <&pwm1_pin>;
 649                 clocks = <&clk_gates7 10>;
 650                 clock-names = "pclk_pwm";
 651                 status = "disabled";
 652         };
 653
 654         pwm2: pwm@20050020 {
 655                 compatible = "rockchip,rk-pwm";
 656                 reg = <0x20050020 0x10>;
 657                 #pwm-cells = <2>;
 658                 pinctrl-names = "default";
 659                 pinctrl-0 = <&pwm2_pin>;
 660                 clocks = <&clk_gates7 10>;
 661                 clock-names = "pclk_pwm";
 662                 status = "disabled";
 663         };
 664
 665         pwm3: pwm@20050030 {
 666                 compatible = "rockchip,rk-pwm";
 667                 reg = <0x20050030 0x10>;
 668                 #pwm-cells = <2>;
 669                 pinctrl-names = "default";
 670                 pinctrl-0 = <&pwm3_pin>;
 671                 clocks = <&clk_gates7 10>;
 672                 clock-names = "pclk_pwm";
 673                 status = "disabled";
 674         };
 675
 676         remotectl: pwm@20050030 {
 677                 compatible = "rockchip,remotectl-pwm";
 678                 reg = <0x20050030 0x10>;
 679                 #pwm-cells = <2>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&pwm3_pin>;
 682                 clocks = <&clk_gates7 10>;
 683                 clock-names = "pclk_pwm";
 684                 remote_pwm_id = <3>;
 685                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 686                 status = "okay";
 687         };
 688         dwc_control_usb: dwc-control-usb@20008000 {
 689                 compatible = "rockchip,rk3126-dwc-control-usb";
 690                 reg = <0x20008000 0x4>;
 691                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 692                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 693                              <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 694                 interrupt-names = "otg_bvalid",
 695                                   "otg0_linestate",
 696                                   "otg1_linestate";
 697                 clocks = <&clk_gates9 13>;
 698                 clock-names = "hclk_usb_peri";
 699                 rockchip,remote_wakeup;
 700                 rockchip,usb_irq_wakeup;
 701                 resets = <&reset RK3128_RST_USBPOR>;
 702                 reset-names = "usbphy_por";
 703                 usb_bc{
 704                         compatible = "inno,phy";
 705                         regbase = &dwc_control_usb;
 706                         rk_usb,bvalid     = <0x14c  5 1>;
 707                         rk_usb,iddig      = <0x14c  8 1>;
 708                         rk_usb,vdmsrcen   = <0x184 12 1>;
 709                         rk_usb,vdpsrcen   = <0x184 11 1>;
 710                         rk_usb,rdmpden    = <0x184 10 1>;
 711                         rk_usb,idpsrcen   = <0x184  9 1>;
 712                         rk_usb,idmsinken  = <0x184  8 1>;
 713                         rk_usb,idpsinken  = <0x184  7 1>;
 714                         rk_usb,dpattach   = <0x2c0  7 1>;
 715                         rk_usb,cpdet      = <0x2c0  6 1>;
 716                         rk_usb,dcpattach  = <0x2c0  5 1>;
 717                 };
 718         };
 719
 720         usb0: usb@10180000 {
 721                 compatible = "rockchip,rk3126_usb20_otg";
 722                 reg = <0x10180000 0x40000>;
 723                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 724                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 725                 clock-names = "clk_usbphy0", "hclk_usb0";
 726                 resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_UTMI0>,
 727                                 <&reset RK3128_RST_OTGC0>;
 728                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 729                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 730                 rockchip,usb-mode = <0>;
 731         };
 732
 733         ehci: usb@101c0000 {
 734                 compatible = "rockchip,rk3126_ehci";
 735                 reg = <0x101c0000 0x20000>;
 736                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 737                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 738                 clock-names = "clk_usbphy1", "hclk_host0";
 739                 resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
 740                                 <&reset RK3128_RST_OTGC1>;
 741                 reset-names = "host_ahb", "host_phy", "host_controller";
 742         };
 743
 744         ohci: usb@101e0000 {
 745                 compatible = "rockchip,rk3126_ohci";
 746                 reg = <0x101e0000 0x20000>;
 747                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 748         };
 749
 750         fb: fb{
 751                 compatible = "rockchip,rk-fb";
 752                 rockchip,disp-mode = <ONE_DUAL>;
 753         };
 754
 755         rk_screen: rk_screen{
 756                 compatible = "rockchip,screen";
 757         };
 758
 759         lvds: lvds@20038000 {
 760                 compatible = "rockchip,rk31xx-lvds";
 761                 reg = <0x20038000 0x4000>, <0x101100b0 0x01>;
 762                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 763                 clocks = <&clk_gates5 0>, <&clk_gates9 6>, <&clk_gates9 5>;
 764                 clock-names = "pclk_lvds", "pclk_lvds_ctl", "hclk_vio_h2p";
 765                 status = "disabled";
 766         };
 767
 768         lcdc: lcdc@1010e000 {
 769                 compatible = "rockchip,rk312x-lcdc";
 770                 rockchip,prop = <PRMRY>;
 771                 reg = <0x1010e000 0x1000>;
 772                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 773                 clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>, <&pd_vop>, <&clk_cpll>;
 774                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_lcdc", "pd_lcdc", "sclk_pll";
 775                 rockchip,iommu-enabled = <1>;
 776                 status = "disabled";
 777         };
 778
 779         hdmi: hdmi@20034000 {
 780                 compatible = "rockchip,rk312x-hdmi";
 781                 reg = <0x20034000 0x4000>;
 782                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 783                 rockchip,hdmi_lcdc_source = <0>;
 784                 pinctrl-names = "default", "gpio";
 785                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 786                 pinctrl-1 = <&hdmi_gpio>;
 787                 clocks = <&clk_gates3 8>, <&pd_hdmi>;
 788                 clock-names = "pclk_hdmi", "pd_hdmi";
 789                 rockchip,hdcp_enable = <0>;
 790                 rockchip,cec_enable = <0>;
 791                 status = "disabled";
 792         };
 793
 794         tve: tve{
 795                 compatible = "rockchip,rk312x-tve";
 796                 reg = <0x1010e200 0x100>;
 797                 saturation = <0x002b4d3c>;
 798                 brightcontrast = <0x00007700>;
 799                 adjtiming = <0xa6c00880>;
 800                 lumafilter0 = <0x02ff0000>;
 801                 lumafilter1 = <0xf40202fd>;
 802                 lumafilter2 = <0xf332d919>;
 803                 daclevel = <0x3a>;
 804                 status = "disabled";
 805         };
 806
 807         vpu: vpu_service {
 808                 compatible = "rockchip,vpu_sub";
 809                 iommu_enabled = <1>;
 810                 reg = <0x10106000 0x800>;
 811                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 812                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 813                 interrupt-names = "irq_enc", "irq_dec";
 814                 dev_mode = <0>;
 815                 name = "vpu_service";
 816         };
 817
 818         hevc: hevc_service {
 819                 compatible = "rockchip,hevc_sub";
 820                 iommu_enabled = <1>;
 821                 reg = <0x10104000 0x400>;
 822                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 823                 interrupt-names = "irq_dec";
 824                 dev_mode = <1>;
 825                 name = "hevc_service";
 826         };
 827
 828         vpu_combo: vpu_combo@ff9a0000 {
 829                 compatible = "rockchip,vpu_combo";
 830                 subcnt = <2>;
 831                 rockchip,sub = <&vpu>, <&hevc>;
 832                 clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
 833                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 834                 resets = <&reset RK3128_RST_VCODEC_H>, <&reset RK3128_RST_VCODEC_A>,
 835                         <&reset RK3128_RST_HEVC>;
 836                 reset-names = "video_h", "video_a", "video";
 837                 mode_bit = <15>;
 838                 mode_ctrl = <0x144>;
 839                 name = "vpu_combo";
 840                 status = "okay";
 841         };
 842
 843         iep: iep@10108000 {
 844                 compatible = "rockchip,iep";
 845                 iommu_enabled = <1>;
 846                 reg = <0x10108000 0x800>;
 847                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 848                 clocks = <&clk_gates9 8>, <&clk_gates9 7>;
 849                 clock-names = "aclk_iep", "hclk_iep";
 850                 version = <1>;
 851                 status = "okay";
 852         };
 853
 854         rga: rga@1010c000 {
 855                 compatible = "rockchip,rk312x-rga";
 856                 reg = <0x1010c000 0x1000>;
 857                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 858                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 859                 clock-names = "hclk_rga", "aclk_rga";
 860                 status = "okay";
 861         };
 862
 863   vop_mmu {
 864                 dbgname = "vop";
 865                 compatible = "rockchip,vop_mmu";
 866                 reg = <0x1010e300 0x100>;
 867                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 868                 interrupt-names = "vop_mmu";
 869           };
 870
 871           hevc_mmu {
 872                 dbgname = "hevc";
 873                 compatible = "rockchip,hevc_mmu";
 874                 reg = <0x10104440 0x40>,
 875                       <0x10104480 0x40>;
 876                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 877                 interrupt-names = "hevc_mmu";
 878           };
 879
 880           vpu_mmu {
 881                 dbgname = "vpu";
 882                 compatible = "rockchip,vpu_mmu";
 883                 reg = <0x10106800 0x100>;
 884                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 885                 interrupt-names = "vpu_mmu";
 886           };
 887
 888           iep_mmu {
 889                 dbgname = "iep";
 890                 compatible = "rockchip,iep_mmu";
 891                 reg = <0x10108800 0x100>;
 892                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 893                 interrupt-names = "iep_mmu";
 894           };
 895
 896           dvfs {
 897                 vd_arm: vd_arm {
 898                         regulator_name = "vdd_arm";
 899                         pd_core {
 900                                 clk_core_dvfs_table: clk_core {
 901                                         operating-points = <
 902                                                 /* KHz    uV */
 903                                                 312000 1100000
 904                                                 504000 1100000
 905                                                 816000 1100000
 906                                                 1008000 1100000
 907                                                 >;
 908                                         temp-limit-enable = <0>;
 909                                         target-temp = <80>;
 910                                         temp-channel = <1>;
 911                                         normal-temp-limit = <
 912                                         /*delta-temp    delta-freq*/
 913                                                 3       96000
 914                                                 6       144000
 915                                                 9       192000
 916                                                 15      384000
 917                                                 >;
 918                                         performance-temp-limit = <
 919                                                 /*temp    freq*/
 920                                                 110     816000
 921                                                 >;
 922                                         status = "okay";
 923                                         regu-mode-table = <
 924                                                 /*freq     mode*/
 925                                                 1008000    4
 926                                                 0          3
 927                                         >;
 928                                         regu-mode-en = <0>;
 929                                         lkg_adjust_volt_en = <1>;
 930                                         channel = <0>;
 931                                         def_table_lkg = <35>;
 932                                         min_adjust_freq = <1200000>;
 933                                         lkg_adjust_volt_table = <
 934                                                 /*lkg(mA)  volt(uV)*/
 935                                                 60         25000
 936                                                 >;
 937                                 };
 938                         };
 939                 };
 940
 941                 vd_logic: vd_logic {
 942                         regulator_name = "vdd_logic";
 943                         pd_ddr {
 944                                 clk_ddr_dvfs_table: clk_ddr {
 945                                         operating-points = <
 946                                                 /* KHz    uV */
 947                                                 200000 1200000
 948                                                 300000 1200000
 949                                                 400000 1200000
 950                                                 >;
 951                                         status = "disabled";
 952                                 };
 953                         };
 954
 955                         pd_gpu {
 956                                 clk_gpu_dvfs_table: clk_gpu {
 957                                         operating-points = <
 958                                                 /* KHz    uV */
 959                                                 200000 1200000
 960                                                 300000 1200000
 961                                                 400000 1200000
 962                                                 >;
 963                                         status = "okay";
 964                                         regu-mode-table = <
 965                                                 /*freq     mode*/
 966                                                 200000     4
 967                                                 0          3
 968                                         >;
 969                                         regu-mode-en = <0>;
 970                                 };
 971                         };
 972                 };
 973         };
 974         ion {
 975                 compatible = "rockchip,ion";
 976                 #address-cells = <1>;
 977                 #size-cells = <0>;
 978
 979                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
 980                         compatible = "rockchip,ion-heap";
 981                         rockchip,ion_heap = <4>;
 982                         reg = <0x00000000 0x800000>; /* 8MB */
 983                 };
 984                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
 985                         compatible = "rockchip,ion-heap";
 986                         rockchip,ion_heap = <0>;
 987                 };
 988         };
 989         cif: cif@1010a000 {
 990              compatible = "rockchip,cif";
 991              reg = <0x1010a000 0x2000>;
 992              interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 993              clocks = <&pd_vip>,<&clk_gates6 5>,<&clk_gates6 4>,<&clk_cif0_in>,<&clk_cif_out>;
 994              clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
 995              status = "okay";
 996              };
 997
 998         codec_hdmi_spdif: codec-hdmi-spdif {
 999                 compatible = "hdmi-spdif";
1000         };
1001
1002         rockchip-hdmi-spdif {
1003                 compatible = "rockchip-hdmi-spdif";
1004                 dais {
1005                         dai0 {
1006                                 audio-codec = <&codec_hdmi_spdif>;
1007                                 audio-controller = <&spdif>;
1008                         };
1009                 };
1010         };
1011         codec: codec@20030000 {
1012                 compatible = "rk312x-codec";
1013                 reg = <0x20030000 0x4000>;
1014                 //pinctrl-names = "default";
1015                 //pinctrl-0 = <&i2s_gpio>;
1016                 boot_depop = <1>;
1017                 pa_enable_time = <1000>;
1018                 clocks = <&clk_gates5 14>;
1019                 clock-names = "g_pclk_acodec";
1020         };
1021         rockchip_audio: audio-rk312x {
1022                 compatible = "audio-rk312x";
1023                 dais {
1024                         dai0 {
1025                                 audio-codec = <&codec>;
1026                                 audio-controller = <&i2s1>;
1027                                 format = "i2s";
1028                                 //continuous-clock;
1029                                 //bitclock-inversion;
1030                                 //frame-inversion;
1031                                 //bitclock-master;
1032                                 //frame-master;
1033                         };
1034                         dai1 {
1035                                 audio-codec = <&codec>;
1036                                 audio-controller = <&i2s1>;
1037                                 format = "i2s";
1038                                 //continuous-clock;
1039                                 //bitclock-inversion;
1040                                 //frame-inversion;
1041                                 //bitclock-master;
1042                                 //frame-master;
1043                         };
1044                 };
1045         };
1046 };