arch/arm/boot/dts/rk312x.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/sensor-dev.h>
   4 #include <dt-bindings/clock/rk_system_status.h>
   5 #include <dt-bindings/rkfb/rk_fb.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk312x-clocks.dtsi"
   9 #include "rk312x-pinctrl.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk312x";
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18                 serial1 = &uart1;
  19                 serial2 = &uart2;
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 i2c3 = &i2c3;
  24                 lcdc = &lcdc;
  25         //      spi0 = &spi0;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a7";
  35                         reg = <0xf00>;
  36                 };
  37                 cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0xf01>;
  41                 };
  42                 cpu@2 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a7";
  45                         reg = <0xf02>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a7";
  50                         reg = <0xf03>;
  51                 };
  52         };
  53
  54         gic: interrupt-controller@10139000 {
  55                 compatible = "arm,cortex-a15-gic";
  56                 interrupt-controller;
  57                 #interrupt-cells = <3>;
  58                 #address-cells = <0>;
  59                 reg = <0x10139000 0x1000>,
  60                       <0x1013a000 0x1000>;
  61         };
  62
  63         arm-pmu {
  64                 compatible = "arm,cortex-a7-pmu";
  65                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  66                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  67                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  68                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  69         };
  70
  71         sram: sram@10080000 {
  72                 compatible = "mmio-sram";
  73                 reg = <0x10080000 0x2000>;
  74                 map-exec;
  75         };
  76
  77         timer {
  78                 compatible = "arm,armv7-timer";
  79                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  80                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  81                 clock-frequency = <24000000>;
  82         };
  83
  84         timer@20044000 {
  85                 compatible = "rockchip,timer";
  86                 reg = <0x20044000 0x20>;
  87                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  88                 rockchip,broadcast = <1>;
  89         };
  90
  91         watchdog: wdt@2004c000 {
  92                 compatible = "rockchip,watch dog";
  93                 reg = <0x2004c000 0x100>;
  94         //      clocks = <&clk_gates7 15>;
  95                 clock-names = "pclk_wdt";
  96                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  97                 rockchip,irq = <1>;
  98                 rockchip,timeout = <60>;
  99                 rockchip,atboot = <1>;
 100                 rockchip,debug = <0>;
 101                 status = "disabled";
 102         };
 103
 104         amba {
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 compatible = "arm,amba-bus";
 108                 interrupt-parent = <&gic>;
 109                 ranges;
 110
 111                 pdma: pdma@20078000 {
 112                         compatible = "arm,pl330", "arm,primecell";
 113                         reg = <0x20078000 0x4000>;
 114                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 115                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 116                         #dma-cells = <1>;
 117                 };
 118         };
 119
 120         reset: reset@20000110 {
 121                 compatible = "rockchip,reset";
 122                 reg = <0x20000110 0x24>;
 123                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 124                 #reset-cells = <1>;
 125         };
 126
 127         nandc: nandc@10500000 {
 128                 compatible = "rockchip,rk-nandc";
 129                 reg = <0x10500000 0x4000>;
 130                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 131                 //pinctrl-names = "default";
 132                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 133                 nandc_id = <0>;
 134                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 15>;
 135                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 136         };
 137
 138         nandc0reg: nandc0@10500000 {
 139                 compatible = "rockchip,rk-nandc";
 140                 reg = <0x10500000 0x4000>;
 141         };
 142         uart0: serial@20060000 {
 143                 compatible = "rockchip,serial";
 144                 reg = <0x20060000 0x100>;
 145                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 146                 clock-frequency = <24000000>;
 147                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 148                 clock-names = "sclk_uart", "pclk_uart";
 149                 reg-shift = <2>;
 150                 reg-io-width = <4>;
 151                 dmas = <&pdma 2>, <&pdma 3>;
 152                 #dma-cells = <2>;
 153                 pinctrl-names = "default";
 154                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 155                 status = "disabled";
 156         };
 157
 158         uart1: serial@20064000 {
 159                 compatible = "rockchip,serial";
 160                 reg = <0x20064000 0x100>;
 161                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 162                 clock-frequency = <24000000>;
 163                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 164                 clock-names = "sclk_uart", "pclk_uart";
 165                 reg-shift = <2>;
 166                 reg-io-width = <4>;
 167                 dmas = <&pdma 4>, <&pdma 5>;
 168                 #dma-cells = <2>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 171                 status = "disabled";
 172         };
 173
 174         uart2: serial@20068000 {
 175                 compatible = "rockchip,serial";
 176                 reg = <0x20068000 0x100>;
 177                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 178                 clock-frequency = <24000000>;
 179                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 180                 clock-names = "sclk_uart", "pclk_uart";
 181                 reg-shift = <2>;
 182                 reg-io-width = <4>;
 183                 dmas = <&pdma 6>, <&pdma 7>;
 184                 #dma-cells = <2>;
 185                 pinctrl-names = "default";
 186                 pinctrl-0 = <&uart2_xfer>;
 187                 status = "disabled";
 188         };
 189
 190         fiq-debugger {
 191                 compatible = "rockchip,fiq-debugger";
 192                 rockchip,serial-id = <2>;
 193                 rockchip,signal-irq = <106>;
 194                 rockchip,wake-irq = <0>;
 195                 status = "disabled";
 196         };
 197
 198         clocks-init{
 199                 compatible = "rockchip,clocks-init";
 200                 rockchip,clocks-init-parent =
 201                         <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
 202                         <&aclk_peri &clk_gpll_div2>, <&clk_uart0_pll &clk_gpll>,
 203                         <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
 204                         <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 205                         <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
 206                         <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
 207                         <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
 208                         <&sclk_lcdc0 &clk_cpll>, <&clk_gpu_pre &clk_gpll_div2>,
 209                         <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
 210                         <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
 211                         <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
 212                         <&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
 213                         <&clk_mac_pll &clk_cpll>;
 214                 rockchip,clocks-init-rate =
 215                         <&clk_core 816000000>, <&clk_gpll 594000000>,
 216                         <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
 217                         <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
 218                         <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
 219                         <&pclk_peri_pre 75000000>, <&clk_gpu_pre 300000000>,
 220                         <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
 221                         <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
 222                         <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
 223                         <&clk_mac_ref 50000000>;
 224         /*      rockchip,clocks-uboot-has-init =
 225                         <&aclk_vio1>;*/
 226         };
 227         gpu {
 228                 compatible = "arm,mali400";
 229                 reg = <0x10091000 0x200>,
 230                       <0x10090000 0x100>,
 231                       <0x10093000 0x100>,
 232                       <0x10098000 0x1100>,
 233                       <0x10094000 0x100>,
 234                       <0x1009A000 0x1100>,
 235                       <0x10095000 0x100>;
 236
 237                 reg-names = "Mali_L2",
 238                             "Mali_GP",
 239                             "Mali_GP_MMU",
 240                             "Mali_PP0",
 241                             "Mali_PP0_MMU",
 242                             "Mali_PP1",
 243                             "Mali_PP1_MMU";
 244
 245                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 246                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 247                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 248                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 250                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 251
 252                 interrupt-names = "Mali_GP_IRQ",
 253                                   "Mali_GP_MMU_IRQ",
 254                                   "Mali_PP0_IRQ",
 255                                   "Mali_PP0_MMU_IRQ",
 256                                   "Mali_PP1_IRQ",
 257                                   "Mali_PP1_MMU_IRQ";
 258           };
 259
 260         clocks-enable {
 261                 compatible = "rockchip,clocks-enable";
 262                 clocks =
 263                                 /*PD_CORE*/
 264                                 <&clk_gates0 6>,<&clk_gates0 0>,
 265                                 <&clk_gates0 7>,
 266
 267                                 /*PD_CPU*/
 268                                 <&clk_gates0 1>, <&clk_gates0 3>,
 269                                 <&clk_gates0 4>, <&clk_gates0 5>,
 270                                 <&clk_gates0 12>,
 271
 272                                 /*TIMER*/
 273                                 <&clk_gates10 3>, <&clk_gates10 4>,
 274                                 <&clk_gates10 5>, <&clk_gates10 6>,
 275                                 <&clk_gates10 7>, <&clk_gates10 8>,
 276
 277                                 /*PD_PERI*/
 278                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 279                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 280
 281                                 /*aclk_cpu_pre*/
 282                                 <&clk_gates4 12>,/*aclk_intmem*/
 283                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 284
 285                                 /*hclk_cpu_pre*/
 286                                 <&clk_gates5 6>,/*hclk_rom*/
 287                                 <&clk_gates3 5>,/*hclk_crypto*/
 288
 289                                 /*pclk_cpu_pre*/
 290                                 <&clk_gates5 4>,/*pclk_grf*/
 291                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 292                                 <&clk_gates5 14>,/*pclk_acodec*/
 293                                 <&clk_gates3 8>,/*pclk_hdmi*/
 294
 295                                 /*aclk_peri_pre*/
 296                                 <&clk_gates10 10>,/*aclk_gmac*/
 297                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 298                                 <&clk_gates5 1>,/*aclk_dmac2*/
 299                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 300                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 301
 302                                 /*hclk_peri_pre*/
 303                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 304                                 <&clk_gates9 13>,/*hclk_usb_peri*/
 305                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 306
 307                                 /*pclk_peri_pre*/
 308                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 309
 310                                 /*hclk_vio_pre*/
 311                                 <&clk_gates6 12>,/*hclk_vio_niu*/
 312                                 <&clk_gates6 1>,/*hclk_lcdc*/
 313
 314                                 /*aclk_vio0_pre*/
 315                                 <&clk_gates6 13>,/*aclk_vio*/
 316                                 <&clk_gates6 0>,/*aclk_lcdc*/
 317
 318                                 /*aclk_vio1_pre*/
 319                                 <&clk_gates9 10>,/*aclk_vio1_niu*/
 320
 321                                 /*UART*/
 322                                 <&clk_gates1 12>,
 323                                 <&clk_gates1 13>,
 324                                 <&clk_gates8 2>,/*pclk_uart2*/
 325
 326                                 <&clk_gpu_pre>,
 327
 328                                 /*jtag*/
 329                                 <&clk_gates1 3>,/*clk_jtag*/
 330
 331                                 /*pmu*/
 332                                 <&clk_gates1 0>;/*pclk_pmu_pre*/
 333         };
 334
 335         i2c0: i2c@20070000 {
 336                 compatible = "rockchip,rk30-i2c";
 337                 reg = <0x20070000 0x1000>;
 338                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 pinctrl-names = "default", "gpio";
 342                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 343                 pinctrl-1 = <&i2c0_gpio>;
 344                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 345                 clocks = <&clk_gates8 4>;
 346                 rockchip,check-idle = <1>;
 347                 status = "disabled";
 348         };
 349
 350         i2c1: i2c@20054000 {
 351                 compatible = "rockchip,rk30-i2c";
 352                 reg = <0x20054000 0x1000>;
 353                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 pinctrl-names = "default", "gpio";
 357                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 358                 pinctrl-1 = <&i2c1_gpio>;
 359                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 360                 clocks = <&clk_gates8 5>;
 361                 rockchip,check-idle = <1>;
 362                 status = "disabled";
 363         };
 364
 365         i2c2: i2c@20058000 {
 366                 compatible = "rockchip,rk30-i2c";
 367                 reg = <0x20058000 0x1000>;
 368                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 pinctrl-names = "default", "gpio";
 372                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 373                 pinctrl-1 = <&i2c2_gpio>;
 374                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 375                 clocks = <&clk_gates8 6>;
 376                 rockchip,check-idle = <1>;
 377                 status = "disabled";
 378         };
 379
 380         i2c3: i2c@2005c000 {
 381                 compatible = "rockchip,rk30-i2c";
 382                 reg = <0x2005C000 0x1000>;
 383                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 pinctrl-names = "default", "gpio";
 387                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 388                 pinctrl-1 = <&i2c3_gpio>;
 389                 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
 390                 clocks = <&clk_gates8 7>;
 391                 rockchip,check-idle = <1>;
 392                 status = "disabled";
 393         };
 394
 395         i2s0: i2s@10220000 {
 396                 compatible = "rockchip-i2s";
 397                 reg = <0x10220000 0x1000>;
 398                 i2s-id = <0>;
 399                 clocks = <&clk_i2s_2ch>, <&clk_i2s_2ch_out>, <&clk_gates7 2>;
 400                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 401                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 402                 dmas = <&pdma 0>, <&pdma 1>;
 403                 //#dma-cells = <2>;
 404                 dma-names = "tx", "rx";
 405                 //pinctrl-names = "default", "sleep";
 406                 //pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 407                 //pinctrl-1 = <&i2s0_gpio>;
 408         };
 409
 410         i2s1: i2s@10200000 {
 411                 compatible = "rockchip-i2s";
 412                 reg = <0x10200000 0x1000>;
 413                 i2s-id = <1>;
 414                 clocks = <&clk_i2s_8ch>, <&clk_gates7 4>;
 415                 clock-names = "i2s_clk", "i2s_hclk";
 416                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 417                 dmas = <&pdma 14>, <&pdma 15>;
 418                 //#dma-cells = <2>;
 419                 dma-names = "tx", "rx";
 420         };
 421
 422         spdif: spdif@10204000 {
 423                 compatible = "rockchip-spdif";
 424                 reg = <0x10204000 0x1000>;
 425                 clocks = <&clk_spdif>, <&clk_gates10 8>;
 426                 clock-names = "spdif_8ch_mclk", "spdif_hclk";
 427                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 428                 dmas = <&pdma 13>;
 429                 //#dma-cells = <1>;
 430                 dma-names = "tx";
 431                 //pinctrl-names = "default";
 432                 //pinctrl-0 = <&spdif_tx>;
 433         };
 434
 435         dsihost0: mipi@10110000{
 436                 compatible = "rockchip,rk32-dsi";
 437                 rockchip,prop = <0>;
 438                 reg = <0x10110000 0x4000>, <0x20038000 0x4000>;
 439                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 440                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 441                 clocks = <&clk_gates2 15>, <&clk_gates5 0> ;//, <&pd_mipidsi>;
 442                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";//, "pd_mipi_dsi";
 443                 status = "okay";
 444         };
 445
 446         emmc: rksdmmc@1021c000 {
 447                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 448                 reg = <0x1021c000 0x4000>;
 449                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 450                 #address-cells = <1>;
 451                 #size-cells = <0>;
 452                 //pinctrl-names = "default",,"suspend";
 453                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 454                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 455                 clock-names = "clk_mmc", "hclk_mmc";
 456                 dmas = <&pdma 12>;
 457                 dma-names = "dw_mci";
 458                 num-slots = <1>;
 459                 fifo-depth = <0x100>;
 460                 bus-width = <8>;
 461         };
 462
 463
 464         sdmmc: rksdmmc@10214000 {
 465                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 466                 reg = <0x10214000 0x4000>;
 467                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 468                 #address-cells = <1>;
 469                 #size-cells = <0>;
 470                 pinctrl-names = "default", "idle";
 471                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 472                 pinctrl-1 = <&sdmmc0_gpio>;
 473                 //cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 474                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 475                 clock-names = "clk_mmc", "hclk_mmc";
 476                 dmas = <&pdma 10>;
 477                 dma-names = "dw_mci";
 478                 num-slots = <1>;
 479                 fifo-depth = <0x100>;
 480                 bus-width = <4>;
 481         };
 482
 483         sdio: rksdmmc@10218000 {
 484                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 485                 reg = <0x10218000 0x4000>;
 486                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 487                 #address-cells = <1>;
 488                 #size-cells = <0>;
 489                 pinctrl-names = "default","idle";
 490                 pinctrl-0 = <&sdio0_pwren &sdio0_cmd>;
 491                 pinctrl-1 = <&sdio0_gpio>;
 492                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 493                 clock-names = "clk_mmc", "hclk_mmc";
 494                 dmas = <&pdma 11>;
 495                 dma-names = "dw_mci";
 496                 num-slots = <1>;
 497                 fifo-depth = <0x100>;
 498                 bus-width = <4>;
 499         };
 500
 501         adc: adc@2006c000 {
 502                 compatible = "rockchip,saradc";
 503                 reg = <0x2006c000 0x100>;
 504                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 505                 #io-channel-cells = <1>;
 506                 io-channel-ranges;
 507                 rockchip,adc-vref = <1800>;
 508                 clock-frequency = <1000000>;
 509                 //clocks = <&clk_saradc>, <&clk_gates7 1>;
 510                 //clock-names = "saradc", "pclk_saradc";
 511                 status = "disabled";
 512         };
 513
 514         pwm0: pwm@20050000 {
 515                 compatible = "rockchip,rk-pwm";
 516                 reg = <0x20050000 0x10>;
 517                 #pwm-cells = <2>;
 518                 pinctrl-names = "default";
 519                 pinctrl-0 = <&pwm0_pin>;
 520                 clocks = <&clk_gates7 10>;
 521                 clock-names = "pclk_pwm";
 522                 status = "disabled";
 523         };
 524
 525         pwm1: pwm@20050010 {
 526                 compatible = "rockchip,rk-pwm";
 527                 reg = <0x20050010 0x10>;
 528                 #pwm-cells = <2>;
 529                 pinctrl-names = "default";
 530                 pinctrl-0 = <&pwm1_pin>;
 531                 clocks = <&clk_gates7 10>;
 532                 clock-names = "pclk_pwm";
 533                 status = "disabled";
 534         };
 535
 536         pwm2: pwm@20050020 {
 537                 compatible = "rockchip,rk-pwm";
 538                 reg = <0x20050020 0x10>;
 539                 #pwm-cells = <2>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&pwm2_pin>;
 542                 clocks = <&clk_gates7 10>;
 543                 clock-names = "pclk_pwm";
 544                 status = "disabled";
 545         };
 546
 547         pwm3: pwm@20050030 {
 548                 compatible = "rockchip,rk-pwm";
 549                 reg = <0x20050030 0x10>;
 550                 #pwm-cells = <2>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&pwm3_pin>;
 553                 clocks = <&clk_gates7 10>;
 554                 clock-names = "pclk_pwm";
 555                 status = "disabled";
 556         };
 557
 558         dwc_control_usb: dwc-control-usb@20008000 {
 559                 compatible = "rockchip,rk3126-dwc-control-usb";
 560                 reg = <0x20008000 0x4>;
 561                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 562                 interrupt-names = "otg_bvalid";
 563                 clocks = <&clk_gates9 13>;
 564                 clock-names = "hclk_usb_peri";
 565                 rockchip,remote_wakeup;
 566                 rockchip,usb_irq_wakeup;
 567                 resets = <&reset RK3128_RST_USBPOR>;
 568                 reset-names = "usbphy_por";
 569                 usb_bc{
 570                         compatible = "inno,phy";
 571                         regbase = &dwc_control_usb;
 572                 };
 573         };
 574
 575         usb0: usb@10180000 {
 576                 compatible = "rockchip,rk3126_usb20_otg";
 577                 reg = <0x10180000 0x40000>;
 578                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 579                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 580                 clock-names = "clk_usbphy0", "hclk_usb0";
 581                 resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_USBOTG0>,
 582                                 <&reset RK3128_RST_OTGC0>;
 583                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 584                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 585                 rockchip,usb-mode = <0>;
 586         };
 587
 588         usb1: usb@101c0000 {
 589                 compatible = "rockchip,rk3126_usb20_host";
 590                 reg = <0x101c0000 0x40000>;
 591                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 592                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 593                 clock-names = "clk_usbphy1", "hclk_usb1";
 594                 resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
 595                                 <&reset RK3128_RST_OTGC1>;
 596                 reset-names = "host_ahb", "host_phy", "host_controller";
 597         };
 598
 599         fb: fb{
 600                 compatible = "rockchip,rk-fb";
 601                 rockchip,disp-mode = <ONE_DUAL>;
 602         };
 603
 604         rk_screen: rk_screen{
 605                 compatible = "rockchip,screen";
 606         };
 607
 608         lvds: lvds@20038000 {
 609                 compatible = "rockchip,rk31xx-lvds";
 610                 reg = <0x20038000 0x4000>;
 611                 clocks = <&clk_gates5 0>;
 612                 clock-names = "pclk_lvds";
 613                 pinctrl-names = "lcdc", "sleep";
 614                 pinctrl-0 = <&lcdc0_lcdc_d>;
 615                 pinctrl-1 = <&lcdc0_lcdc_gpio>;
 616         };
 617
 618         lcdc: lcdc@1010e000 {
 619                 compatible = "rockchip,rk312x-lcdc";
 620                 rockchip,prop = <PRMRY>;
 621                 reg = <0x1010e000 0x2000>;
 622                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 623                 pinctrl-names = "default", "gpio";
 624                 pinctrl-0 = <&lcdc0_lcdc>;
 625                 pinctrl-1 = <&lcdc0_gpio>;
 626                 clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>;
 627                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk";
 628                 rockchip,iommu-enabled = <1>;
 629                 status = "disabled";
 630         };
 631
 632         hdmi: hdmi@20034000 {
 633                 compatible = "rockchip,rk312x-hdmi";
 634                 reg = <0x20034000 0x4000>;
 635                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 636                 rockchip,hdmi_lcdc_source = <0>;
 637                 pinctrl-names = "default", "gpio";
 638                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 639                 pinctrl-1 = <&hdmi_gpio>;
 640                 clocks = <&clk_gates3 8>;
 641                 clock-names = "pclk_hdmi";
 642                 status = "disabled";
 643         };
 644
 645         tve: tve{
 646                 compatible = "rockchip,rk312x-tve";
 647                 reg = <0x1011e200 0x100>;
 648                 status = "disabled";
 649         };
 650
 651         vpu: vpu_service@10104000 {
 652                 compatible = "vpu_service";
 653                 reg = <0x10104000 0x800>;
 654                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 655                 interrupt-names = "irq_enc", "irq_dec";
 656                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 657                 clock-names = "aclk_vcodec", "hclk_vcodec";
 658                 name = "vpu_service";
 659                 status = "disabled";
 660         };
 661
 662         hevc: hevc_service@10104000 {
 663                 compatible = "rockchip,hevc_service";
 664                 reg = <0x10104000 0x400>;
 665                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 666                 interrupt-names = "irq_dec";
 667                 clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
 668                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 669                 name = "hevc_service";
 670                 status = "disabled";
 671         };
 672
 673         iep: iep@10108000 {
 674                 compatible = "rockchip,iep";
 675                 reg = <0x10108000 0x800>;
 676                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 677                 clocks = <&clk_gates9 8>, <&clk_gates9 7>;
 678                 clock-names = "aclk_iep", "hclk_iep";
 679                 status = "okay";
 680         };
 681
 682         vop_mmu {
 683                 dbgname = "vop";
 684                 compatible = "iommu,vop_mmu";
 685                 reg = <0x1010e300 0x100>;
 686                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 687                 interrupt-names = "vop_mmu";
 688           };
 689
 690           hevc_mmu {
 691                 dbgname = "hevc";
 692                 compatible = "iommu,hevc_mmu";
 693                 reg = <0x10104440 0x100>,
 694                       <0x10104480 0x100>;
 695                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 696                 interrupt-names = "hevc_mmu";
 697           };
 698
 699           vpu_mmu {
 700                 dbgname = "vpu";
 701                 compatible = "iommu,vpu_mmu";
 702                 reg = <0x10104800 0x100>;
 703                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 704                 interrupt-names = "vpu_mmu";
 705           };
 706
 707           iep_mmu {
 708                 dbgname = "iep";
 709                 compatible = "iommu,iep_mmu";
 710                 reg = <0x10108800 0x100>;
 711                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 712                 interrupt-names = "iep_mmu";
 713           };
 714
 715           dvfs {
 716                 temp-limit-enable = <0>;
 717                 target-temp = <80>;
 718
 719                 vd_arm: vd_arm {
 720                         regulator_name = "vdd_arm";
 721                         pd_core {
 722                                 clk_core_dvfs_table: clk_core {
 723                                         operating-points = <
 724                                                 /* KHz    uV */
 725                                                 312000 1100000
 726                                                 504000 1100000
 727                                                 816000 1100000
 728                                                 1008000 1100000
 729                                                 >;
 730                                         temp-channel = <1>;
 731                                         normal-temp-limit = <
 732                                         /*delta-temp    delta-freq*/
 733                                                 3       96000
 734                                                 6       144000
 735                                                 9       192000
 736                                                 15      384000
 737                                                 >;
 738                                         performance-temp-limit = <
 739                                                 /*temp    freq*/
 740                                                 110     816000
 741                                                 >;
 742                                         status = "okay";
 743                                         regu-mode-table = <
 744                                                 /*freq     mode*/
 745                                                 1008000    4
 746                                                 0          3
 747                                         >;
 748                                         regu-mode-en = <0>;
 749                                 };
 750                         };
 751                 };
 752
 753                 vd_logic: vd_logic {
 754                         regulator_name = "vdd_logic";
 755                         pd_ddr {
 756                                 clk_ddr_dvfs_table: clk_ddr {
 757                                         operating-points = <
 758                                                 /* KHz    uV */
 759                                                 200000 1200000
 760                                                 300000 1200000
 761                                                 400000 1200000
 762                                                 >;
 763                                         status = "disabled";
 764                                 };
 765                         };
 766
 767                         pd_gpu {
 768                                 clk_gpu_dvfs_table: clk_gpu {
 769                                         operating-points = <
 770                                                 /* KHz    uV */
 771                                                 200000 1200000
 772                                                 300000 1200000
 773                                                 400000 1200000
 774                                                 >;
 775                                         status = "okay";
 776                                         regu-mode-table = <
 777                                                 /*freq     mode*/
 778                                                 200000     4
 779                                                 0          3
 780                                         >;
 781                                         regu-mode-en = <0>;
 782                                 };
 783                         };
 784                 };
 785         };
 786         ion {
 787                 compatible = "rockchip,ion";
 788                 #address-cells = <1>;
 789                 #size-cells = <0>;
 790
 791                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 792                         compatible = "rockchip,ion-reserve";
 793                         rockchip,ion_heap = <1>;
 794                         reg = <0x00000000 0x10000000>; /* 256MB */
 795                 };
 796                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 797                         rockchip,ion_heap = <3>;
 798                 };
 799         };
 800 };