arch/arm/boot/dts/rk312x.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/suspend/rockchip-pm.h>
   3 #include <dt-bindings/sensor-dev.h>
   4 #include <dt-bindings/clock/rk_system_status.h>
   5 #include <dt-bindings/rkfb/rk_fb.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk312x-clocks.dtsi"
   9 #include "rk312x-pinctrl.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk312x";
  13         rockchip,sram = <&sram>;
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18                 serial1 = &uart1;
  19                 serial2 = &uart2;
  20                 i2c0 = &i2c0;
  21                 i2c1 = &i2c1;
  22                 i2c2 = &i2c2;
  23                 i2c3 = &i2c3;
  24                 lcdc = &lcdc;
  25         //      spi0 = &spi0;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a7";
  35                         reg = <0xf00>;
  36                 };
  37                 cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0xf01>;
  41                 };
  42                 cpu@2 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a7";
  45                         reg = <0xf02>;
  46                 };
  47                 cpu@3 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a7";
  50                         reg = <0xf03>;
  51                 };
  52         };
  53
  54         gic: interrupt-controller@10139000 {
  55                 compatible = "arm,cortex-a15-gic";
  56                 interrupt-controller;
  57                 #interrupt-cells = <3>;
  58                 #address-cells = <0>;
  59                 reg = <0x10139000 0x1000>,
  60                       <0x1013a000 0x1000>;
  61         };
  62
  63         arm-pmu {
  64                 compatible = "arm,cortex-a7-pmu";
  65                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  66                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  67                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  68                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  69         };
  70
  71         sram: sram@10080000 {
  72                 compatible = "mmio-sram";
  73                 reg = <0x10080000 0x2000>;
  74                 map-exec;
  75         };
  76
  77         timer {
  78                 compatible = "arm,armv7-timer";
  79                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  80                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  81                 clock-frequency = <24000000>;
  82         };
  83
  84         timer@20044000 {
  85                 compatible = "rockchip,timer";
  86                 reg = <0x20044000 0x20>;
  87                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  88                 rockchip,broadcast = <1>;
  89         };
  90
  91         watchdog: wdt@2004c000 {
  92                 compatible = "rockchip,watch dog";
  93                 reg = <0x2004c000 0x100>;
  94         //      clocks = <&clk_gates7 15>;
  95                 clock-names = "pclk_wdt";
  96                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  97                 rockchip,irq = <1>;
  98                 rockchip,timeout = <60>;
  99                 rockchip,atboot = <1>;
 100                 rockchip,debug = <0>;
 101                 status = "disabled";
 102         };
 103
 104         amba {
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 compatible = "arm,amba-bus";
 108                 interrupt-parent = <&gic>;
 109                 ranges;
 110
 111                 pdma: pdma@20078000 {
 112                         compatible = "arm,pl330", "arm,primecell";
 113                         reg = <0x20078000 0x4000>;
 114                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 115                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 116                         #dma-cells = <1>;
 117                 };
 118         };
 119
 120         reset: reset@20000110 {
 121                 compatible = "rockchip,reset";
 122                 reg = <0x20000110 0x24>;
 123                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 124                 #reset-cells = <1>;
 125         };
 126
 127         nandc: nandc@10500000 {
 128                 compatible = "rockchip,rk-nandc";
 129                 reg = <0x10500000 0x4000>;
 130                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 131                 //pinctrl-names = "default";
 132                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 133                 nandc_id = <0>;
 134                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 15>;
 135                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 136         };
 137
 138         nandc0reg: nandc0@10500000 {
 139                 compatible = "rockchip,rk-nandc";
 140                 reg = <0x10500000 0x4000>;
 141         };
 142         uart0: serial@20060000 {
 143                 compatible = "rockchip,serial";
 144                 reg = <0x20060000 0x100>;
 145                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 146                 clock-frequency = <24000000>;
 147                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 148                 clock-names = "sclk_uart", "pclk_uart";
 149                 reg-shift = <2>;
 150                 reg-io-width = <4>;
 151                 dmas = <&pdma 2>, <&pdma 3>;
 152                 #dma-cells = <2>;
 153                 pinctrl-names = "default";
 154                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 155                 status = "disabled";
 156         };
 157
 158         uart1: serial@20064000 {
 159                 compatible = "rockchip,serial";
 160                 reg = <0x20064000 0x100>;
 161                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 162                 clock-frequency = <24000000>;
 163                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 164                 clock-names = "sclk_uart", "pclk_uart";
 165                 reg-shift = <2>;
 166                 reg-io-width = <4>;
 167                 dmas = <&pdma 4>, <&pdma 5>;
 168                 #dma-cells = <2>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 171                 status = "disabled";
 172         };
 173
 174         uart2: serial@20068000 {
 175                 compatible = "rockchip,serial";
 176                 reg = <0x20068000 0x100>;
 177                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 178                 clock-frequency = <24000000>;
 179                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 180                 clock-names = "sclk_uart", "pclk_uart";
 181                 reg-shift = <2>;
 182                 reg-io-width = <4>;
 183                 dmas = <&pdma 6>, <&pdma 7>;
 184                 #dma-cells = <2>;
 185                 pinctrl-names = "default";
 186                 pinctrl-0 = <&uart2_xfer>;
 187                 status = "disabled";
 188         };
 189
 190         gmac: eth@2008c000 {
 191                 compatible = "rockchip,gmac";
 192                 reg = <0x2008c000 0x4000>;
 193                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;  /*irq=88*/
 194                 interrupt-names = "macirq";
 195                 clocks = <&clk_mac_ref>, <&clk_gates2 6>,
 196                         <&clk_gates2 7>, <&clk_gates2 4>,
 197                         <&clk_gates2 5>,
 198                         <&clk_gates10 11>;
 199                 clock-names = "clk_mac", "mac_clk_rx",
 200                         "mac_clk_tx", "clk_mac_ref",
 201                         "clk_mac_refout",
 202                         "pclk_mac";
 203                 //phy-mode = "rmii";
 204                 phy-mode = "rgmii";
 205                 pinctrl-names = "default";
 206                 pinctrl-0 = <&gmac_rxdv &gmac_txclk &gmac_crs &gmac_rxclk &gmac_mdio &gmac_txen &gmac_clk &gmac_rxer &gmac_rxd1 &gmac_rxd0 &gmac_txd1 &gmac_txd0 &gmac_rxd3 &gmac_rxd2 &gmac_txd2 &gmac_txd3 &gmac_col_gpio &gmac_mdc>;
 207         };
 208
 209         fiq-debugger {
 210                 compatible = "rockchip,fiq-debugger";
 211                 rockchip,serial-id = <2>;
 212                 rockchip,signal-irq = <106>;
 213                 rockchip,wake-irq = <0>;
 214                 status = "disabled";
 215         };
 216
 217         clocks-init{
 218                 compatible = "rockchip,clocks-init";
 219                 rockchip,clocks-init-parent =
 220                         <&clk_core &clk_apll>, <&aclk_cpu &clk_gpll_div2>,
 221                         <&aclk_peri &clk_gpll_div2>, <&clk_uart0_pll &clk_gpll>,
 222                         <&clk_uart2_pll &clk_gpll>, <&clk_i2s_2ch_pll &clk_gpll>,
 223                         <&clk_i2s_8ch_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 224                         <&clk_vepu &clk_gpll_div2>, <&clk_vdpu &clk_gpll_div2>,
 225                         <&clk_hevc_core &clk_gpll>, <&aclk_vio0_pre &clk_gpll_div2>,
 226                         <&aclk_vio1_pre &clk_gpll_div2>, <&hclk_vio_pre &clk_gpll_div2>,
 227                         <&sclk_lcdc0 &clk_cpll>, <&clk_gpu &clk_gpll_div2>,
 228                         <&clk_cif_pll &clk_gpll_div2>, <&dclk_ebc &clk_gpll_div2>,
 229                         <&clk_emmc &clk_gpll_div2>, <&clk_sdio &clk_gpll_div2>,
 230                         <&clk_sfc &clk_gpll_div2>, <&clk_sdmmc0 &clk_gpll_div2>,
 231                         <&clk_tsp &clk_gpll_div2>, <&clk_nandc &clk_gpll_div2>,
 232                         <&clk_mac_pll &clk_cpll>;
 233                 rockchip,clocks-init-rate =
 234                         <&clk_core 816000000>, <&clk_gpll 594000000>,
 235                         <&clk_cpll 400000000>, <&aclk_cpu 300000000>,
 236                         <&hclk_cpu_pre 150000000>, <&pclk_cpu_pre 75000000>,
 237                         <&aclk_peri 300000000>, <&hclk_peri_pre 150000000>,
 238                         <&pclk_peri_pre 75000000>, <&clk_gpu 300000000>,
 239                         <&aclk_vio0_pre 300000000>, <&hclk_vio_pre 150000000>,
 240                         <&aclk_vio1_pre 300000000>, <&clk_vepu 300000000>,
 241                         <&clk_vdpu 300000000>, <&clk_hevc_core 200000000>,
 242                         <&clk_mac_ref 125000000>;
 243         /*      rockchip,clocks-uboot-has-init =
 244                         <&aclk_vio1>;*/
 245         };
 246         gpu {
 247                 compatible = "arm,mali400";
 248                 reg = <0x10091000 0x200>,
 249                       <0x10090000 0x100>,
 250                       <0x10093000 0x100>,
 251                       <0x10098000 0x1100>,
 252                       <0x10094000 0x100>,
 253                       <0x1009A000 0x1100>,
 254                       <0x10095000 0x100>;
 255
 256                 reg-names = "Mali_L2",
 257                             "Mali_GP",
 258                             "Mali_GP_MMU",
 259                             "Mali_PP0",
 260                             "Mali_PP0_MMU",
 261                             "Mali_PP1",
 262                             "Mali_PP1_MMU";
 263
 264                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 270
 271                 interrupt-names = "Mali_GP_IRQ",
 272                                   "Mali_GP_MMU_IRQ",
 273                                   "Mali_PP0_IRQ",
 274                                   "Mali_PP0_MMU_IRQ",
 275                                   "Mali_PP1_IRQ",
 276                                   "Mali_PP1_MMU_IRQ";
 277           };
 278
 279         clocks-enable {
 280                 compatible = "rockchip,clocks-enable";
 281                 clocks =
 282                                 /*PD_CORE*/
 283                                 <&clk_gates0 6>,<&clk_gates0 0>,
 284                                 <&clk_gates0 7>,
 285
 286                                 /*PD_CPU*/
 287                                 <&clk_gates0 1>, <&clk_gates0 3>,
 288                                 <&clk_gates0 4>, <&clk_gates0 5>,
 289                                 <&clk_gates0 12>,
 290
 291                                 /*TIMER*/
 292                                 <&clk_gates10 3>, <&clk_gates10 4>,
 293                                 <&clk_gates10 5>, <&clk_gates10 6>,
 294                                 <&clk_gates10 7>, <&clk_gates10 8>,
 295
 296                                 /*PD_PERI*/
 297                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 298                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 299
 300                                 /*aclk_cpu_pre*/
 301                                 <&clk_gates4 12>,/*aclk_intmem*/
 302                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 303
 304                                 /*hclk_cpu_pre*/
 305                                 <&clk_gates5 6>,/*hclk_rom*/
 306                                 <&clk_gates3 5>,/*hclk_crypto*/
 307
 308                                 /*pclk_cpu_pre*/
 309                                 <&clk_gates5 4>,/*pclk_grf*/
 310                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 311                                 <&clk_gates5 14>,/*pclk_acodec*/
 312                                 <&clk_gates3 8>,/*pclk_hdmi*/
 313
 314                                 /*aclk_peri_pre*/
 315                                 <&clk_gates10 10>,/*aclk_gmac*/
 316                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 317                                 <&clk_gates5 1>,/*aclk_dmac2*/
 318                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 319                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 320
 321                                 /*hclk_peri_pre*/
 322                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 323                                 <&clk_gates9 13>,/*hclk_usb_peri*/
 324                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 325
 326                                 /*pclk_peri_pre*/
 327                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 328
 329                                 /*hclk_vio_pre*/
 330                                 <&clk_gates6 12>,/*hclk_vio_niu*/
 331                                 <&clk_gates6 1>,/*hclk_lcdc*/
 332
 333                                 /*aclk_vio0_pre*/
 334                                 <&clk_gates6 13>,/*aclk_vio*/
 335                                 <&clk_gates6 0>,/*aclk_lcdc*/
 336
 337                                 /*aclk_vio1_pre*/
 338                                 <&clk_gates9 10>,/*aclk_vio1_niu*/
 339
 340                                 /*UART*/
 341                                 <&clk_gates1 12>,
 342                                 <&clk_gates1 13>,
 343                                 <&clk_gates8 2>,/*pclk_uart2*/
 344
 345                                 <&clk_gpu>,
 346
 347                                 /*jtag*/
 348                                 <&clk_gates1 3>,/*clk_jtag*/
 349
 350                                 /*pmu*/
 351                                 <&clk_gates1 0>;/*pclk_pmu_pre*/
 352         };
 353
 354         i2c0: i2c@20072000 {
 355                 compatible = "rockchip,rk30-i2c";
 356                 reg = <0x20072000 0x1000>;
 357                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 pinctrl-names = "default", "gpio";
 361                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 362                 pinctrl-1 = <&i2c0_gpio>;
 363                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 364                 clocks = <&clk_gates8 4>;
 365                 rockchip,check-idle = <1>;
 366                 status = "disabled";
 367         };
 368
 369         i2c1: i2c@20056000 {
 370                 compatible = "rockchip,rk30-i2c";
 371                 reg = <0x20056000 0x1000>;
 372                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 pinctrl-names = "default", "gpio";
 376                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 377                 pinctrl-1 = <&i2c1_gpio>;
 378                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 379                 clocks = <&clk_gates8 5>;
 380                 rockchip,check-idle = <1>;
 381                 status = "disabled";
 382         };
 383
 384         i2c2: i2c@2005a000 {
 385                 compatible = "rockchip,rk30-i2c";
 386                 reg = <0x2005a000 0x1000>;
 387                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 pinctrl-names = "default", "gpio";
 391                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 392                 pinctrl-1 = <&i2c2_gpio>;
 393                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 394                 clocks = <&clk_gates8 6>;
 395                 rockchip,check-idle = <1>;
 396                 status = "disabled";
 397         };
 398
 399         i2c3: i2c@2005e000 {
 400                 compatible = "rockchip,rk30-i2c";
 401                 reg = <0x2005e000 0x1000>;
 402                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 pinctrl-names = "default", "gpio";
 406                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 407                 pinctrl-1 = <&i2c3_gpio>;
 408                 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
 409                 clocks = <&clk_gates8 7>;
 410                 rockchip,check-idle = <1>;
 411                 status = "disabled";
 412         };
 413
 414         i2s0: i2s@10220000 {
 415                 compatible = "rockchip-i2s";
 416                 reg = <0x10220000 0x1000>;
 417                 i2s-id = <0>;
 418                 clocks = <&clk_i2s_2ch>, <&clk_i2s_2ch_out>, <&clk_gates7 2>;
 419                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 420                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 421                 dmas = <&pdma 0>, <&pdma 1>;
 422                 //#dma-cells = <2>;
 423                 dma-names = "tx", "rx";
 424                 //pinctrl-names = "default", "sleep";
 425                 //pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo>;
 426                 //pinctrl-1 = <&i2s0_gpio>;
 427         };
 428
 429         i2s1: i2s@10200000 {
 430                 compatible = "rockchip-i2s";
 431                 reg = <0x10200000 0x1000>;
 432                 i2s-id = <1>;
 433                 clocks = <&clk_i2s_8ch>, <&clk_gates7 4>;
 434                 clock-names = "i2s_clk", "i2s_hclk";
 435                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 436                 dmas = <&pdma 14>, <&pdma 15>;
 437                 //#dma-cells = <2>;
 438                 dma-names = "tx", "rx";
 439         };
 440
 441         spdif: spdif@10204000 {
 442                 compatible = "rockchip-spdif";
 443                 reg = <0x10204000 0x1000>;
 444                 clocks = <&clk_spdif>, <&clk_gates10 8>;
 445                 clock-names = "spdif_8ch_mclk", "spdif_hclk";
 446                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 447                 dmas = <&pdma 13>;
 448                 //#dma-cells = <1>;
 449                 dma-names = "tx";
 450                 //pinctrl-names = "default";
 451                 //pinctrl-0 = <&spdif_tx>;
 452         };
 453
 454         dsihost0: mipi@10110000{
 455                 compatible = "rockchip,rk32-dsi";
 456                 rockchip,prop = <0>;
 457                 reg = <0x10110000 0x4000>, <0x20038000 0x4000>;
 458                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 459                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 460                 clocks = <&clk_gates2 15>, <&clk_gates5 0> ;//, <&pd_mipidsi>;
 461                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";//, "pd_mipi_dsi";
 462                 status = "okay";
 463         };
 464
 465         emmc: rksdmmc@1021c000 {
 466                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 467                 reg = <0x1021c000 0x4000>;
 468                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 469                 #address-cells = <1>;
 470                 #size-cells = <0>;
 471                 //pinctrl-names = "default",,"suspend";
 472                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 473                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 474                 clock-names = "clk_mmc", "hclk_mmc";
 475                 dmas = <&pdma 12>;
 476                 dma-names = "dw_mci";
 477                 num-slots = <1>;
 478                 fifo-depth = <0x100>;
 479                 bus-width = <8>;
 480         };
 481
 482
 483         sdmmc: rksdmmc@10214000 {
 484                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 485                 reg = <0x10214000 0x4000>;
 486                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 487                 #address-cells = <1>;
 488                 #size-cells = <0>;
 489                 pinctrl-names = "default", "idle";
 490                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_pwren &sdmmc0_dectn &sdmmc0_bus4>;
 491                 pinctrl-1 = <&sdmmc0_gpio>;
 492                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 493                 clock-names = "clk_mmc", "hclk_mmc";
 494                 dmas = <&pdma 10>;
 495                 dma-names = "dw_mci";
 496                 num-slots = <1>;
 497                 fifo-depth = <0x100>;
 498                 bus-width = <4>;
 499         };
 500
 501         sdio: rksdmmc@10218000 {
 502                 compatible = "rockchip,rk_mmc", "rockchip,rk312x-sdmmc";
 503                 reg = <0x10218000 0x4000>;
 504                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 505                 #address-cells = <1>;
 506                 #size-cells = <0>;
 507                 pinctrl-names = "default","idle";
 508                 pinctrl-0 = <&sdio0_pwren &sdio0_cmd>;
 509                 pinctrl-1 = <&sdio0_gpio>;
 510                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 511                 clock-names = "clk_mmc", "hclk_mmc";
 512                 dmas = <&pdma 11>;
 513                 dma-names = "dw_mci";
 514                 num-slots = <1>;
 515                 fifo-depth = <0x100>;
 516                 bus-width = <4>;
 517         };
 518
 519         adc: adc@2006c000 {
 520                 compatible = "rockchip,saradc";
 521                 reg = <0x2006c000 0x100>;
 522                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 523                 #io-channel-cells = <1>;
 524                 io-channel-ranges;
 525                 rockchip,adc-vref = <1800>;
 526                 clock-frequency = <1000000>;
 527                 clocks = <&clk_saradc>, <&clk_gates7 14>;
 528                 clock-names = "saradc", "pclk_saradc";
 529                 status = "disabled";
 530         };
 531
 532         pwm0: pwm@20050000 {
 533                 compatible = "rockchip,rk-pwm";
 534                 reg = <0x20050000 0x10>;
 535                 #pwm-cells = <2>;
 536                 pinctrl-names = "default";
 537                 pinctrl-0 = <&pwm0_pin>;
 538                 clocks = <&clk_gates7 10>;
 539                 clock-names = "pclk_pwm";
 540                 status = "disabled";
 541         };
 542
 543         pwm1: pwm@20050010 {
 544                 compatible = "rockchip,rk-pwm";
 545                 reg = <0x20050010 0x10>;
 546                 #pwm-cells = <2>;
 547                 pinctrl-names = "default";
 548                 pinctrl-0 = <&pwm1_pin>;
 549                 clocks = <&clk_gates7 10>;
 550                 clock-names = "pclk_pwm";
 551                 status = "disabled";
 552         };
 553
 554         pwm2: pwm@20050020 {
 555                 compatible = "rockchip,rk-pwm";
 556                 reg = <0x20050020 0x10>;
 557                 #pwm-cells = <2>;
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&pwm2_pin>;
 560                 clocks = <&clk_gates7 10>;
 561                 clock-names = "pclk_pwm";
 562                 status = "disabled";
 563         };
 564
 565         pwm3: pwm@20050030 {
 566                 compatible = "rockchip,rk-pwm";
 567                 reg = <0x20050030 0x10>;
 568                 #pwm-cells = <2>;
 569                 pinctrl-names = "default";
 570                 pinctrl-0 = <&pwm3_pin>;
 571                 clocks = <&clk_gates7 10>;
 572                 clock-names = "pclk_pwm";
 573                 status = "disabled";
 574         };
 575
 576         remotectl: pwm@20050030 {
 577                 compatible = "rockchip,remotectl-pwm";
 578                 reg = <0x20050030 0x10>;
 579                 #pwm-cells = <2>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&pwm3_pin>;
 582                 clocks = <&clk_gates7 10>;
 583                 clock-names = "pclk_pwm";
 584                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 585                 status = "okay";
 586         };
 587         dwc_control_usb: dwc-control-usb@20008000 {
 588                 compatible = "rockchip,rk3126-dwc-control-usb";
 589                 reg = <0x20008000 0x4>;
 590                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 591                 interrupt-names = "otg_bvalid";
 592                 clocks = <&clk_gates9 13>;
 593                 clock-names = "hclk_usb_peri";
 594                 rockchip,remote_wakeup;
 595                 rockchip,usb_irq_wakeup;
 596                 resets = <&reset RK3128_RST_USBPOR>;
 597                 reset-names = "usbphy_por";
 598                 usb_bc{
 599                         compatible = "inno,phy";
 600                         regbase = &dwc_control_usb;
 601                 };
 602         };
 603
 604         usb0: usb@10180000 {
 605                 compatible = "rockchip,rk3126_usb20_otg";
 606                 reg = <0x10180000 0x40000>;
 607                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 608                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 609                 clock-names = "clk_usbphy0", "hclk_usb0";
 610                 resets = <&reset RK3128_RST_USBOTG0>, <&reset RK3128_RST_USBOTG0>,
 611                                 <&reset RK3128_RST_OTGC0>;
 612                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 613                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 614                 rockchip,usb-mode = <0>;
 615         };
 616
 617         usb1: usb@101c0000 {
 618                 compatible = "rockchip,rk3126_usb20_host";
 619                 reg = <0x101c0000 0x40000>;
 620                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 621                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 622                 clock-names = "clk_usbphy1", "hclk_usb1";
 623                 resets = <&reset RK3128_RST_USBOTG1>, <&reset RK3128_RST_UTMI1>,
 624                                 <&reset RK3128_RST_OTGC1>;
 625                 reset-names = "host_ahb", "host_phy", "host_controller";
 626         };
 627
 628         fb: fb{
 629                 compatible = "rockchip,rk-fb";
 630                 rockchip,disp-mode = <ONE_DUAL>;
 631         };
 632
 633         rk_screen: rk_screen{
 634                 compatible = "rockchip,screen";
 635         };
 636
 637         lvds: lvds@20038000 {
 638                 compatible = "rockchip,rk31xx-lvds";
 639                 reg = <0x20038000 0x4000>;
 640                 clocks = <&clk_gates5 0>;
 641                 clock-names = "pclk_lvds";
 642                 pinctrl-names = "lcdc", "sleep";
 643                 pinctrl-0 = <&lcdc0_lcdc_d>;
 644                 pinctrl-1 = <&lcdc0_lcdc_gpio>;
 645         };
 646
 647         lcdc: lcdc@1010e000 {
 648                 compatible = "rockchip,rk312x-lcdc";
 649                 rockchip,prop = <PRMRY>;
 650                 reg = <0x1010e000 0x2000>;
 651                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 652                 clocks = <&clk_gates6 0>, <&dclk_lcdc0>, <&clk_gates6 1>, <&sclk_lcdc0>;
 653                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk";
 654                 rockchip,iommu-enabled = <1>;
 655                 status = "disabled";
 656         };
 657
 658         hdmi: hdmi@20034000 {
 659                 compatible = "rockchip,rk312x-hdmi";
 660                 reg = <0x20034000 0x4000>;
 661                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 662                 rockchip,hdmi_lcdc_source = <0>;
 663                 pinctrl-names = "default", "gpio";
 664                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 665                 pinctrl-1 = <&hdmi_gpio>;
 666                 clocks = <&clk_gates3 8>;
 667                 clock-names = "pclk_hdmi";
 668                 status = "disabled";
 669         };
 670
 671         tve: tve{
 672                 compatible = "rockchip,rk312x-tve";
 673                 reg = <0x1010e200 0x100>;
 674                 status = "disabled";
 675         };
 676
 677         vpu: vpu_service@10106000 {
 678                 compatible = "vpu_service";
 679                 iommu_enabled = <1>;
 680                 reg = <0x10106000 0x800>;
 681                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 682                 interrupt-names = "irq_enc", "irq_dec";
 683                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 684                 clock-names = "aclk_vcodec", "hclk_vcodec";
 685                 name = "vpu_service";
 686                 status = "okay";
 687         };
 688
 689         hevc: hevc_service@10104000 {
 690                 compatible = "rockchip,hevc_service";
 691                 iommu_enabled = <1>;
 692                 reg = <0x10104000 0x400>;
 693                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 694                 interrupt-names = "irq_dec";
 695                 clocks = <&clk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>;
 696                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 697                 name = "hevc_service";
 698                 status = "okay";
 699         };
 700
 701         iep: iep@10108000 {
 702                 compatible = "rockchip,iep";
 703                 iommu_enabled = <1>;
 704                 reg = <0x10108000 0x800>;
 705                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 706                 clocks = <&clk_gates9 8>, <&clk_gates9 7>;
 707                 clock-names = "aclk_iep", "hclk_iep";
 708                 status = "okay";
 709         };
 710
 711         rga: rga@1010c000 {
 712                 compatible = "rockchip,rga_drv";
 713                 reg = <0x1010c000 0x1000>;
 714                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 715                 clocks = <&clk_gates0 11>, <&clk_gates1 4>;
 716                 clock-names = "hclk_rga", "aclk_rga";
 717                 status = "okay";
 718         };
 719
 720   vop_mmu {
 721                 dbgname = "vop";
 722                 compatible = "iommu,vop_mmu";
 723                 reg = <0x1010e300 0x100>;
 724                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 725                 interrupt-names = "vop_mmu";
 726           };
 727
 728           hevc_mmu {
 729                 dbgname = "hevc";
 730                 compatible = "iommu,hevc_mmu";
 731                 reg = <0x10104440 0x100>,
 732                       <0x10104480 0x100>;
 733                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 734                 interrupt-names = "hevc_mmu";
 735           };
 736
 737           vpu_mmu {
 738                 dbgname = "vpu";
 739                 compatible = "iommu,vpu_mmu";
 740                 reg = <0x10104800 0x100>;
 741                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 742                 interrupt-names = "vpu_mmu";
 743           };
 744
 745           iep_mmu {
 746                 dbgname = "iep";
 747                 compatible = "iommu,iep_mmu";
 748                 reg = <0x10108800 0x100>;
 749                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 750                 interrupt-names = "iep_mmu";
 751           };
 752
 753           dvfs {
 754                 temp-limit-enable = <0>;
 755                 target-temp = <80>;
 756
 757                 vd_arm: vd_arm {
 758                         regulator_name = "vdd_arm";
 759                         pd_core {
 760                                 clk_core_dvfs_table: clk_core {
 761                                         operating-points = <
 762                                                 /* KHz    uV */
 763                                                 312000 1100000
 764                                                 504000 1100000
 765                                                 816000 1100000
 766                                                 1008000 1100000
 767                                                 >;
 768                                         temp-channel = <1>;
 769                                         normal-temp-limit = <
 770                                         /*delta-temp    delta-freq*/
 771                                                 3       96000
 772                                                 6       144000
 773                                                 9       192000
 774                                                 15      384000
 775                                                 >;
 776                                         performance-temp-limit = <
 777                                                 /*temp    freq*/
 778                                                 110     816000
 779                                                 >;
 780                                         status = "okay";
 781                                         regu-mode-table = <
 782                                                 /*freq     mode*/
 783                                                 1008000    4
 784                                                 0          3
 785                                         >;
 786                                         regu-mode-en = <0>;
 787                                 };
 788                         };
 789                 };
 790
 791                 vd_logic: vd_logic {
 792                         regulator_name = "vdd_logic";
 793                         pd_ddr {
 794                                 clk_ddr_dvfs_table: clk_ddr {
 795                                         operating-points = <
 796                                                 /* KHz    uV */
 797                                                 200000 1200000
 798                                                 300000 1200000
 799                                                 400000 1200000
 800                                                 >;
 801                                         status = "disabled";
 802                                 };
 803                         };
 804
 805                         pd_gpu {
 806                                 clk_gpu_dvfs_table: clk_gpu {
 807                                         operating-points = <
 808                                                 /* KHz    uV */
 809                                                 200000 1200000
 810                                                 300000 1200000
 811                                                 400000 1200000
 812                                                 >;
 813                                         status = "okay";
 814                                         regu-mode-table = <
 815                                                 /*freq     mode*/
 816                                                 200000     4
 817                                                 0          3
 818                                         >;
 819                                         regu-mode-en = <0>;
 820                                 };
 821                         };
 822                 };
 823         };
 824         ion {
 825                 compatible = "rockchip,ion";
 826                 #address-cells = <1>;
 827                 #size-cells = <0>;
 828
 829                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 830                         compatible = "rockchip,ion-reserve";
 831                         rockchip,ion_heap = <1>;
 832                         reg = <0x00000000 0x10000000>; /* 256MB */
 833                 };
 834                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 835                         rockchip,ion_heap = <3>;
 836                 };
 837         };
 838         cif: cif@1010a000 {
 839              compatible = "rockchip,cif";
 840              reg = <0x1010a000 0x2000>;
 841              interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 842              clocks = <&clk_gates3 3>,<&clk_gates6 5>,<&clk_gates6 4>,<&clk_cif0_in>,<&clk_cif_out>;
 843              clock-names = "pd_cif0", "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
 844              status = "okay";
 845              };
 846 };