2 * Copyright (C) 2014 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk312x.h>
19 compatible = "rockchip,rk-clocks";
22 ranges = <0x0 0x20000000 0x1f0>;
25 compatible = "rockchip,rk-fixed-rate-cons";
28 compatible = "rockchip,rk-fixed-clock";
29 clock-output-names = "xin24m";
30 clock-frequency = <24000000>;
35 compatible = "rockchip,rk-fixed-clock";
37 clock-output-names = "xin12m";
38 clock-frequency = <12000000>;
42 gmac_clkin: gmac_clkin {
43 compatible = "rockchip,rk-fixed-clock";
44 clock-output-names = "gmac_clkin";
45 clock-frequency = <125000000>;
50 compatible = "rockchip,rk-fixed-clock";
51 clock-output-names = "usb480m";
52 clock-frequency = <480000000>;
56 i2s_clkin: i2s_clkin {
57 compatible = "rockchip,rk-fixed-clock";
58 clock-output-names = "i2s_clkin";
59 clock-frequency = <0>;
64 compatible = "rockchip,rk-fixed-clock";
65 clock-output-names = "jtag_tck";
66 clock-frequency = <0>;
70 pclkin_cif: pclkin_cif {
71 compatible = "rockchip,rk-fixed-clock";
72 clock-output-names = "pclkin_cif";
73 clock-frequency = <0>;
77 clk_tsp_in: clk_tsp_in {
78 compatible = "rockchip,rk-fixed-clock";
79 clock-output-names = "clk_tsp_in";
80 clock-frequency = <0>;
86 compatible = "rockchip,rk-fixed-clock";
87 clock-output-names = "dummy";
88 clock-frequency = <0>;
92 dummy_cpll: dummy_cpll {
93 compatible = "rockchip,rk-fixed-clock";
94 clock-output-names = "dummy_cpll";
95 clock-frequency = <0>;
102 compatible = "rockchip,rk-fixed-factor-cons";
104 clk_gpll_div2: clk_gpll_div2 {
105 compatible = "rockchip,rk-fixed-factor-clock";
106 clocks = <&clk_gpll>;
107 clock-output-names = "clk_gpll_div2";
113 clk_gpll_div3: clk_gpll_div3 {
114 compatible = "rockchip,rk-fixed-factor-clock";
115 clocks = <&clk_gpll>;
116 clock-output-names = "clk_gpll_div3";
122 clk_pvtm_func: clk_pvtm_func {
123 compatible = "rockchip,rk-fixed-factor-clock";
125 clock-output-names = "clk_pvtm_func";
131 hclk_vepu: hclk_vepu {
132 compatible = "rockchip,rk-fixed-factor-clock";
133 clocks = <&clk_vepu>;
134 clock-output-names = "hclk_vepu";
140 hclk_vdpu: hclk_vdpu {
141 compatible = "rockchip,rk-fixed-factor-clock";
142 clocks = <&clk_vdpu>;
143 clock-output-names = "hclk_vdpu";
149 pclkin_cif_inv: pclkin_cif_inv {
150 compatible = "rockchip,rk-fixed-factor-clock";
151 clocks = <&clk_gates3 3>;
152 clock-output-names = "pclkin_cif_inv";
161 compatible = "rockchip,rk-pd-cons";
164 compatible = "rockchip,rk-pd-clock";
165 clock-output-names = "pd_gpu";
166 rockchip,pd-id = <CLK_PD_GPU>;
171 compatible = "rockchip,rk-pd-clock";
172 clock-output-names = "pd_video";
173 rockchip,pd-id = <CLK_PD_VIDEO>;
178 compatible = "rockchip,rk-pd-clock";
179 clock-output-names = "pd_vio";
180 rockchip,pd-id = <CLK_PD_VIO>;
185 compatible = "rockchip,rk-pd-clock";
187 clock-output-names = "pd_vop0";
188 rockchip,pd-id = <CLK_PD_VIRT>;
193 compatible = "rockchip,rk-pd-clock";
195 clock-output-names = "pd_vop1";
196 rockchip,pd-id = <CLK_PD_VIRT>;
201 compatible = "rockchip,rk-pd-clock";
203 clock-output-names = "pd_vip";
204 rockchip,pd-id = <CLK_PD_VIRT>;
209 compatible = "rockchip,rk-pd-clock";
211 clock-output-names = "pd_iep";
212 rockchip,pd-id = <CLK_PD_VIRT>;
217 compatible = "rockchip,rk-pd-clock";
219 clock-output-names = "pd_rga";
220 rockchip,pd-id = <CLK_PD_VIRT>;
225 compatible = "rockchip,rk-pd-clock";
227 clock-output-names = "pd_ebc";
228 rockchip,pd-id = <CLK_PD_VIRT>;
232 pd_mipidsi: pd_mipidsi {
233 compatible = "rockchip,rk-pd-clock";
235 clock-output-names = "pd_mipidsi";
236 rockchip,pd-id = <CLK_PD_VIRT>;
241 compatible = "rockchip,rk-pd-clock";
243 clock-output-names = "pd_hdmi";
244 rockchip,pd-id = <CLK_PD_VIRT>;
252 compatible = "rockchip,rk-clock-regs";
253 #address-cells = <1>;
255 reg = <0x0000 0x01f0>;
258 /* PLL control regs */
260 compatible = "rockchip,rk-pll-cons";
261 #address-cells = <1>;
265 clk_apll: pll-clk@0000 {
266 compatible = "rockchip,rk3188-pll-clk";
268 mode-reg = <0x0040 0>;
269 status-reg = <0x0004 10>;
271 clock-output-names = "clk_apll";
272 rockchip,pll-type = <CLK_PLL_3036_APLL>;
276 clk_dpll: pll-clk@0010 {
277 compatible = "rockchip,rk3188-pll-clk";
279 mode-reg = <0x0040 4>;
280 status-reg = <0x0014 10>;
282 clock-output-names = "clk_dpll";
283 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
287 clk_cpll: pll-clk@0020 {
288 compatible = "rockchip,rk3188-pll-clk";
290 mode-reg = <0x0040 8>;
291 status-reg = <0x0024 10>;
293 clock-output-names = "clk_cpll";
294 rockchip,pll-type = <CLK_PLL_312XPLUS>;
296 #clock-init-cells = <1>;
299 clk_gpll: pll-clk@0030 {
300 compatible = "rockchip,rk3188-pll-clk";
302 mode-reg = <0x0040 12>;
303 status-reg = <0x0034 10>;
305 clock-output-names = "clk_gpll";
306 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
308 #clock-init-cells = <1>;
313 /* Select control regs */
315 compatible = "rockchip,rk-sel-cons";
316 #address-cells = <1>;
320 clk_sel_con0: sel-con@0044 {
321 compatible = "rockchip,rk3188-selcon";
323 #address-cells = <1>;
326 clk_core_div: clk_core_div {
327 compatible = "rockchip,rk3188-div-con";
328 rockchip,bits = <0 5>;
329 clocks = <&clk_core>;
330 clock-output-names = "clk_core";
331 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
333 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
334 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
335 CLK_SET_RATE_NO_REPARENT)>;
338 /* reg[6:5]: reserved */
340 clk_core: clk_core_mux {
341 compatible = "rockchip,rk3188-mux-con";
342 rockchip,bits = <7 1>;
343 clocks = <&clk_apll>, <&clk_gpll_div2>;
344 clock-output-names = "clk_core";
346 #clock-init-cells = <1>;
349 aclk_cpu_div: aclk_cpu_div {
350 compatible = "rockchip,rk3188-div-con";
351 rockchip,bits = <8 5>;
352 clocks = <&aclk_cpu>;
353 clock-output-names = "aclk_cpu";
354 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
356 rockchip,clkops-idx =
357 <CLKOPS_RATE_MUX_DIV>;
358 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
361 aclk_cpu: aclk_cpu_mux {
362 compatible = "rockchip,rk3188-mux-con";
363 rockchip,bits = <13 2>;
364 clocks = <&clk_apll>, <&clk_gpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
365 clock-output-names = "aclk_cpu";
367 #clock-init-cells = <1>;
370 /* reg[15]: reserved */
374 clk_sel_con1: sel-con@0048 {
375 compatible = "rockchip,rk3188-selcon";
377 #address-cells = <1>;
380 pclk_dbg_div: pclk_dbg_div {
381 compatible = "rockchip,rk3188-div-con";
382 rockchip,bits = <0 4>;
383 clocks = <&clk_core>;
384 clock-output-names = "pclk_dbg";
385 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
387 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
390 aclk_core_pre: aclk_core_pre_div {
391 compatible = "rockchip,rk3188-div-con";
392 rockchip,bits = <4 3>;
393 clocks = <&clk_core>;
394 clock-output-names = "aclk_core_pre";
395 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
397 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
400 /* reg[7]: reserved */
402 hclk_cpu_pre: hclk_cpu_pre_div {
403 compatible = "rockchip,rk3188-div-con";
404 rockchip,bits = <8 2>;
405 clocks = <&aclk_cpu>;
406 clock-output-names = "hclk_cpu_pre";
407 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
409 #clock-init-cells = <1>;
412 /* reg[11:10]: reserved */
414 pclk_cpu_pre: pclk_cpu_pre_div {
415 compatible = "rockchip,rk3188-div-con";
416 rockchip,bits = <12 3>;
417 clocks = <&aclk_cpu>;
418 clock-output-names = "pclk_cpu_pre";
419 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
421 #clock-init-cells = <1>;
424 /* reg[15]: reserved */
427 clk_sel_con2: sel-con@004c {
428 compatible = "rockchip,rk3188-selcon";
430 #address-cells = <1>;
433 clk_pvtm_div: clk_pvtm_div {
434 compatible = "rockchip,rk3188-mux-con";
435 rockchip,bits = <0 7>;
436 clocks = <&clk_pvtm_func>;
437 clock-output-names = "clk_pvtm";
438 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
440 #clock-init-cells = <1>;
443 /* reg[7]: reserved */
445 clk_nandc_div: clk_nandc_div {
446 compatible = "rockchip,rk3188-div-con";
447 rockchip,bits = <8 5>;
448 clocks = <&clk_nandc>;
449 clock-output-names = "clk_nandc";
450 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
452 rockchip,clkops-idx =
453 <CLKOPS_RATE_MUX_DIV>;
456 /* reg[13]: reserved */
458 clk_nandc: clk_nandc_mux {
459 compatible = "rockchip,rk3188-mux-con";
460 rockchip,bits = <14 2>;
461 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
462 clock-output-names = "clk_nandc";
464 #clock-init-cells = <1>;
469 clk_sel_con3: sel-con@0050 {
470 compatible = "rockchip,rk3188-selcon";
472 #address-cells = <1>;
475 clk_i2s_2ch_pll_div: clk_i2s_2ch_pll_div {
476 compatible = "rockchip,rk3188-div-con";
477 rockchip,bits = <0 7>;
478 clocks = <&clk_i2s_2ch_pll>;
479 clock-output-names = "clk_i2s_2ch_pll";
480 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
482 rockchip,clkops-idx =
483 <CLKOPS_RATE_MUX_DIV>;
484 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
487 /* reg[7]: reserved */
489 clk_i2s_2ch: clk_i2s_2ch_mux {
490 compatible = "rockchip,rk3188-mux-con";
491 rockchip,bits = <8 2>;
492 clocks = <&clk_i2s_2ch_pll_div>, <&i2s_2ch_frac>, <&i2s_clkin>, <&xin12m>;
493 clock-output-names = "clk_i2s_2ch";
495 rockchip,clkops-idx =
496 <CLKOPS_RATE_RK3288_I2S>;
497 rockchip,flags = <CLK_SET_RATE_PARENT>;
500 /* reg[11:10]: reserved */
502 clk_i2s_2ch_out: clk_i2s_2ch_out_mux {
503 compatible = "rockchip,rk3188-mux-con";
504 rockchip,bits = <12 1>;
505 clocks = <&clk_i2s_2ch>, <&xin12m>;
506 clock-output-names = "i2s_clkout";
510 /* reg[13]: reserved */
512 clk_i2s_2ch_pll: i2s_2ch_pll_mux {
513 compatible = "rockchip,rk3188-mux-con";
514 rockchip,bits = <14 2>;
515 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
516 clock-output-names = "clk_i2s_2ch_pll";
518 #clock-init-cells = <1>;
523 clk_sel_con4: sel-con@0054 {
524 compatible = "rockchip,rk3188-selcon";
526 #address-cells = <1>;
529 clk_tsp_div: clk_tsp_div {
530 compatible = "rockchip,rk3188-div-con";
531 rockchip,bits = <0 5>;
533 clock-output-names = "clk_tsp";
534 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
536 rockchip,clkops-idx =
537 <CLKOPS_RATE_MUX_DIV>;
540 /* reg[5]: reserved */
542 clk_tsp: clk_tsp_mux {
543 compatible = "rockchip,rk3188-mux-con";
544 rockchip,bits = <6 2>;
545 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
546 clock-output-names = "clk_tsp";
548 #clock-init-cells = <1>;
551 clk_24m_div: clk_24m_div {
552 compatible = "rockchip,rk3188-div-con";
553 rockchip,bits = <8 5>;
555 clock-output-names = "clk_24m";
556 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
560 /* reg[15:13]: reserved */
565 clk_sel_con5: sel-con@0058 {
566 compatible = "rockchip,rk3188-selcon";
568 #address-cells = <1>;
571 clk_mac_pll_div: clk_mac_pll_div {
572 compatible = "rockchip,rk3188-div-con";
573 rockchip,bits = <0 5>;
574 clocks = <&clk_mac_pll>;
575 clock-output-names = "clk_mac_pll";
576 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
578 rockchip,clkops-idx =
579 <CLKOPS_RATE_MUX_DIV>;
580 #clock-init-cells = <1>;
583 /* reg[5]: reserved */
585 clk_mac_pll: clk_mac_pll_mux {
586 compatible = "rockchip,rk3188-mux-con";
587 rockchip,bits = <6 2>;
588 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
589 clock-output-names = "clk_mac_pll";
591 #clock-init-cells = <1>;
594 /* reg[14:8]: reserved */
596 clk_mac_ref: clk_mac_ref_mux {
597 compatible = "rockchip,rk3188-mux-con";
598 rockchip,bits = <15 1>;
599 clocks = <&clk_mac_pll_div>, <&gmac_clkin>;
600 clock-output-names = "clk_mac_ref";
602 rockchip,clkops-idx =
603 <CLKOPS_RATE_MAC_REF>;
604 rockchip,flags = <CLK_SET_RATE_PARENT>;
605 #clock-init-cells = <1>;
611 clk_sel_con6: sel-con@005c {
612 compatible = "rockchip,rk3188-selcon";
614 #address-cells = <1>;
617 spdif_div: spdif_div {
618 compatible = "rockchip,rk3188-div-con";
619 rockchip,bits = <0 7>;
620 clocks = <&clk_spdif_pll>;
621 clock-output-names = "clk_spdif_pll";
622 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
624 rockchip,clkops-idx =
625 <CLKOPS_RATE_MUX_DIV>;
626 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
629 /* reg[7]: reserved */
631 clk_spdif: spdif_mux {
632 compatible = "rockchip,rk3188-mux-con";
633 rockchip,bits = <8 2>;
634 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
635 clock-output-names = "clk_spdif";
637 rockchip,clkops-idx =
638 <CLKOPS_RATE_RK3288_I2S>;
639 rockchip,flags = <CLK_SET_RATE_PARENT>;
642 /* reg[13:10]: reserved */
644 clk_spdif_pll: spdif_pll_mux {
645 compatible = "rockchip,rk3188-mux-con";
646 rockchip,bits = <14 2>;
647 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
648 clock-output-names = "clk_spdif_pll";
650 #clock-init-cells = <1>;
655 clk_sel_con7: sel-con@0060 {
656 compatible = "rockchip,rk3188-selcon";
658 #address-cells = <1>;
661 i2s_2ch_frac: i2s_2ch_frac {
662 compatible = "rockchip,rk3188-frac-con";
663 clocks = <&clk_i2s_2ch_pll>;
664 clock-output-names = "i2s_2ch_frac";
665 /* numerator denominator */
666 rockchip,bits = <0 32>;
667 rockchip,clkops-idx =
673 clk_sel_con8: sel-con@0064 {
674 compatible = "rockchip,rk3188-selcon";
676 #address-cells = <1>;
679 i2s_8ch_frac: i2s_8ch_frac {
680 compatible = "rockchip,rk3188-frac-con";
681 clocks = <&clk_i2s_8ch_pll>;
682 clock-output-names = "i2s_8ch_frac";
683 /* numerator denominator */
684 rockchip,bits = <0 32>;
685 rockchip,clkops-idx =
691 clk_sel_con9: sel-con@0068 {
692 compatible = "rockchip,rk3188-selcon";
694 #address-cells = <1>;
697 clk_i2s_8ch_pll_div: clk_i2s_8ch_pll_div {
698 compatible = "rockchip,rk3188-div-con";
699 rockchip,bits = <0 7>;
700 clocks = <&clk_i2s_8ch_pll>;
701 clock-output-names = "clk_i2s_8ch_pll";
702 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
704 rockchip,clkops-idx =
705 <CLKOPS_RATE_MUX_DIV>;
706 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
709 /* reg[7]: reserved */
711 clk_i2s_8ch: clk_i2s_8ch_mux {
712 compatible = "rockchip,rk3188-mux-con";
713 rockchip,bits = <8 2>;
714 clocks = <&clk_i2s_8ch_pll_div>, <&i2s_8ch_frac>, <&i2s_clkin>, <&xin12m>;
715 clock-output-names = "clk_i2s_8ch";
717 rockchip,clkops-idx =
718 <CLKOPS_RATE_RK3288_I2S>;
719 rockchip,flags = <CLK_SET_RATE_PARENT>;
722 /* reg[13:10]: reserved */
724 clk_i2s_8ch_pll: i2s_8ch_pll_mux {
725 compatible = "rockchip,rk3188-mux-con";
726 rockchip,bits = <14 2>;
727 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
728 clock-output-names = "clk_i2s_8ch_pll";
730 #clock-init-cells = <1>;
735 clk_sel_con10: sel-con@006c {
736 compatible = "rockchip,rk3188-selcon";
738 #address-cells = <1>;
741 aclk_peri_div: aclk_peri_div {
742 compatible = "rockchip,rk3188-div-con";
743 rockchip,bits = <0 5>;
744 clocks = <&aclk_peri>;
745 clock-output-names = "aclk_peri";
746 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
748 rockchip,clkops-idx =
749 <CLKOPS_RATE_MUX_DIV>;
750 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
753 /* reg[7:5]: reserved */
755 hclk_peri_pre: hclk_peri_pre_div {
756 compatible = "rockchip,rk3188-div-con";
757 rockchip,bits = <8 2>;
758 clocks = <&aclk_peri>;
759 clock-output-names = "hclk_peri_pre";
760 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
761 rockchip,div-relations =
766 #clock-init-cells = <1>;
769 /* reg[11:10]: reserved */
771 pclk_peri_pre: pclk_peri_div {
772 compatible = "rockchip,rk3188-div-con";
773 rockchip,bits = <12 2>;
774 clocks = <&aclk_peri>;
775 clock-output-names = "pclk_peri_pre";
776 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
777 rockchip,div-relations =
783 #clock-init-cells = <1>;
786 aclk_peri: aclk_peri_mux {
787 compatible = "rockchip,rk3188-mux-con";
788 rockchip,bits = <14 2>;
789 clocks = <&clk_gpll>,<&clk_cpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
790 clock-output-names = "aclk_peri";
792 #clock-init-cells = <1>;
796 clk_sel_con11: sel-con@0070 {
797 compatible = "rockchip,rk3188-selcon";
799 #address-cells = <1>;
802 clk_sdmmc0_div: clk_sdmmc0_div {
803 compatible = "rockchip,rk3188-div-con";
804 rockchip,bits = <0 6>;
805 clocks = <&clk_sdmmc0>;
806 clock-output-names = "clk_sdmmc0";
807 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
809 rockchip,clkops-idx =
810 <CLKOPS_RATE_MUX_EVENDIV>;
813 clk_sdmmc0: clk_sdmmc0_mux {
814 compatible = "rockchip,rk3188-mux-con";
815 rockchip,bits = <6 2>;
816 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
817 clock-output-names = "clk_sdmmc0";
819 #clock-init-cells = <1>;
822 clk_sfc_div: clk_sfc_div {
823 compatible = "rockchip,rk3188-div-con";
824 rockchip,bits = <8 5>;
826 clock-output-names = "clk_sfc";
827 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
829 rockchip,clkops-idx =
830 <CLKOPS_RATE_MUX_EVENDIV>;
833 /* reg[13]: reserved */
835 clk_sfc: clk_sfc_mux {
836 compatible = "rockchip,rk3188-mux-con";
837 rockchip,bits = <14 2>;
838 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
839 clock-output-names = "clk_sfc";
841 #clock-init-cells = <1>;
846 clk_sel_con12: sel-con@0074 {
847 compatible = "rockchip,rk3188-selcon";
849 #address-cells = <1>;
852 clk_sdio_div: clk_sdio_div {
853 compatible = "rockchip,rk3188-div-con";
854 rockchip,bits = <0 6>;
855 clocks = <&clk_sdio>;
856 clock-output-names = "clk_sdio";
857 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
859 rockchip,clkops-idx =
860 <CLKOPS_RATE_MUX_EVENDIV>;
863 clk_sdio: clk_sdio_mux {
864 compatible = "rockchip,rk3188-mux-con";
865 rockchip,bits = <6 2>;
866 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
867 clock-output-names = "clk_sdio";
869 #clock-init-cells = <1>;
872 clk_emmc_div: clk_emmc_div {
873 compatible = "rockchip,rk3188-div-con";
874 rockchip,bits = <8 6>;
875 clocks = <&clk_emmc>;
876 clock-output-names = "clk_emmc";
877 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
879 rockchip,clkops-idx =
880 <CLKOPS_RATE_MUX_EVENDIV>;
883 clk_emmc: clk_emmc_mux {
884 compatible = "rockchip,rk3188-mux-con";
885 rockchip,bits = <14 2>;
886 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
887 clock-output-names = "clk_emmc";
889 #clock-init-cells = <1>;
894 clk_sel_con13: sel-con@0078 {
895 compatible = "rockchip,rk3188-selcon";
897 #address-cells = <1>;
900 clk_uart0_pll_div: clk_uart0_pll_div {
901 compatible = "rockchip,rk3188-div-con";
902 rockchip,bits = <0 7>;
903 clocks = <&clk_uart0_pll>;
904 clock-output-names = "clk_uart0_pll";
905 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
909 /* reg[7]: reserved */
911 clk_uart0: clk_uart0_mux {
912 compatible = "rockchip,rk3188-mux-con";
913 rockchip,bits = <8 2>;
914 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>;
915 clock-output-names = "clk_uart0";
917 rockchip,clkops-idx =
918 <CLKOPS_RATE_RK3288_I2S>;
919 rockchip,flags = <CLK_SET_RATE_PARENT>;
922 /* reg[11:10]: reserved */
924 clk_uart0_pll: clk_uart0_pll_mux {
925 compatible = "rockchip,rk3188-mux-con";
926 rockchip,bits = <12 2>;
927 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
928 clock-output-names = "clk_uart0_pll";
930 #clock-init-cells = <1>;
933 clk_uart2_pll: clk_uart2_pll_mux {
934 compatible = "rockchip,rk3188-mux-con";
935 rockchip,bits = <14 2>;
936 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
937 clock-output-names = "clk_uart2_pll";
939 #clock-init-cells = <1>;
944 clk_sel_con14: sel-con@007c {
945 compatible = "rockchip,rk3188-selcon";
947 #address-cells = <1>;
950 clk_uart1_div: clk_uart1_div {
951 compatible = "rockchip,rk3188-div-con";
952 rockchip,bits = <0 7>;
953 clocks = <&clk_uart2_pll>;
954 clock-output-names = "clk_uart1_div";
955 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
959 /* reg[7]: reserved */
961 clk_uart1: clk_uart1_mux {
962 compatible = "rockchip,rk3188-mux-con";
963 rockchip,bits = <8 2>;
964 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
965 clock-output-names = "clk_uart1";
967 rockchip,clkops-idx =
968 <CLKOPS_RATE_RK3288_I2S>;
969 rockchip,flags = <CLK_SET_RATE_PARENT>;
972 /* reg[15:10]: reserved */
975 clk_sel_con15: sel-con@0080 {
976 compatible = "rockchip,rk3188-selcon";
978 #address-cells = <1>;
981 clk_uart2_div: clk_uart2_div {
982 compatible = "rockchip,rk3188-div-con";
983 rockchip,bits = <0 7>;
984 clocks = <&clk_uart2_pll>;
985 clock-output-names = "clk_uart2_div";
986 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
990 /* reg[7]: reserved */
992 clk_uart2: clk_uart2_mux {
993 compatible = "rockchip,rk3188-mux-con";
994 rockchip,bits = <8 2>;
995 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
996 clock-output-names = "clk_uart2";
998 rockchip,clkops-idx =
999 <CLKOPS_RATE_RK3288_I2S>;
1000 rockchip,flags = <CLK_SET_RATE_PARENT>;
1003 /* reg[15:10]: reserved */
1006 clk_sel_con17: sel-con@0088 {
1007 compatible = "rockchip,rk3188-selcon";
1009 #address-cells = <1>;
1012 uart0_frac: uart0_frac {
1013 compatible = "rockchip,rk3188-frac-con";
1014 clocks = <&clk_uart0_pll>;
1015 clock-output-names = "uart0_frac";
1016 /* numerator denominator */
1017 rockchip,bits = <0 32>;
1018 rockchip,clkops-idx =
1024 clk_sel_con18: sel-con@008c {
1025 compatible = "rockchip,rk3188-selcon";
1027 #address-cells = <1>;
1030 uart1_frac: uart1_frac {
1031 compatible = "rockchip,rk3188-frac-con";
1032 clocks = <&clk_uart1_div>;
1033 clock-output-names = "uart1_frac";
1034 /* numerator denominator */
1035 rockchip,bits = <0 32>;
1036 rockchip,clkops-idx =
1042 clk_sel_con19: sel-con@0090 {
1043 compatible = "rockchip,rk3188-selcon";
1045 #address-cells = <1>;
1048 uart2_frac: uart2_frac {
1049 compatible = "rockchip,rk3188-frac-con";
1050 clocks = <&clk_uart2_div>;
1051 clock-output-names = "uart2_frac";
1052 /* numerator denominator */
1053 rockchip,bits = <0 32>;
1054 rockchip,clkops-idx =
1061 clk_sel_con20: sel-con@0094 {
1062 compatible = "rockchip,rk3188-selcon";
1064 #address-cells = <1>;
1067 spdif_frac: spdif_frac {
1068 compatible = "rockchip,rk3188-frac-con";
1069 clocks = <&spdif_div>;
1070 clock-output-names = "spdif_frac";
1071 /* numerator denominator */
1072 rockchip,bits = <0 32>;
1073 rockchip,clkops-idx =
1080 clk_sel_con23: sel-con@00a0 {
1081 compatible = "rockchip,rk3188-selcon";
1083 #address-cells = <1>;
1086 dclk_ebc: dclk_ebc_mux {
1087 compatible = "rockchip,rk3188-mux-con";
1088 rockchip,bits = <0 2>;
1089 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
1090 clock-output-names = "dclk_ebc";
1092 #clock-init-cells = <1>;
1095 /* reg[7:2]: reserved */
1097 dclk_ebc_div: dclk_ebc_div {
1098 compatible = "rockchip,rk3188-div-con";
1099 rockchip,bits = <8 8>;
1100 clocks = <&dclk_ebc>;
1101 clock-output-names = "dclk_ebc";
1102 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1104 rockchip,clkops-idx =
1105 <CLKOPS_RATE_MUX_DIV>;
1110 clk_sel_con24: sel-con@00a4 {
1111 compatible = "rockchip,rk3188-selcon";
1113 #address-cells = <1>;
1116 clk_crypto_div: clk_crypto_div {
1117 compatible = "rockchip,rk3188-div-con";
1118 rockchip,bits = <0 2>;
1119 clocks = <&aclk_cpu>;
1120 clock-output-names = "clk_crypto";
1121 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1123 #clock-init-cells = <1>;
1126 /* reg[7:2]: reserved */
1128 clk_saradc: clk_saradc_div {
1129 compatible = "rockchip,rk3188-div-con";
1130 rockchip,bits = <8 8>;
1132 clock-output-names = "clk_saradc";
1133 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1135 #clock-init-cells = <1>;
1140 clk_sel_con25: sel-con@00a8 {
1141 compatible = "rockchip,rk3188-selcon";
1143 #address-cells = <1>;
1146 clk_spi0_div: clk_spi0_div {
1147 compatible = "rockchip,rk3188-div-con";
1148 rockchip,bits = <0 7>;
1149 clocks = <&clk_spi0>;
1150 clock-output-names = "clk_spi0";
1151 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1153 rockchip,clkops-idx =
1154 <CLKOPS_RATE_MUX_DIV>;
1157 /* reg[7]: reserved */
1159 clk_spi0: clk_spi0_mux {
1160 compatible = "rockchip,rk3188-mux-con";
1161 rockchip,bits = <8 2>;
1162 clocks = <&clk_cpll>, <&clk_gpll>,<&clk_gpll_div2>;
1163 clock-output-names = "clk_spi0";
1167 /* reg[15:10]: reserved */
1171 clk_sel_con26: sel-con@00ac {
1172 compatible = "rockchip,rk3188-selcon";
1174 #address-cells = <1>;
1178 compatible = "rockchip,rk3188-div-con";
1179 rockchip,bits = <0 2>;
1180 clocks = <&clk_ddr>;
1181 clock-output-names = "clk_ddr";
1182 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1183 rockchip,div-relations =
1188 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1189 CLK_SET_RATE_NO_REPARENT)>;
1190 rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
1193 /* reg[7:2]: reserved */
1195 clk_ddr: ddr_clk_pll_mux {
1196 compatible = "rockchip,rk3188-mux-con";
1197 rockchip,bits = <8 1>;
1198 clocks = <&clk_dpll>, <&dummy>;
1199 clock-output-names = "clk_ddr";
1203 /* reg[15:9]: reserved */
1206 clk_sel_con27: sel-con@00b0 {
1207 compatible = "rockchip,rk3188-selcon";
1209 #address-cells = <1>;
1212 dclk_lcdc0: dclk_lcdc0_mux {
1213 compatible = "rockchip,rk3188-mux-con";
1214 rockchip,bits = <0 2>;
1215 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1216 clock-output-names = "dclk_lcdc0";
1218 #clock-init-cells = <1>;
1221 /* reg[7:2]: reserved */
1223 dclk_lcdc0_div: dclk_lcdc0_div {
1224 compatible = "rockchip,rk3188-div-con";
1225 rockchip,bits = <8 8>;
1226 clocks = <&dclk_lcdc0>;
1227 clock-output-names = "dclk_lcdc0";
1228 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1230 rockchip,clkops-idx =
1231 <CLKOPS_RATE_MUX_DIV>;
1232 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1236 clk_sel_con28: sel-con@00b4 {
1237 compatible = "rockchip,rk3188-selcon";
1239 #address-cells = <1>;
1242 sclk_lcdc0: sclk_lcdc0_mux {
1243 compatible = "rockchip,rk3188-mux-con";
1244 rockchip,bits = <0 2>;
1245 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1246 clock-output-names = "sclk_lcdc0";
1248 #clock-init-cells = <1>;
1251 /* reg[7:2]: reserved */
1253 sclk_lcdc0_div: sclk_lcdc0_div {
1254 compatible = "rockchip,rk3188-div-con";
1255 rockchip,bits = <8 8>;
1256 clocks = <&sclk_lcdc0>;
1257 clock-output-names = "sclk_lcdc0";
1258 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1260 rockchip,clkops-idx =
1261 <CLKOPS_RATE_MUX_DIV>;
1262 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1266 clk_sel_con29: sel-con@00b8 {
1267 compatible = "rockchip,rk3188-selcon";
1269 #address-cells = <1>;
1272 clk_cif_pll: clk_cif_pll_mux {
1273 compatible = "rockchip,rk3188-mux-con";
1274 rockchip,bits = <0 2>;
1275 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1276 clock-output-names = "clk_cif_pll";
1278 #clock-init-cells = <1>;
1281 clk_cif_out_div: clk_cif_out_div {
1282 compatible = "rockchip,rk3188-div-con";
1283 rockchip,bits = <2 5>;
1284 clocks = <&clk_cif_out>;
1285 clock-output-names = "clk_cif_out";
1286 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1288 rockchip,clkops-idx =
1289 <CLKOPS_RATE_MUX_DIV>;
1290 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1293 clk_cif_out: clk_cif_out_mux {
1294 compatible = "rockchip,rk3188-mux-con";
1295 rockchip,bits = <7 1>;
1296 clocks = <&clk_cif_pll>, <&xin24m>;
1297 clock-output-names = "clk_cif_out";
1299 #clock-init-cells = <1>;
1302 pclk_pmu_pre: pclk_pmu_pre_div {
1303 compatible = "rockchip,rk3188-div-con";
1304 rockchip,bits = <8 6>;
1305 clocks = <&clk_cpll>;
1306 clock-output-names = "pclk_pmu_pre";
1307 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1309 #clock-init-cells = <1>;
1312 /* reg[15:14]: reserved */
1315 clk_sel_con30: sel-con@00bc {
1316 compatible = "rockchip,rk3188-selcon";
1318 #address-cells = <1>;
1321 clk_testout_div: clk_testout_div {
1322 compatible = "rockchip,rk3188-div-con";
1323 rockchip,bits = <0 5>;
1325 clock-output-names = "clk_testout";
1326 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1328 #clock-init-cells = <1>;
1331 /* reg[6:5]: reserved */
1333 clk_cif0_in: clk_cif0_in_mux {
1334 compatible = "rockchip,rk3188-mux-con";
1335 rockchip,bits = <7 1>;
1336 clocks = <&pclkin_cif>, <&pclkin_cif_inv>;
1337 clock-output-names = "clk_cif0_in";
1339 #clock-init-cells = <1>;
1342 hclk_vio_pre_div: hclk_vio_pre_div {
1343 compatible = "rockchip,rk3188-div-con";
1344 rockchip,bits = <8 5>;
1345 clocks = <&hclk_vio_pre>;
1346 clock-output-names = "hclk_vio_pre";
1347 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1349 rockchip,clkops-idx =
1350 <CLKOPS_RATE_MUX_DIV>;
1351 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1354 /* reg[13]: reserved */
1356 hclk_vio_pre: hclk_vio_pre_mux {
1357 compatible = "rockchip,rk3188-mux-con";
1358 rockchip,bits = <14 2>;
1359 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1360 clock-output-names = "hclk_vio_pre";
1362 #clock-init-cells = <1>;
1367 clk_sel_con31: sel-con@00c0 {
1368 compatible = "rockchip,rk3188-selcon";
1370 #address-cells = <1>;
1373 aclk_vio0_pre_div: aclk_vio0_pre_div {
1374 compatible = "rockchip,rk3188-div-con";
1375 rockchip,bits = <0 5>;
1376 clocks = <&aclk_vio0_pre>;
1377 clock-output-names = "aclk_vio0_pre";
1378 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1380 rockchip,clkops-idx =
1381 <CLKOPS_RATE_MUX_DIV>;
1382 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1385 aclk_vio0_pre: aclk_vio0_pre_mux {
1386 compatible = "rockchip,rk3188-mux-con";
1387 rockchip,bits = <5 3>;
1388 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1389 clock-output-names = "aclk_vio0_pre";
1391 #clock-init-cells = <1>;
1394 aclk_vio1_pre_div: aclk_vio1_pre_div {
1395 compatible = "rockchip,rk3188-div-con";
1396 rockchip,bits = <8 5>;
1397 clocks = <&aclk_vio1_pre>;
1398 clock-output-names = "aclk_vio1_pre";
1399 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1401 rockchip,clkops-idx =
1402 <CLKOPS_RATE_MUX_DIV>;
1403 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1406 aclk_vio1_pre: aclk_vio1_pre_mux {
1407 compatible = "rockchip,rk3188-mux-con";
1408 rockchip,bits = <13 3>;
1409 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1410 clock-output-names = "aclk_vio1_pre";
1412 #clock-init-cells = <1>;
1417 clk_sel_con32: sel-con@00c4 {
1418 compatible = "rockchip,rk3188-selcon";
1420 #address-cells = <1>;
1423 clk_vepu_div: clk_vepu_div {
1424 compatible = "rockchip,rk3188-div-con";
1425 rockchip,bits = <0 5>;
1426 clocks = <&clk_vepu>;
1427 clock-output-names = "clk_vepu";
1428 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1430 rockchip,clkops-idx =
1431 <CLKOPS_RATE_MUX_DIV>;
1432 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1435 clk_vepu: clk_vepu_mux {
1436 compatible = "rockchip,rk3188-mux-con";
1437 rockchip,bits = <5 3>;
1438 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1439 clock-output-names = "clk_vepu";
1441 #clock-init-cells = <1>;
1444 clk_vdpu_div: clk_vdpu_div {
1445 compatible = "rockchip,rk3188-div-con";
1446 rockchip,bits = <8 5>;
1447 clocks = <&clk_vdpu>;
1448 clock-output-names = "clk_vdpu";
1449 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1451 rockchip,clkops-idx =
1452 <CLKOPS_RATE_MUX_DIV>;
1453 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1456 clk_vdpu: clk_vdpu_mux {
1457 compatible = "rockchip,rk3188-mux-con";
1458 rockchip,bits = <13 3>;
1459 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1460 clock-output-names = "clk_vdpu";
1462 #clock-init-cells = <1>;
1467 clk_sel_con34: sel-con@00cc {
1468 compatible = "rockchip,rk3188-selcon";
1470 #address-cells = <1>;
1473 clk_gpu_div: clk_gpu_div {
1474 compatible = "rockchip,rk3188-div-con";
1475 rockchip,bits = <0 5>;
1476 clocks = <&clk_gpu>;
1477 clock-output-names = "clk_gpu";
1478 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1480 rockchip,clkops-idx =
1481 <CLKOPS_RATE_MUX_DIV>;
1482 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1485 clk_gpu: clk_gpu_mux {
1486 compatible = "rockchip,rk3188-mux-con";
1487 rockchip,bits = <5 3>;
1488 clocks = <&dummy_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1489 clock-output-names = "clk_gpu";
1491 #clock-init-cells = <1>;
1494 clk_hevc_core_div: clk_hevc_core_div {
1495 compatible = "rockchip,rk3188-div-con";
1496 rockchip,bits = <8 5>;
1497 clocks = <&clk_hevc_core>;
1498 clock-output-names = "clk_hevc_core";
1499 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1501 rockchip,clkops-idx =
1502 <CLKOPS_RATE_MUX_DIV>;
1503 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1506 clk_hevc_core: clk_hevc_core_mux {
1507 compatible = "rockchip,rk3188-mux-con";
1508 rockchip,bits = <13 3>;
1509 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1510 clock-output-names = "clk_hevc_core";
1512 #clock-init-cells = <1>;
1520 /* Gate control regs */
1522 compatible = "rockchip,rk-gate-cons";
1523 #address-cells = <1>;
1527 clk_gates0: gate-clk@00d0{
1528 compatible = "rockchip,rk3188-gate-clk";
1531 <&clk_core>, <&dummy>,
1532 <&dummy>, <&aclk_cpu>,
1534 <&aclk_cpu>, <&aclk_cpu>,
1535 <&dummy>, <&clk_core>,
1537 <&dummy>, <&clk_i2s_2ch_pll>,
1538 <&i2s_2ch_frac>, <&hclk_vio_pre>,
1540 <&aclk_cpu>, <&clk_i2s_2ch_out>,
1541 <&clk_i2s_2ch>, <&dummy>;
1543 clock-output-names =
1544 "pclk_dbg", "aclk_cpu", /*clk_cpu_cpll*/
1545 "clk_ddr", "aclk_cpu_pre",
1547 "hclk_cpu_pre", "pclk_cpu_pre",
1548 "clk_core", "aclk_core_pre",
1550 "reserved", "clk_i2s_2ch_pll",
1551 "i2s_2ch_frac", "hclk_vio_pre",
1553 "clk_crypto", "clk_i2s_2ch_out",
1554 "clk_i2s_2ch", "clk_testout";
1555 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1560 clk_gates1: gate-clk@00d4{
1561 compatible = "rockchip,rk3188-gate-clk";
1564 <&clk_cpll>, <&dummy>,
1565 <&dummy>, <&jtag_tck>,
1567 <&aclk_vio1_pre>, <&xin12m>,
1568 <&xin12m>, <&clk_mac_pll>,
1570 <&clk_uart0_pll>, <&uart0_frac>,
1571 <&clk_uart1_div>, <&uart1_frac>,
1573 <&clk_uart2_div>, <&uart2_frac>,
1574 <&clk_tsp>, <&dummy>;
1576 clock-output-names =
1577 "pclk_pmu_pre", "reserved",
1578 "reserved", "clk_jtag",
1580 "aclk_vio1_pre", "clk_otgphy0",
1581 "clk_otgphy1", "clk_mac_pll",
1583 "clk_uart0_pll", "uart0_frac",
1584 "clk_uart1_div", "uart1_frac",
1586 "clk_uart2_div", "uart2_frac",
1587 "clk_tsp", "reserved";
1589 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1593 clk_gates2: gate-clk@00d8 {
1594 compatible = "rockchip,rk3188-gate-clk";
1597 <&aclk_peri>, <&aclk_peri>,
1598 <&aclk_peri>, <&aclk_peri>,
1600 <&clk_mac_ref>, <&clk_mac_ref>,
1601 <&clk_mac_ref>, <&clk_mac_ref>,
1603 <&clk_saradc>, <&clk_spi0>,
1604 <&clk_spdif_pll>, <&clk_sdmmc0>,
1606 <&spdif_frac>, <&clk_sdio>,
1607 <&clk_emmc>, <&xin24m>;
1608 clock-output-names =
1609 "aclk_peri", "aclk_peri_pre",
1610 "hclk_peri_pre", "pclk_peri_pre",
1612 "clk_mac_ref", "clk_mac_refout",
1613 "clk_mac_rx", "clk_mac_tx",
1615 "clk_saradc", "clk_spi0",
1616 "clk_spdif_pll", "clk_sdmmc0",
1618 "spdif_frac", "clk_sdio",
1619 "clk_emmc", "clk_mipi_24m";
1620 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1625 clk_gates3: gate-clk@00dc {
1626 compatible = "rockchip,rk3188-gate-clk";
1629 <&aclk_vio0_pre>, <&dclk_lcdc0>,
1630 <&sclk_lcdc0>, <&pclkin_cif>,
1632 <&dclk_ebc>, <&hclk_cpu_pre>,
1633 <&hclk_peri_pre>, <&clk_cif_pll>,
1635 <&pclk_cpu_pre>, <&clk_vepu>,
1636 <&clk_hevc_core>, <&clk_vdpu>,
1638 <&hclk_vdpu>, <&clk_gpu>,
1639 <&aclk_peri>, <&clk_sfc>;
1641 clock-output-names =
1642 "aclk_vio0_pre", "dclk_lcdc0",
1643 "sclk_lcdc0", "pclkin_cif",
1645 "dclk_ebc", "g_hclk_crypto",
1646 "g_hclk_em_peri", "clk_cif_pll",
1648 "g_pclk_hdmi", "clk_vepu",
1649 "clk_hevc_core", "clk_vdpu",
1651 "hclk_vdpu", "clk_gpu",
1652 "g_hclk_gps", "clk_sfc";
1653 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1658 clk_gates4: gate-clk@00e0{
1659 compatible = "rockchip,rk3188-gate-clk";
1662 <&hclk_peri_pre>, <&pclk_peri_pre>,
1663 <&aclk_peri>, <&aclk_peri>,
1665 <&clk_i2s_8ch_pll>, <&i2s_8ch_frac>,
1666 <&clk_i2s_8ch>, <&dummy>,
1669 <&aclk_cpu>, <&dummy>,
1671 <&aclk_cpu>, <&dummy>,
1674 clock-output-names =
1675 "g_hp_axi_matrix", "g_pp_axi_matrix",
1676 "g_aclk_cpu_peri", "g_ap_axi_matrix",
1678 "clk_i2s_8ch_pll", "i2s_8ch_frac",
1679 "clk_i2s_8ch", "reserved",
1681 "reserved", "reserved",
1682 "g_aclk_strc_sys", "reserved",
1684 /* Not use these ddr gates */
1685 "g_aclk_intmem", "reserved",
1686 "reserved", "reserved";
1688 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1692 clk_gates5: gate-clk@00e4 {
1693 compatible = "rockchip,rk3188-gate-clk";
1696 <&pclk_cpu_pre>, <&aclk_peri>,
1697 <&pclk_peri_pre>, <&dummy>,
1699 <&pclk_cpu_pre>, <&dummy>,
1700 <&hclk_cpu_pre>, <&pclk_cpu_pre>,
1702 <&dummy>, <&hclk_peri_pre>,
1703 <&hclk_peri_pre>, <&hclk_peri_pre>,
1705 <&dummy>, <&hclk_peri_pre>,
1706 <&pclk_cpu_pre>, <&dummy>;
1708 clock-output-names =
1709 "g_pclk_mipiphy", "g_aclk_dmac",
1710 "g_pclk_efuse", "reserved",
1712 "g_pclk_grf", "reserved",
1713 "g_hclk_rom", "g_pclk_ddrupctl",
1715 "reserved", "g_hclk_nandc",
1716 "g_hclk_sdmmc0", "g_hclk_sdio",
1718 "reserved", "g_hclk_otg0",
1719 "g_pclk_acodec", "reserved";
1721 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1726 clk_gates6: gate-clk@00e8 {
1727 compatible = "rockchip,rk3188-gate-clk";
1730 <&aclk_vio0_pre>, <&hclk_vio_pre>,
1733 <&hclk_vio_pre>, <&aclk_vio0_pre>,
1737 <&hclk_vio_pre>, <&aclk_vio0_pre>,
1739 <&hclk_vio_pre>, <&aclk_vio0_pre>,
1742 clock-output-names =
1743 "g_aclk_lcdc0", "g_hclk_lcdc0",
1744 "reserved", "reserved",
1746 "g_hclk_cif", "g_aclk_cif",
1747 "reserved", "reserved",
1749 "reserved", "reserved",
1750 "g_hclk_rga", "g_aclk_rga",
1752 "g_hclk_vio_bus", "g_aclk_vio",
1753 "reserved", "reserved";
1755 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1760 clk_gates7: gate-clk@00ec {
1761 compatible = "rockchip,rk3188-gate-clk";
1764 <&hclk_peri_pre>, <&hclk_peri_pre>,
1765 <&hclk_peri_pre>, <&hclk_peri_pre>,
1767 <&hclk_peri_pre>, <&dummy>,
1768 <&dummy>, <&pclk_peri_pre>,
1771 <&pclk_peri_pre>, <&dummy>,
1773 <&pclk_peri_pre>, <&dummy>,
1774 <&pclk_peri_pre>, <&pclk_peri_pre>;
1776 clock-output-names =
1777 "g_hclk_emmc", "g_hclk_sfc",
1778 "g_hclk_i2s_2ch", "g_hclk_host",
1780 "g_hclk_i2s_8ch", "reserved",
1781 "reserved", "g_pclk_timer",
1783 "reserved", "reserved",
1784 "g_pclk_pwm", "reserved",
1786 "g_pclk_spi0", "reserved",
1787 "g_pclk_saradc", "g_pclk_wdt";
1789 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1794 clk_gates8: gate-clk@00f0 {
1795 compatible = "rockchip,rk3188-gate-clk";
1798 <&pclk_peri_pre>, <&pclk_peri_pre>,
1799 <&pclk_peri_pre>, <&dummy>,
1801 <&pclk_peri_pre>, <&pclk_peri_pre>,
1802 <&pclk_peri_pre>, <&pclk_peri_pre>,
1804 <&dummy>, <&pclk_peri_pre>,
1805 <&pclk_peri_pre>, <&pclk_peri_pre>,
1807 <&pclk_peri_pre>, <&dummy>,
1810 clock-output-names =
1811 "g_pclk_uart0", "g_pclk_uart1",
1812 "g_pclk_uart2", "reserved",
1814 "g_pclk_i2c0", "g_pclk_i2c1",
1815 "g_pclk_i2c2", "g_pclk_i2c3",
1817 "reserved", "g_pclk_gpio0",
1818 "g_pclk_gpio1", "g_pclk_gpio2",
1820 "g_pclk_gpio3", "reserved",
1821 "reserved", "reserved";
1823 rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
1827 clk_gates9: gate-clk@00f4 {
1828 compatible = "rockchip,rk3188-gate-clk";
1832 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
1834 <&dummy>, <&hclk_vio_pre>,
1835 <&hclk_vio_pre>, <&hclk_vio_pre>,
1837 <&aclk_vio1_pre>, <&hclk_vio_pre>,
1838 <&aclk_vio1_pre>, <&dummy>,
1840 <&pclk_peri_pre>, <&hclk_peri_pre>,
1841 <&hclk_peri_pre>, <&aclk_peri>;
1843 clock-output-names =
1844 "reserved", "reserved",
1845 "g_pclk_pmu", "g_pclk_pmu_noc",
1847 "reserved", "g_hclk_vio_h2p",
1848 "g_pclk_mipi", "g_hclk_iep",
1850 "g_aclk_iep", "g_hclk_ebc",
1851 "g_aclk_vio1_niu", "reserved",
1853 "g_pclk_sim_card", "g_hclk_usb_peri",
1854 "g_hclk_pe_arbi", "g_aclk_peri_niu";
1856 rockchip,suspend-clkgating-setting=<0x0 0x0>;
1861 clk_gates10: gate-clk@00f8 {
1862 compatible = "rockchip,rk3188-gate-clk";
1865 <&xin24m>, <&xin24m>,
1866 <&xin24m>, <&xin24m>,
1868 <&xin24m>, <&xin24m>,
1869 <&xin24m>, <&xin24m>,
1871 <&xin24m>, <&hclk_peri_pre>,
1872 <&aclk_peri>, <&pclk_peri_pre>,
1874 <&hclk_peri_pre>, <&clk_tsp_in>,
1875 <&hclk_peri_pre>, <&clk_nandc>;
1877 clock-output-names =
1878 "clk_pvtm_core", "clk_pvtm_gpu",
1879 "clk_pvtm_func", "clk_timer0",
1881 "clk_timer1", "clk_timer2",
1882 "clk_timer3", "clk_timer4",
1884 "clk_timer5", "g_hclk_spdif",
1885 "g_aclk_gmac", "g_pclk_gmac",
1887 "g_hclk_tsp", "g_clkin0_tsp",
1888 "g_hclk_usbhost", "clk_nandc";
1890 rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */