2 * Copyright (C) 2014 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk312x.h>
19 compatible = "rockchip,rk-clocks";
22 ranges = <0x0 0x20000000 0x1f0>;
25 compatible = "rockchip,rk-fixed-rate-cons";
28 compatible = "rockchip,rk-fixed-clock";
29 clock-output-names = "xin24m";
30 clock-frequency = <24000000>;
35 compatible = "rockchip,rk-fixed-clock";
37 clock-output-names = "xin12m";
38 clock-frequency = <12000000>;
42 gmac_clkin: gmac_clkin {
43 compatible = "rockchip,rk-fixed-clock";
44 clock-output-names = "gmac_clkin";
45 clock-frequency = <125000000>;
50 compatible = "rockchip,rk-fixed-clock";
51 clock-output-names = "usb480m";
52 clock-frequency = <480000000>;
56 i2s_clkin: i2s_clkin {
57 compatible = "rockchip,rk-fixed-clock";
58 clock-output-names = "i2s_clkin";
59 clock-frequency = <0>;
64 compatible = "rockchip,rk-fixed-clock";
65 clock-output-names = "jtag_tck";
66 clock-frequency = <0>;
70 pclkin_cif: pclkin_cif {
71 compatible = "rockchip,rk-fixed-clock";
72 clock-output-names = "pclkin_cif";
73 clock-frequency = <0>;
77 clk_tsp_in: clk_tsp_in {
78 compatible = "rockchip,rk-fixed-clock";
79 clock-output-names = "clk_tsp_in";
80 clock-frequency = <0>;
86 compatible = "rockchip,rk-fixed-clock";
87 clock-output-names = "dummy";
88 clock-frequency = <0>;
92 dummy_cpll: dummy_cpll {
93 compatible = "rockchip,rk-fixed-clock";
94 clock-output-names = "dummy_cpll";
95 clock-frequency = <0>;
102 compatible = "rockchip,rk-fixed-factor-cons";
104 clk_gpll_div2: clk_gpll_div2 {
105 compatible = "rockchip,rk-fixed-factor-clock";
106 clocks = <&clk_gpll>;
107 clock-output-names = "clk_gpll_div2";
113 clk_gpll_div3: clk_gpll_div3 {
114 compatible = "rockchip,rk-fixed-factor-clock";
115 clocks = <&clk_gpll>;
116 clock-output-names = "clk_gpll_div3";
122 g_clk_pvtm_func: g_clk_pvtm_func {
123 compatible = "rockchip,rk-fixed-factor-clock";
125 clock-output-names = "g_clk_pvtm_func";
131 hclk_vepu: hclk_vepu {
132 compatible = "rockchip,rk-fixed-factor-clock";
133 clocks = <&clk_vepu>;
134 clock-output-names = "hclk_vepu";
140 hclk_vdpu: hclk_vdpu {
141 compatible = "rockchip,rk-fixed-factor-clock";
142 clocks = <&clk_vdpu>;
143 clock-output-names = "hclk_vdpu";
149 pclkin_cif_inv: pclkin_cif_inv {
150 compatible = "rockchip,rk-fixed-factor-clock";
151 clocks = <&clk_gates3 3>;
152 clock-output-names = "pclkin_cif_inv";
158 hclk_vio_niu: hclk_vio_niu {
159 compatible = "rockchip,rk-fixed-factor-clock";
160 clocks = <&hclk_vio_pre>;
161 clock-output-names = "hclk_vio_niu";
167 aclk_vio0_niu: aclk_vio0_niu {
168 compatible = "rockchip,rk-fixed-factor-clock";
169 clocks = <&aclk_vio0_pre>;
170 clock-output-names = "aclk_vio0_niu";
176 aclk_vio1_niu: aclk_vio1_niu {
177 compatible = "rockchip,rk-fixed-factor-clock";
178 clocks = <&aclk_vio1_pre>;
179 clock-output-names = "aclk_vio1_niu";
188 compatible = "rockchip,rk-pd-cons";
191 compatible = "rockchip,rk-pd-clock";
192 clock-output-names = "pd_gpu";
193 rockchip,pd-id = <CLK_PD_GPU>;
198 compatible = "rockchip,rk-pd-clock";
199 clock-output-names = "pd_video";
200 rockchip,pd-id = <CLK_PD_VIDEO>;
205 compatible = "rockchip,rk-pd-clock";
206 clock-output-names = "pd_vio";
207 rockchip,pd-id = <CLK_PD_VIO>;
212 compatible = "rockchip,rk-pd-clock";
214 clock-output-names = "pd_vop";
215 rockchip,pd-id = <CLK_PD_VIRT>;
220 compatible = "rockchip,rk-pd-clock";
222 clock-output-names = "pd_vip";
223 rockchip,pd-id = <CLK_PD_VIRT>;
228 compatible = "rockchip,rk-pd-clock";
230 clock-output-names = "pd_iep";
231 rockchip,pd-id = <CLK_PD_VIRT>;
236 compatible = "rockchip,rk-pd-clock";
238 clock-output-names = "pd_rga";
239 rockchip,pd-id = <CLK_PD_VIRT>;
244 compatible = "rockchip,rk-pd-clock";
246 clock-output-names = "pd_ebc";
247 rockchip,pd-id = <CLK_PD_VIRT>;
251 pd_mipidsi: pd_mipidsi {
252 compatible = "rockchip,rk-pd-clock";
254 clock-output-names = "pd_mipidsi";
255 rockchip,pd-id = <CLK_PD_VIRT>;
260 compatible = "rockchip,rk-pd-clock";
262 clock-output-names = "pd_hdmi";
263 rockchip,pd-id = <CLK_PD_VIRT>;
271 compatible = "rockchip,rk-clock-regs";
272 #address-cells = <1>;
274 reg = <0x0000 0x01f0>;
277 /* PLL control regs */
279 compatible = "rockchip,rk-pll-cons";
280 #address-cells = <1>;
284 clk_apll: pll-clk@0000 {
285 compatible = "rockchip,rk3188-pll-clk";
287 mode-reg = <0x0040 0>;
288 status-reg = <0x0004 10>;
290 clock-output-names = "clk_apll";
291 rockchip,pll-type = <CLK_PLL_3036_APLL>;
295 clk_dpll: pll-clk@0010 {
296 compatible = "rockchip,rk3188-pll-clk";
298 mode-reg = <0x0040 4>;
299 status-reg = <0x0014 10>;
301 clock-output-names = "clk_dpll";
302 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
306 clk_cpll: pll-clk@0020 {
307 compatible = "rockchip,rk3188-pll-clk";
309 mode-reg = <0x0040 8>;
310 status-reg = <0x0024 10>;
312 clock-output-names = "clk_cpll";
313 rockchip,pll-type = <CLK_PLL_312XPLUS>;
315 #clock-init-cells = <1>;
318 clk_gpll: pll-clk@0030 {
319 compatible = "rockchip,rk3188-pll-clk";
321 mode-reg = <0x0040 12>;
322 status-reg = <0x0034 10>;
324 clock-output-names = "clk_gpll";
325 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
327 #clock-init-cells = <1>;
332 /* Select control regs */
334 compatible = "rockchip,rk-sel-cons";
335 #address-cells = <1>;
339 clk_sel_con0: sel-con@0044 {
340 compatible = "rockchip,rk3188-selcon";
342 #address-cells = <1>;
345 clk_core_div: clk_core_div {
346 compatible = "rockchip,rk3188-div-con";
347 rockchip,bits = <0 5>;
348 clocks = <&clk_core>;
349 clock-output-names = "clk_core";
350 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
352 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
353 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
354 CLK_SET_RATE_NO_REPARENT)>;
357 /* reg[6:5]: reserved */
359 clk_core: clk_core_mux {
360 compatible = "rockchip,rk3188-mux-con";
361 rockchip,bits = <7 1>;
362 clocks = <&clk_apll>, <&clk_gpll_div2>;
363 clock-output-names = "clk_core";
365 #clock-init-cells = <1>;
368 aclk_cpu_div: aclk_cpu_div {
369 compatible = "rockchip,rk3188-div-con";
370 rockchip,bits = <8 5>;
371 clocks = <&aclk_cpu>;
372 clock-output-names = "aclk_cpu";
373 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
375 rockchip,clkops-idx =
376 <CLKOPS_RATE_MUX_DIV>;
377 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
380 aclk_cpu: aclk_cpu_mux {
381 compatible = "rockchip,rk3188-mux-con";
382 rockchip,bits = <13 2>;
383 clocks = <&clk_apll>, <&clk_gpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
384 clock-output-names = "aclk_cpu";
386 #clock-init-cells = <1>;
389 /* reg[15]: reserved */
393 clk_sel_con1: sel-con@0048 {
394 compatible = "rockchip,rk3188-selcon";
396 #address-cells = <1>;
399 pclk_dbg_div: pclk_dbg_div {
400 compatible = "rockchip,rk3188-div-con";
401 rockchip,bits = <0 4>;
402 clocks = <&clk_core>;
403 clock-output-names = "pclk_dbg";
404 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
406 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
409 aclk_core_pre: aclk_core_pre_div {
410 compatible = "rockchip,rk3188-div-con";
411 rockchip,bits = <4 3>;
412 clocks = <&clk_core>;
413 clock-output-names = "aclk_core_pre";
414 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
416 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
419 /* reg[7]: reserved */
421 hclk_cpu_pre: hclk_cpu_pre_div {
422 compatible = "rockchip,rk3188-div-con";
423 rockchip,bits = <8 2>;
424 clocks = <&aclk_cpu>;
425 clock-output-names = "hclk_cpu_pre";
426 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
428 #clock-init-cells = <1>;
431 /* reg[11:10]: reserved */
433 pclk_cpu_pre: pclk_cpu_pre_div {
434 compatible = "rockchip,rk3188-div-con";
435 rockchip,bits = <12 3>;
436 clocks = <&aclk_cpu>;
437 clock-output-names = "pclk_cpu_pre";
438 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
440 #clock-init-cells = <1>;
443 /* reg[15]: reserved */
446 clk_sel_con2: sel-con@004c {
447 compatible = "rockchip,rk3188-selcon";
449 #address-cells = <1>;
452 clk_pvtm_div: clk_pvtm_div {
453 compatible = "rockchip,rk3188-mux-con";
454 rockchip,bits = <0 7>;
455 clocks = <&g_clk_pvtm_func>;
456 clock-output-names = "clk_pvtm";
457 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
459 #clock-init-cells = <1>;
462 /* reg[7]: reserved */
464 clk_nandc_div: clk_nandc_div {
465 compatible = "rockchip,rk3188-div-con";
466 rockchip,bits = <8 5>;
467 clocks = <&clk_nandc>;
468 clock-output-names = "clk_nandc";
469 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
471 rockchip,clkops-idx =
472 <CLKOPS_RATE_MUX_DIV>;
475 /* reg[13]: reserved */
477 clk_nandc: clk_nandc_mux {
478 compatible = "rockchip,rk3188-mux-con";
479 rockchip,bits = <14 2>;
480 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
481 clock-output-names = "clk_nandc";
483 #clock-init-cells = <1>;
488 clk_sel_con3: sel-con@0050 {
489 compatible = "rockchip,rk3188-selcon";
491 #address-cells = <1>;
494 clk_i2s_2ch_pll_div: clk_i2s_2ch_pll_div {
495 compatible = "rockchip,rk3188-div-con";
496 rockchip,bits = <0 7>;
497 clocks = <&clk_i2s_2ch_pll>;
498 clock-output-names = "clk_i2s_2ch_pll";
499 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
501 rockchip,clkops-idx =
502 <CLKOPS_RATE_MUX_DIV>;
503 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
506 /* reg[7]: reserved */
508 clk_i2s_2ch: clk_i2s_2ch_mux {
509 compatible = "rockchip,rk3188-mux-con";
510 rockchip,bits = <8 2>;
511 clocks = <&clk_i2s_2ch_pll_div>, <&i2s_2ch_frac>, <&i2s_clkin>, <&xin12m>;
512 clock-output-names = "clk_i2s_2ch";
514 rockchip,clkops-idx =
515 <CLKOPS_RATE_RK3288_I2S>;
516 rockchip,flags = <CLK_SET_RATE_PARENT>;
519 /* reg[11:10]: reserved */
521 clk_i2s_2ch_out: clk_i2s_2ch_out_mux {
522 compatible = "rockchip,rk3188-mux-con";
523 rockchip,bits = <12 1>;
524 clocks = <&clk_i2s_2ch>, <&xin12m>;
525 clock-output-names = "i2s_clkout";
529 /* reg[13]: reserved */
531 clk_i2s_2ch_pll: i2s_2ch_pll_mux {
532 compatible = "rockchip,rk3188-mux-con";
533 rockchip,bits = <14 2>;
534 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
535 clock-output-names = "clk_i2s_2ch_pll";
537 #clock-init-cells = <1>;
542 clk_sel_con4: sel-con@0054 {
543 compatible = "rockchip,rk3188-selcon";
545 #address-cells = <1>;
548 clk_tsp_div: clk_tsp_div {
549 compatible = "rockchip,rk3188-div-con";
550 rockchip,bits = <0 5>;
552 clock-output-names = "clk_tsp";
553 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
555 rockchip,clkops-idx =
556 <CLKOPS_RATE_MUX_DIV>;
559 /* reg[5]: reserved */
561 clk_tsp: clk_tsp_mux {
562 compatible = "rockchip,rk3188-mux-con";
563 rockchip,bits = <6 2>;
564 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
565 clock-output-names = "clk_tsp";
567 #clock-init-cells = <1>;
570 clk_24m_div: clk_24m_div {
571 compatible = "rockchip,rk3188-div-con";
572 rockchip,bits = <8 5>;
574 clock-output-names = "clk_24m";
575 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
579 /* reg[15:13]: reserved */
584 clk_sel_con5: sel-con@0058 {
585 compatible = "rockchip,rk3188-selcon";
587 #address-cells = <1>;
590 clk_mac_pll_div: clk_mac_pll_div {
591 compatible = "rockchip,rk3188-div-con";
592 rockchip,bits = <0 5>;
593 clocks = <&clk_mac_pll>;
594 clock-output-names = "clk_mac_pll";
595 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
597 rockchip,clkops-idx =
598 <CLKOPS_RATE_MUX_DIV>;
599 #clock-init-cells = <1>;
602 /* reg[5]: reserved */
604 clk_mac_pll: clk_mac_pll_mux {
605 compatible = "rockchip,rk3188-mux-con";
606 rockchip,bits = <6 2>;
607 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
608 clock-output-names = "clk_mac_pll";
610 #clock-init-cells = <1>;
613 /* reg[14:8]: reserved */
615 clk_mac_ref: clk_mac_ref_mux {
616 compatible = "rockchip,rk3188-mux-con";
617 rockchip,bits = <15 1>;
618 clocks = <&clk_mac_pll_div>, <&gmac_clkin>;
619 clock-output-names = "clk_mac_ref";
621 rockchip,clkops-idx =
622 <CLKOPS_RATE_MAC_REF>;
623 rockchip,flags = <CLK_SET_RATE_PARENT>;
624 #clock-init-cells = <1>;
630 clk_sel_con6: sel-con@005c {
631 compatible = "rockchip,rk3188-selcon";
633 #address-cells = <1>;
636 spdif_div: spdif_div {
637 compatible = "rockchip,rk3188-div-con";
638 rockchip,bits = <0 7>;
639 clocks = <&clk_spdif_pll>;
640 clock-output-names = "clk_spdif_pll";
641 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
643 rockchip,clkops-idx =
644 <CLKOPS_RATE_MUX_DIV>;
645 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
648 /* reg[7]: reserved */
650 clk_spdif: spdif_mux {
651 compatible = "rockchip,rk3188-mux-con";
652 rockchip,bits = <8 2>;
653 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
654 clock-output-names = "clk_spdif";
656 rockchip,clkops-idx =
657 <CLKOPS_RATE_RK3288_I2S>;
658 rockchip,flags = <CLK_SET_RATE_PARENT>;
661 /* reg[13:10]: reserved */
663 clk_spdif_pll: spdif_pll_mux {
664 compatible = "rockchip,rk3188-mux-con";
665 rockchip,bits = <14 2>;
666 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
667 clock-output-names = "clk_spdif_pll";
669 #clock-init-cells = <1>;
674 clk_sel_con7: sel-con@0060 {
675 compatible = "rockchip,rk3188-selcon";
677 #address-cells = <1>;
680 i2s_2ch_frac: i2s_2ch_frac {
681 compatible = "rockchip,rk3188-frac-con";
682 clocks = <&clk_i2s_2ch_pll>;
683 clock-output-names = "i2s_2ch_frac";
684 /* numerator denominator */
685 rockchip,bits = <0 32>;
686 rockchip,clkops-idx =
692 clk_sel_con8: sel-con@0064 {
693 compatible = "rockchip,rk3188-selcon";
695 #address-cells = <1>;
698 i2s_8ch_frac: i2s_8ch_frac {
699 compatible = "rockchip,rk3188-frac-con";
700 clocks = <&clk_i2s_8ch_pll>;
701 clock-output-names = "i2s_8ch_frac";
702 /* numerator denominator */
703 rockchip,bits = <0 32>;
704 rockchip,clkops-idx =
710 clk_sel_con9: sel-con@0068 {
711 compatible = "rockchip,rk3188-selcon";
713 #address-cells = <1>;
716 clk_i2s_8ch_pll_div: clk_i2s_8ch_pll_div {
717 compatible = "rockchip,rk3188-div-con";
718 rockchip,bits = <0 7>;
719 clocks = <&clk_i2s_8ch_pll>;
720 clock-output-names = "clk_i2s_8ch_pll";
721 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
723 rockchip,clkops-idx =
724 <CLKOPS_RATE_MUX_DIV>;
725 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
728 /* reg[7]: reserved */
730 clk_i2s_8ch: clk_i2s_8ch_mux {
731 compatible = "rockchip,rk3188-mux-con";
732 rockchip,bits = <8 2>;
733 clocks = <&clk_i2s_8ch_pll_div>, <&i2s_8ch_frac>, <&i2s_clkin>, <&xin12m>;
734 clock-output-names = "clk_i2s_8ch";
736 rockchip,clkops-idx =
737 <CLKOPS_RATE_RK3288_I2S>;
738 rockchip,flags = <CLK_SET_RATE_PARENT>;
741 /* reg[13:10]: reserved */
743 clk_i2s_8ch_pll: i2s_8ch_pll_mux {
744 compatible = "rockchip,rk3188-mux-con";
745 rockchip,bits = <14 2>;
746 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
747 clock-output-names = "clk_i2s_8ch_pll";
749 #clock-init-cells = <1>;
754 clk_sel_con10: sel-con@006c {
755 compatible = "rockchip,rk3188-selcon";
757 #address-cells = <1>;
760 aclk_peri_div: aclk_peri_div {
761 compatible = "rockchip,rk3188-div-con";
762 rockchip,bits = <0 5>;
763 clocks = <&aclk_peri>;
764 clock-output-names = "aclk_peri";
765 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
767 rockchip,clkops-idx =
768 <CLKOPS_RATE_MUX_DIV>;
769 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
772 /* reg[7:5]: reserved */
774 hclk_peri_pre: hclk_peri_pre_div {
775 compatible = "rockchip,rk3188-div-con";
776 rockchip,bits = <8 2>;
777 clocks = <&aclk_peri>;
778 clock-output-names = "hclk_peri_pre";
779 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
780 rockchip,div-relations =
785 #clock-init-cells = <1>;
788 /* reg[11:10]: reserved */
790 pclk_peri_pre: pclk_peri_div {
791 compatible = "rockchip,rk3188-div-con";
792 rockchip,bits = <12 2>;
793 clocks = <&aclk_peri>;
794 clock-output-names = "pclk_peri_pre";
795 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
796 rockchip,div-relations =
802 #clock-init-cells = <1>;
805 aclk_peri: aclk_peri_mux {
806 compatible = "rockchip,rk3188-mux-con";
807 rockchip,bits = <14 2>;
808 clocks = <&clk_gpll>,<&clk_cpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
809 clock-output-names = "aclk_peri";
811 #clock-init-cells = <1>;
815 clk_sel_con11: sel-con@0070 {
816 compatible = "rockchip,rk3188-selcon";
818 #address-cells = <1>;
821 clk_sdmmc0_div: clk_sdmmc0_div {
822 compatible = "rockchip,rk3188-div-con";
823 rockchip,bits = <0 6>;
824 clocks = <&clk_sdmmc0>;
825 clock-output-names = "clk_sdmmc0";
826 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
828 rockchip,clkops-idx =
829 <CLKOPS_RATE_MUX_EVENDIV>;
832 clk_sdmmc0: clk_sdmmc0_mux {
833 compatible = "rockchip,rk3188-mux-con";
834 rockchip,bits = <6 2>;
835 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
836 clock-output-names = "clk_sdmmc0";
838 #clock-init-cells = <1>;
841 clk_sfc_div: clk_sfc_div {
842 compatible = "rockchip,rk3188-div-con";
843 rockchip,bits = <8 5>;
845 clock-output-names = "clk_sfc";
846 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
848 rockchip,clkops-idx =
849 <CLKOPS_RATE_MUX_EVENDIV>;
852 /* reg[13]: reserved */
854 clk_sfc: clk_sfc_mux {
855 compatible = "rockchip,rk3188-mux-con";
856 rockchip,bits = <14 2>;
857 clocks = <&clk_cpll>,<&clk_gpll>,<&clk_gpll_div2>,<&xin24m>;
858 clock-output-names = "clk_sfc";
860 #clock-init-cells = <1>;
865 clk_sel_con12: sel-con@0074 {
866 compatible = "rockchip,rk3188-selcon";
868 #address-cells = <1>;
871 clk_sdio_div: clk_sdio_div {
872 compatible = "rockchip,rk3188-div-con";
873 rockchip,bits = <0 6>;
874 clocks = <&clk_sdio>;
875 clock-output-names = "clk_sdio";
876 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
878 rockchip,clkops-idx =
879 <CLKOPS_RATE_MUX_EVENDIV>;
882 clk_sdio: clk_sdio_mux {
883 compatible = "rockchip,rk3188-mux-con";
884 rockchip,bits = <6 2>;
885 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
886 clock-output-names = "clk_sdio";
888 #clock-init-cells = <1>;
891 clk_emmc_div: clk_emmc_div {
892 compatible = "rockchip,rk3188-div-con";
893 rockchip,bits = <8 6>;
894 clocks = <&clk_emmc>;
895 clock-output-names = "clk_emmc";
896 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
898 rockchip,clkops-idx =
899 <CLKOPS_RATE_MUX_EVENDIV>;
902 clk_emmc: clk_emmc_mux {
903 compatible = "rockchip,rk3188-mux-con";
904 rockchip,bits = <14 2>;
905 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
906 clock-output-names = "clk_emmc";
908 #clock-init-cells = <1>;
913 clk_sel_con13: sel-con@0078 {
914 compatible = "rockchip,rk3188-selcon";
916 #address-cells = <1>;
919 clk_uart0_pll_div: clk_uart0_pll_div {
920 compatible = "rockchip,rk3188-div-con";
921 rockchip,bits = <0 7>;
922 clocks = <&clk_uart0_pll>;
923 clock-output-names = "clk_uart0_pll";
924 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
928 /* reg[7]: reserved */
930 clk_uart0: clk_uart0_mux {
931 compatible = "rockchip,rk3188-mux-con";
932 rockchip,bits = <8 2>;
933 clocks = <&clk_uart0_pll>, <&uart0_frac>, <&xin24m>;
934 clock-output-names = "clk_uart0";
936 rockchip,clkops-idx =
937 <CLKOPS_RATE_RK3288_I2S>;
938 rockchip,flags = <CLK_SET_RATE_PARENT>;
941 /* reg[11:10]: reserved */
943 clk_uart0_pll: clk_uart0_pll_mux {
944 compatible = "rockchip,rk3188-mux-con";
945 rockchip,bits = <12 2>;
946 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
947 clock-output-names = "clk_uart0_pll";
949 #clock-init-cells = <1>;
952 clk_uart2_pll: clk_uart2_pll_mux {
953 compatible = "rockchip,rk3188-mux-con";
954 rockchip,bits = <14 2>;
955 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
956 clock-output-names = "clk_uart2_pll";
958 #clock-init-cells = <1>;
963 clk_sel_con14: sel-con@007c {
964 compatible = "rockchip,rk3188-selcon";
966 #address-cells = <1>;
969 clk_uart1_div: clk_uart1_div {
970 compatible = "rockchip,rk3188-div-con";
971 rockchip,bits = <0 7>;
972 clocks = <&clk_uart2_pll>;
973 clock-output-names = "clk_uart1_div";
974 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
978 /* reg[7]: reserved */
980 clk_uart1: clk_uart1_mux {
981 compatible = "rockchip,rk3188-mux-con";
982 rockchip,bits = <8 2>;
983 clocks = <&clk_uart1_div>, <&uart1_frac>, <&xin24m>;
984 clock-output-names = "clk_uart1";
986 rockchip,clkops-idx =
987 <CLKOPS_RATE_RK3288_I2S>;
988 rockchip,flags = <CLK_SET_RATE_PARENT>;
991 /* reg[15:10]: reserved */
994 clk_sel_con15: sel-con@0080 {
995 compatible = "rockchip,rk3188-selcon";
997 #address-cells = <1>;
1000 clk_uart2_div: clk_uart2_div {
1001 compatible = "rockchip,rk3188-div-con";
1002 rockchip,bits = <0 7>;
1003 clocks = <&clk_uart2_pll>;
1004 clock-output-names = "clk_uart2_div";
1005 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1009 /* reg[7]: reserved */
1011 clk_uart2: clk_uart2_mux {
1012 compatible = "rockchip,rk3188-mux-con";
1013 rockchip,bits = <8 2>;
1014 clocks = <&clk_uart2_div>, <&uart2_frac>, <&xin24m>;
1015 clock-output-names = "clk_uart2";
1017 rockchip,clkops-idx =
1018 <CLKOPS_RATE_RK3288_I2S>;
1019 rockchip,flags = <CLK_SET_RATE_PARENT>;
1022 /* reg[15:10]: reserved */
1025 clk_sel_con17: sel-con@0088 {
1026 compatible = "rockchip,rk3188-selcon";
1028 #address-cells = <1>;
1031 uart0_frac: uart0_frac {
1032 compatible = "rockchip,rk3188-frac-con";
1033 clocks = <&clk_uart0_pll>;
1034 clock-output-names = "uart0_frac";
1035 /* numerator denominator */
1036 rockchip,bits = <0 32>;
1037 rockchip,clkops-idx =
1043 clk_sel_con18: sel-con@008c {
1044 compatible = "rockchip,rk3188-selcon";
1046 #address-cells = <1>;
1049 uart1_frac: uart1_frac {
1050 compatible = "rockchip,rk3188-frac-con";
1051 clocks = <&clk_uart1_div>;
1052 clock-output-names = "uart1_frac";
1053 /* numerator denominator */
1054 rockchip,bits = <0 32>;
1055 rockchip,clkops-idx =
1061 clk_sel_con19: sel-con@0090 {
1062 compatible = "rockchip,rk3188-selcon";
1064 #address-cells = <1>;
1067 uart2_frac: uart2_frac {
1068 compatible = "rockchip,rk3188-frac-con";
1069 clocks = <&clk_uart2_div>;
1070 clock-output-names = "uart2_frac";
1071 /* numerator denominator */
1072 rockchip,bits = <0 32>;
1073 rockchip,clkops-idx =
1080 clk_sel_con20: sel-con@0094 {
1081 compatible = "rockchip,rk3188-selcon";
1083 #address-cells = <1>;
1086 spdif_frac: spdif_frac {
1087 compatible = "rockchip,rk3188-frac-con";
1088 clocks = <&spdif_div>;
1089 clock-output-names = "spdif_frac";
1090 /* numerator denominator */
1091 rockchip,bits = <0 32>;
1092 rockchip,clkops-idx =
1099 clk_sel_con23: sel-con@00a0 {
1100 compatible = "rockchip,rk3188-selcon";
1102 #address-cells = <1>;
1105 dclk_ebc: dclk_ebc_mux {
1106 compatible = "rockchip,rk3188-mux-con";
1107 rockchip,bits = <0 2>;
1108 clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
1109 clock-output-names = "dclk_ebc";
1111 #clock-init-cells = <1>;
1114 /* reg[7:2]: reserved */
1116 dclk_ebc_div: dclk_ebc_div {
1117 compatible = "rockchip,rk3188-div-con";
1118 rockchip,bits = <8 8>;
1119 clocks = <&dclk_ebc>;
1120 clock-output-names = "dclk_ebc";
1121 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1123 rockchip,clkops-idx =
1124 <CLKOPS_RATE_MUX_DIV>;
1129 clk_sel_con24: sel-con@00a4 {
1130 compatible = "rockchip,rk3188-selcon";
1132 #address-cells = <1>;
1135 clk_crypto_div: clk_crypto_div {
1136 compatible = "rockchip,rk3188-div-con";
1137 rockchip,bits = <0 2>;
1138 clocks = <&aclk_cpu>;
1139 clock-output-names = "clk_crypto";
1140 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1142 #clock-init-cells = <1>;
1145 /* reg[7:2]: reserved */
1147 clk_saradc: clk_saradc_div {
1148 compatible = "rockchip,rk3188-div-con";
1149 rockchip,bits = <8 8>;
1151 clock-output-names = "clk_saradc";
1152 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1154 #clock-init-cells = <1>;
1159 clk_sel_con25: sel-con@00a8 {
1160 compatible = "rockchip,rk3188-selcon";
1162 #address-cells = <1>;
1165 clk_spi0_div: clk_spi0_div {
1166 compatible = "rockchip,rk3188-div-con";
1167 rockchip,bits = <0 7>;
1168 clocks = <&clk_spi0>;
1169 clock-output-names = "clk_spi0";
1170 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1172 rockchip,clkops-idx =
1173 <CLKOPS_RATE_MUX_DIV>;
1176 /* reg[7]: reserved */
1178 clk_spi0: clk_spi0_mux {
1179 compatible = "rockchip,rk3188-mux-con";
1180 rockchip,bits = <8 2>;
1181 clocks = <&clk_cpll>, <&clk_gpll>,<&clk_gpll_div2>;
1182 clock-output-names = "clk_spi0";
1186 /* reg[15:10]: reserved */
1190 clk_sel_con26: sel-con@00ac {
1191 compatible = "rockchip,rk3188-selcon";
1193 #address-cells = <1>;
1197 compatible = "rockchip,rk3188-div-con";
1198 rockchip,bits = <0 2>;
1199 clocks = <&clk_ddr>;
1200 clock-output-names = "clk_ddr";
1201 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1202 rockchip,div-relations =
1207 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1208 CLK_SET_RATE_NO_REPARENT)>;
1209 rockchip,clkops-idx = <CLKOPS_RATE_DDR_DIV2>;
1212 /* reg[7:2]: reserved */
1214 clk_ddr: ddr_clk_pll_mux {
1215 compatible = "rockchip,rk3188-mux-con";
1216 rockchip,bits = <8 1>;
1217 clocks = <&clk_dpll>, <&dummy>;
1218 clock-output-names = "clk_ddr";
1222 /* reg[15:9]: reserved */
1225 clk_sel_con27: sel-con@00b0 {
1226 compatible = "rockchip,rk3188-selcon";
1228 #address-cells = <1>;
1231 dclk_lcdc0: dclk_lcdc0_mux {
1232 compatible = "rockchip,rk3188-mux-con";
1233 rockchip,bits = <0 2>;
1234 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1235 clock-output-names = "dclk_lcdc0";
1237 #clock-init-cells = <1>;
1240 /* reg[7:2]: reserved */
1242 dclk_lcdc0_div: dclk_lcdc0_div {
1243 compatible = "rockchip,rk3188-div-con";
1244 rockchip,bits = <8 8>;
1245 clocks = <&dclk_lcdc0>;
1246 clock-output-names = "dclk_lcdc0";
1247 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1249 rockchip,clkops-idx =
1250 <CLKOPS_RATE_MUX_DIV>;
1251 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1255 clk_sel_con28: sel-con@00b4 {
1256 compatible = "rockchip,rk3188-selcon";
1258 #address-cells = <1>;
1261 sclk_lcdc0: sclk_lcdc0_mux {
1262 compatible = "rockchip,rk3188-mux-con";
1263 rockchip,bits = <0 2>;
1264 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>;
1265 clock-output-names = "sclk_lcdc0";
1267 #clock-init-cells = <1>;
1270 /* reg[7:2]: reserved */
1272 sclk_lcdc0_div: sclk_lcdc0_div {
1273 compatible = "rockchip,rk3188-div-con";
1274 rockchip,bits = <8 8>;
1275 clocks = <&sclk_lcdc0>;
1276 clock-output-names = "sclk_lcdc0";
1277 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1279 rockchip,clkops-idx =
1280 <CLKOPS_RATE_MUX_DIV>;
1281 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1285 clk_sel_con29: sel-con@00b8 {
1286 compatible = "rockchip,rk3188-selcon";
1288 #address-cells = <1>;
1291 clk_cif_pll: clk_cif_pll_mux {
1292 compatible = "rockchip,rk3188-mux-con";
1293 rockchip,bits = <0 2>;
1294 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1295 clock-output-names = "clk_cif_pll";
1297 #clock-init-cells = <1>;
1300 clk_cif_out_div: clk_cif_out_div {
1301 compatible = "rockchip,rk3188-div-con";
1302 rockchip,bits = <2 5>;
1303 clocks = <&clk_cif_out>;
1304 clock-output-names = "clk_cif_out";
1305 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1307 rockchip,clkops-idx =
1308 <CLKOPS_RATE_MUX_DIV>;
1309 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1312 clk_cif_out: clk_cif_out_mux {
1313 compatible = "rockchip,rk3188-mux-con";
1314 rockchip,bits = <7 1>;
1315 clocks = <&clk_cif_pll>, <&xin24m>;
1316 clock-output-names = "clk_cif_out";
1318 #clock-init-cells = <1>;
1321 pclk_pmu_pre: pclk_pmu_pre_div {
1322 compatible = "rockchip,rk3188-div-con";
1323 rockchip,bits = <8 6>;
1324 clocks = <&clk_cpll>;
1325 clock-output-names = "pclk_pmu_pre";
1326 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1328 #clock-init-cells = <1>;
1331 /* reg[15:14]: reserved */
1334 clk_sel_con30: sel-con@00bc {
1335 compatible = "rockchip,rk3188-selcon";
1337 #address-cells = <1>;
1340 clk_testout_div: clk_testout_div {
1341 compatible = "rockchip,rk3188-div-con";
1342 rockchip,bits = <0 5>;
1344 clock-output-names = "clk_testout";
1345 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1347 #clock-init-cells = <1>;
1350 /* reg[6:5]: reserved */
1352 clk_cif0_in: clk_cif0_in_mux {
1353 compatible = "rockchip,rk3188-mux-con";
1354 rockchip,bits = <7 1>;
1355 clocks = <&pclkin_cif>, <&pclkin_cif_inv>;
1356 clock-output-names = "clk_cif0_in";
1358 #clock-init-cells = <1>;
1361 hclk_vio_pre_div: hclk_vio_pre_div {
1362 compatible = "rockchip,rk3188-div-con";
1363 rockchip,bits = <8 5>;
1364 clocks = <&hclk_vio_pre>;
1365 clock-output-names = "hclk_vio_pre";
1366 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1368 rockchip,clkops-idx =
1369 <CLKOPS_RATE_MUX_DIV>;
1370 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1373 /* reg[13]: reserved */
1375 hclk_vio_pre: hclk_vio_pre_mux {
1376 compatible = "rockchip,rk3188-mux-con";
1377 rockchip,bits = <14 2>;
1378 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&usb480m>;
1379 clock-output-names = "hclk_vio_pre";
1381 #clock-init-cells = <1>;
1386 clk_sel_con31: sel-con@00c0 {
1387 compatible = "rockchip,rk3188-selcon";
1389 #address-cells = <1>;
1392 aclk_vio0_pre_div: aclk_vio0_pre_div {
1393 compatible = "rockchip,rk3188-div-con";
1394 rockchip,bits = <0 5>;
1395 clocks = <&aclk_vio0_pre>;
1396 clock-output-names = "aclk_vio0_pre";
1397 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1399 rockchip,clkops-idx =
1400 <CLKOPS_RATE_MUX_DIV>;
1401 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1404 aclk_vio0_pre: aclk_vio0_pre_mux {
1405 compatible = "rockchip,rk3188-mux-con";
1406 rockchip,bits = <5 3>;
1407 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1408 clock-output-names = "aclk_vio0_pre";
1410 #clock-init-cells = <1>;
1413 aclk_vio1_pre_div: aclk_vio1_pre_div {
1414 compatible = "rockchip,rk3188-div-con";
1415 rockchip,bits = <8 5>;
1416 clocks = <&aclk_vio1_pre>;
1417 clock-output-names = "aclk_vio1_pre";
1418 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1420 rockchip,clkops-idx =
1421 <CLKOPS_RATE_MUX_DIV>;
1422 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1425 aclk_vio1_pre: aclk_vio1_pre_mux {
1426 compatible = "rockchip,rk3188-mux-con";
1427 rockchip,bits = <13 3>;
1428 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1429 clock-output-names = "aclk_vio1_pre";
1431 #clock-init-cells = <1>;
1436 clk_sel_con32: sel-con@00c4 {
1437 compatible = "rockchip,rk3188-selcon";
1439 #address-cells = <1>;
1442 clk_vepu_div: clk_vepu_div {
1443 compatible = "rockchip,rk3188-div-con";
1444 rockchip,bits = <0 5>;
1445 clocks = <&clk_vepu>;
1446 clock-output-names = "clk_vepu";
1447 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1449 rockchip,clkops-idx =
1450 <CLKOPS_RATE_MUX_DIV>;
1451 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1454 clk_vepu: clk_vepu_mux {
1455 compatible = "rockchip,rk3188-mux-con";
1456 rockchip,bits = <5 3>;
1457 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1458 clock-output-names = "clk_vepu";
1460 #clock-init-cells = <1>;
1463 clk_vdpu_div: clk_vdpu_div {
1464 compatible = "rockchip,rk3188-div-con";
1465 rockchip,bits = <8 5>;
1466 clocks = <&clk_vdpu>;
1467 clock-output-names = "clk_vdpu";
1468 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1470 rockchip,clkops-idx =
1471 <CLKOPS_RATE_MUX_DIV>;
1472 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1475 clk_vdpu: clk_vdpu_mux {
1476 compatible = "rockchip,rk3188-mux-con";
1477 rockchip,bits = <13 3>;
1478 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1479 clock-output-names = "clk_vdpu";
1481 #clock-init-cells = <1>;
1486 clk_sel_con34: sel-con@00cc {
1487 compatible = "rockchip,rk3188-selcon";
1489 #address-cells = <1>;
1492 clk_gpu_div: clk_gpu_div {
1493 compatible = "rockchip,rk3188-div-con";
1494 rockchip,bits = <0 5>;
1495 clocks = <&clk_gpu>;
1496 clock-output-names = "clk_gpu";
1497 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1499 rockchip,clkops-idx =
1500 <CLKOPS_RATE_MUX_DIV>;
1501 rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
1504 clk_gpu: clk_gpu_mux {
1505 compatible = "rockchip,rk3188-mux-con";
1506 rockchip,bits = <5 3>;
1507 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1508 clock-output-names = "clk_gpu";
1510 #clock-init-cells = <1>;
1513 clk_hevc_core_div: clk_hevc_core_div {
1514 compatible = "rockchip,rk3188-div-con";
1515 rockchip,bits = <8 5>;
1516 clocks = <&clk_hevc_core>;
1517 clock-output-names = "clk_hevc_core";
1518 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1520 rockchip,clkops-idx =
1521 <CLKOPS_RATE_MUX_DIV>;
1522 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
1525 clk_hevc_core: clk_hevc_core_mux {
1526 compatible = "rockchip,rk3188-mux-con";
1527 rockchip,bits = <13 3>;
1528 clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
1529 clock-output-names = "clk_hevc_core";
1531 #clock-init-cells = <1>;
1539 /* Gate control regs */
1541 compatible = "rockchip,rk-gate-cons";
1542 #address-cells = <1>;
1546 clk_gates0: gate-clk@00d0{
1547 compatible = "rockchip,rk3188-gate-clk";
1550 <&clk_core>, <&dummy>,
1551 <&dummy>, <&aclk_cpu>,
1553 <&aclk_cpu>, <&aclk_cpu>,
1554 <&dummy>, <&clk_core>,
1556 <&dummy>, <&clk_i2s_2ch_pll>,
1557 <&i2s_2ch_frac>, <&hclk_vio_pre>,
1559 <&aclk_cpu>, <&clk_i2s_2ch_out>,
1560 <&clk_i2s_2ch>, <&dummy>;
1562 clock-output-names =
1563 "pclk_dbg", "aclk_cpu", /*clk_cpu_cpll*/
1564 "reserved", "aclk_cpu_pre",
1566 "hclk_cpu_pre", "pclk_cpu_pre",
1567 "clk_core", "aclk_core_pre",
1569 "reserved", "clk_i2s_2ch_pll",
1570 "i2s_2ch_frac", "hclk_vio_pre",
1572 "clk_crypto", "clk_i2s_2ch_out",
1573 "clk_i2s_2ch", "clk_testout";
1574 rockchip,suspend-clkgating-setting=<0x11ff 0x0>;
1579 clk_gates1: gate-clk@00d4{
1580 compatible = "rockchip,rk3188-gate-clk";
1583 <&clk_cpll>, <&dummy>,
1584 <&dummy>, <&jtag_tck>,
1586 <&aclk_vio1_pre>, <&xin12m>,
1587 <&xin12m>, <&clk_mac_pll>,
1589 <&clk_uart0_pll>, <&uart0_frac>,
1590 <&clk_uart1_div>, <&uart1_frac>,
1592 <&clk_uart2_div>, <&uart2_frac>,
1593 <&clk_tsp>, <&dummy>;
1595 clock-output-names =
1596 "pclk_pmu_pre", "reserved",
1597 "reserved", "clk_jtag",
1599 "aclk_vio1_pre", "clk_otgphy0",
1600 "clk_otgphy1", "clk_mac_pll",
1602 "clk_uart0_pll", "uart0_frac",
1603 "clk_uart1_div", "uart1_frac",
1605 "clk_uart2_div", "uart2_frac",
1606 "clk_tsp", "reserved";
1608 rockchip,suspend-clkgating-setting=<0x000f 0x0>;
1612 clk_gates2: gate-clk@00d8 {
1613 compatible = "rockchip,rk3188-gate-clk";
1616 <&aclk_peri>, <&aclk_peri>,
1617 <&aclk_peri>, <&aclk_peri>,
1619 <&clk_mac_ref>, <&clk_mac_ref>,
1620 <&clk_mac_ref>, <&clk_mac_ref>,
1622 <&clk_saradc>, <&clk_spi0>,
1623 <&clk_spdif_pll>, <&clk_sdmmc0>,
1625 <&spdif_frac>, <&clk_sdio>,
1626 <&clk_emmc>, <&xin24m>;
1627 clock-output-names =
1628 "aclk_peri", "aclk_peri_pre",
1629 "hclk_peri_pre", "pclk_peri_pre",
1631 "clk_mac_ref", "clk_mac_refout",
1632 "clk_mac_rx", "clk_mac_tx",
1634 "clk_saradc", "clk_spi0",
1635 "clk_spdif_pll", "clk_sdmmc0",
1637 "spdif_frac", "clk_sdio",
1638 "clk_emmc", "clk_mipi_24m";
1639 rockchip,suspend-clkgating-setting=<0x000f 0x0>;
1644 clk_gates3: gate-clk@00dc {
1645 compatible = "rockchip,rk3188-gate-clk";
1648 <&aclk_vio0_pre>, <&dclk_lcdc0>,
1649 <&sclk_lcdc0>, <&pclkin_cif>,
1651 <&dclk_ebc>, <&hclk_cpu_pre>,
1652 <&hclk_peri_pre>, <&clk_cif_pll>,
1654 <&pclk_cpu_pre>, <&clk_vepu>,
1655 <&clk_hevc_core>, <&clk_vdpu>,
1657 <&hclk_vdpu>, <&clk_gpu>,
1658 <&aclk_peri>, <&clk_sfc>;
1660 clock-output-names =
1661 "aclk_vio0_pre", "dclk_lcdc0",
1662 "sclk_lcdc0", "pclkin_cif",
1664 "dclk_ebc", "g_hclk_crypto",
1665 "g_hclk_em_peri", "clk_cif_pll",
1667 "g_pclk_hdmi", "clk_vepu",
1668 "clk_hevc_core", "clk_vdpu",
1670 "hclk_vdpu", "clk_gpu",
1671 "g_hclk_gps", "clk_sfc";
1672 rockchip,suspend-clkgating-setting=<0x0060 0x0000>;
1677 clk_gates4: gate-clk@00e0{
1678 compatible = "rockchip,rk3188-gate-clk";
1681 <&hclk_peri_pre>, <&pclk_peri_pre>,
1682 <&aclk_peri>, <&aclk_peri>,
1684 <&clk_i2s_8ch_pll>, <&i2s_8ch_frac>,
1685 <&clk_i2s_8ch>, <&dummy>,
1688 <&aclk_cpu>, <&dummy>,
1690 <&aclk_cpu>, <&dummy>,
1693 clock-output-names =
1694 "g_hp_axi_matrix", "g_pp_axi_matrix",
1695 "g_aclk_cpu_peri", "g_ap_axi_matrix",
1697 "clk_i2s_8ch_pll", "i2s_8ch_frac",
1698 "clk_i2s_8ch", "reserved",
1700 "reserved", "reserved",
1701 "g_aclk_strc_sys", "reserved",
1703 /* Not use these ddr gates */
1704 "g_aclk_intmem", "reserved",
1705 "reserved", "reserved";
1707 rockchip,suspend-clkgating-setting = <0xff8f 0x0000>;
1711 clk_gates5: gate-clk@00e4 {
1712 compatible = "rockchip,rk3188-gate-clk";
1715 <&pclk_cpu_pre>, <&aclk_peri>,
1716 <&pclk_peri_pre>, <&dummy>,
1718 <&pclk_cpu_pre>, <&dummy>,
1719 <&hclk_cpu_pre>, <&pclk_cpu_pre>,
1721 <&dummy>, <&hclk_peri_pre>,
1722 <&hclk_peri_pre>, <&hclk_peri_pre>,
1724 <&dummy>, <&hclk_peri_pre>,
1725 <&pclk_cpu_pre>, <&dummy>;
1727 clock-output-names =
1728 "g_pclk_mipiphy", "g_aclk_dmac",
1729 "g_pclk_efuse", "reserved",
1731 "g_pclk_grf", "reserved",
1732 "g_hclk_rom", "g_pclk_ddrupctl",
1734 "reserved", "g_hclk_nandc",
1735 "g_hclk_sdmmc0", "g_hclk_sdio",
1737 "reserved", "g_hclk_otg0",
1738 "g_pclk_acodec", "reserved";
1740 rockchip,suspend-clkgating-setting = <0x00f0 0x0000>;
1745 clk_gates6: gate-clk@00e8 {
1746 compatible = "rockchip,rk3188-gate-clk";
1749 <&aclk_vio0_niu>, <&hclk_vio_niu>,
1752 <&hclk_vio_niu>, <&aclk_vio0_niu>,
1756 <&hclk_vio_niu>, <&aclk_vio0_niu>,
1758 <&hclk_vio_pre>, <&aclk_vio0_pre>,
1761 clock-output-names =
1762 "g_aclk_lcdc0", "g_hclk_lcdc0",
1763 "reserved", "reserved",
1765 "g_hclk_cif", "g_aclk_cif",
1766 "reserved", "reserved",
1768 "reserved", "reserved",
1769 "g_hclk_rga", "g_aclk_rga",
1771 "hclk_vio_niu", "aclk_vio0_niu",
1772 "reserved", "reserved";
1774 rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
1779 clk_gates7: gate-clk@00ec {
1780 compatible = "rockchip,rk3188-gate-clk";
1783 <&hclk_peri_pre>, <&hclk_peri_pre>,
1784 <&hclk_peri_pre>, <&hclk_peri_pre>,
1786 <&hclk_peri_pre>, <&dummy>,
1787 <&dummy>, <&pclk_peri_pre>,
1790 <&pclk_peri_pre>, <&dummy>,
1792 <&pclk_peri_pre>, <&dummy>,
1793 <&pclk_peri_pre>, <&pclk_peri_pre>;
1795 clock-output-names =
1796 "g_hclk_emmc", "g_hclk_sfc",
1797 "g_hclk_i2s_2ch", "g_hclk_host",
1799 "g_hclk_i2s_8ch", "reserved",
1800 "reserved", "g_pclk_timer",
1802 "reserved", "reserved",
1803 "g_pclk_pwm", "reserved",
1805 "g_pclk_spi0", "reserved",
1806 "g_pclk_saradc", "g_pclk_wdt";
1808 rockchip,suspend-clkgating-setting = <0x8480 0x0000>;
1813 clk_gates8: gate-clk@00f0 {
1814 compatible = "rockchip,rk3188-gate-clk";
1817 <&pclk_peri_pre>, <&pclk_peri_pre>,
1818 <&pclk_peri_pre>, <&dummy>,
1820 <&pclk_peri_pre>, <&pclk_peri_pre>,
1821 <&pclk_peri_pre>, <&pclk_peri_pre>,
1823 <&dummy>, <&pclk_peri_pre>,
1824 <&pclk_peri_pre>, <&pclk_peri_pre>,
1826 <&pclk_peri_pre>, <&dummy>,
1829 clock-output-names =
1830 "g_pclk_uart0", "g_pclk_uart1",
1831 "g_pclk_uart2", "reserved",
1833 "g_pclk_i2c0", "g_pclk_i2c1",
1834 "g_pclk_i2c2", "g_pclk_i2c3",
1836 "reserved", "g_pclk_gpio0",
1837 "g_pclk_gpio1", "g_pclk_gpio2",
1839 "g_pclk_gpio3", "reserved",
1840 "reserved", "reserved";
1842 rockchip,suspend-clkgating-setting=<0xff0f 0x0000>;
1846 clk_gates9: gate-clk@00f4 {
1847 compatible = "rockchip,rk3188-gate-clk";
1851 <&pclk_pmu_pre>, <&pclk_pmu_pre>,
1853 <&dummy>, <&hclk_vio_niu>,
1854 <&hclk_vio_niu>, <&hclk_vio_niu>,
1856 <&aclk_vio1_niu>, <&hclk_vio_niu>,
1857 <&aclk_vio1_pre>, <&dummy>,
1859 <&pclk_peri_pre>, <&hclk_peri_pre>,
1860 <&hclk_peri_pre>, <&aclk_peri>;
1862 clock-output-names =
1863 "reserved", "reserved",
1864 "g_pclk_pmu", "g_pclk_pmu_noc",
1866 "reserved", "g_hclk_vio_h2p",
1867 "g_pclk_mipi", "g_hclk_iep",
1869 "g_aclk_iep", "g_hclk_ebc",
1870 "aclk_vio1_niu", "reserved",
1872 "g_pclk_sim_card", "g_hclk_usb_peri",
1873 "g_hclk_pe_arbi", "g_aclk_peri_niu";
1875 rockchip,suspend-clkgating-setting=<0xf00f 0x0>;
1880 clk_gates10: gate-clk@00f8 {
1881 compatible = "rockchip,rk3188-gate-clk";
1884 <&xin24m>, <&xin24m>,
1885 <&xin24m>, <&xin24m>,
1887 <&xin24m>, <&xin24m>,
1888 <&xin24m>, <&xin24m>,
1890 <&xin24m>, <&hclk_peri_pre>,
1891 <&aclk_peri>, <&pclk_peri_pre>,
1893 <&hclk_peri_pre>, <&clk_tsp_in>,
1894 <&hclk_peri_pre>, <&clk_nandc>;
1896 clock-output-names =
1897 "g_clk_pvtm_core", "g_clk_pvtm_gpu",
1898 "g_clk_pvtm_func", "clk_timer0",
1900 "clk_timer1", "clk_timer2",
1901 "clk_timer3", "clk_timer4",
1903 "clk_timer5", "g_hclk_spdif",
1904 "g_aclk_gmac", "g_pclk_gmac",
1906 "g_hclk_tsp", "g_clkin0_tsp",
1907 "g_hclk_usbhost", "clk_nandc";
1909 rockchip,suspend-clkgating-setting = <0x0000 0x0>; /* pwm logic vol */