arch/arm/boot/dts/rk3066a.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/pinctrl/rockchip.h>
  18 #include <dt-bindings/clock/rk3066a-cru.h>
  19 #include "rk3xxx.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3066a";
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 enable-method = "rockchip,rk3066-smp";
  28
  29                 cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         next-level-cache = <&L2>;
  33                         reg = <0x0>;
  34                 };
  35                 cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a9";
  38                         next-level-cache = <&L2>;
  39                         reg = <0x1>;
  40                 };
  41         };
  42
  43         soc {
  44                 timer@20038000 {
  45                         compatible = "snps,dw-apb-timer-osc";
  46                         reg = <0x20038000 0x100>;
  47                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  48                         clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
  49                         clock-names = "timer", "pclk";
  50                 };
  51
  52                 timer@2003a000 {
  53                         compatible = "snps,dw-apb-timer-osc";
  54                         reg = <0x2003a000 0x100>;
  55                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  56                         clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
  57                         clock-names = "timer", "pclk";
  58                 };
  59
  60                 timer@2000e000 {
  61                         compatible = "snps,dw-apb-timer-osc";
  62                         reg = <0x2000e000 0x100>;
  63                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  64                         clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
  65                         clock-names = "timer", "pclk";
  66                 };
  67
  68                 sram: sram@10080000 {
  69                         compatible = "mmio-sram";
  70                         reg = <0x10080000 0x10000>;
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73                         ranges = <0 0x10080000 0x10000>;
  74
  75                         smp-sram@0 {
  76                                 compatible = "rockchip,rk3066-smp-sram";
  77                                 reg = <0x0 0x50>;
  78                         };
  79                 };
  80
  81                 cru: clock-controller@20000000 {
  82                         compatible = "rockchip,rk3066a-cru";
  83                         reg = <0x20000000 0x1000>;
  84                         rockchip,grf = <&grf>;
  85
  86                         #clock-cells = <1>;
  87                         #reset-cells = <1>;
  88                 };
  89
  90                 pinctrl@20008000 {
  91                         compatible = "rockchip,rk3066a-pinctrl";
  92                         rockchip,grf = <&grf>;
  93                         #address-cells = <1>;
  94                         #size-cells = <1>;
  95                         ranges;
  96
  97                         gpio0: gpio0@20034000 {
  98                                 compatible = "rockchip,gpio-bank";
  99                                 reg = <0x20034000 0x100>;
 100                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 101                                 clocks = <&cru PCLK_GPIO0>;
 102
 103                                 gpio-controller;
 104                                 #gpio-cells = <2>;
 105
 106                                 interrupt-controller;
 107                                 #interrupt-cells = <2>;
 108                         };
 109
 110                         gpio1: gpio1@2003c000 {
 111                                 compatible = "rockchip,gpio-bank";
 112                                 reg = <0x2003c000 0x100>;
 113                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 114                                 clocks = <&cru PCLK_GPIO1>;
 115
 116                                 gpio-controller;
 117                                 #gpio-cells = <2>;
 118
 119                                 interrupt-controller;
 120                                 #interrupt-cells = <2>;
 121                         };
 122
 123                         gpio2: gpio2@2003e000 {
 124                                 compatible = "rockchip,gpio-bank";
 125                                 reg = <0x2003e000 0x100>;
 126                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 127                                 clocks = <&cru PCLK_GPIO2>;
 128
 129                                 gpio-controller;
 130                                 #gpio-cells = <2>;
 131
 132                                 interrupt-controller;
 133                                 #interrupt-cells = <2>;
 134                         };
 135
 136                         gpio3: gpio3@20080000 {
 137                                 compatible = "rockchip,gpio-bank";
 138                                 reg = <0x20080000 0x100>;
 139                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 140                                 clocks = <&cru PCLK_GPIO3>;
 141
 142                                 gpio-controller;
 143                                 #gpio-cells = <2>;
 144
 145                                 interrupt-controller;
 146                                 #interrupt-cells = <2>;
 147                         };
 148
 149                         gpio4: gpio4@20084000 {
 150                                 compatible = "rockchip,gpio-bank";
 151                                 reg = <0x20084000 0x100>;
 152                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 153                                 clocks = <&cru PCLK_GPIO4>;
 154
 155                                 gpio-controller;
 156                                 #gpio-cells = <2>;
 157
 158                                 interrupt-controller;
 159                                 #interrupt-cells = <2>;
 160                         };
 161
 162                         gpio6: gpio6@2000a000 {
 163                                 compatible = "rockchip,gpio-bank";
 164                                 reg = <0x2000a000 0x100>;
 165                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 166                                 clocks = <&cru PCLK_GPIO6>;
 167
 168                                 gpio-controller;
 169                                 #gpio-cells = <2>;
 170
 171                                 interrupt-controller;
 172                                 #interrupt-cells = <2>;
 173                         };
 174
 175                         pcfg_pull_default: pcfg_pull_default {
 176                                 bias-pull-pin-default;
 177                         };
 178
 179                         pcfg_pull_none: pcfg_pull_none {
 180                                 bias-disable;
 181                         };
 182
 183                         uart0 {
 184                                 uart0_xfer: uart0-xfer {
 185                                         rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 186                                                         <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 187                                 };
 188
 189                                 uart0_cts: uart0-cts {
 190                                         rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 191                                 };
 192
 193                                 uart0_rts: uart0-rts {
 194                                         rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 195                                 };
 196                         };
 197
 198                         uart1 {
 199                                 uart1_xfer: uart1-xfer {
 200                                         rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 201                                                         <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 202                                 };
 203
 204                                 uart1_cts: uart1-cts {
 205                                         rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 206                                 };
 207
 208                                 uart1_rts: uart1-rts {
 209                                         rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 210                                 };
 211                         };
 212
 213                         uart2 {
 214                                 uart2_xfer: uart2-xfer {
 215                                         rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 216                                                         <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 217                                 };
 218                                 /* no rts / cts for uart2 */
 219                         };
 220
 221                         uart3 {
 222                                 uart3_xfer: uart3-xfer {
 223                                         rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 224                                                         <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 225                                 };
 226
 227                                 uart3_cts: uart3-cts {
 228                                         rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 229                                 };
 230
 231                                 uart3_rts: uart3-rts {
 232                                         rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 233                                 };
 234                         };
 235
 236                         sd0 {
 237                                 sd0_clk: sd0-clk {
 238                                         rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 239                                 };
 240
 241                                 sd0_cmd: sd0-cmd {
 242                                         rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 243                                 };
 244
 245                                 sd0_cd: sd0-cd {
 246                                         rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 247                                 };
 248
 249                                 sd0_wp: sd0-wp {
 250                                         rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 251                                 };
 252
 253                                 sd0_bus1: sd0-bus-width1 {
 254                                         rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 255                                 };
 256
 257                                 sd0_bus4: sd0-bus-width4 {
 258                                         rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 259                                                         <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 260                                                         <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 261                                                         <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 262                                 };
 263                         };
 264
 265                         sd1 {
 266                                 sd1_clk: sd1-clk {
 267                                         rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 268                                 };
 269
 270                                 sd1_cmd: sd1-cmd {
 271                                         rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 272                                 };
 273
 274                                 sd1_cd: sd1-cd {
 275                                         rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 276                                 };
 277
 278                                 sd1_wp: sd1-wp {
 279                                         rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 280                                 };
 281
 282                                 sd1_bus1: sd1-bus-width1 {
 283                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 284                                 };
 285
 286                                 sd1_bus4: sd1-bus-width4 {
 287                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 288                                                         <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 289                                                         <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 290                                                         <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 291                                 };
 292                         };
 293                 };
 294         };
 295 };