2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/rockchip.h>
18 #include <dt-bindings/clock/rk3066a-cru.h>
19 #include "rk3xxx.dtsi"
22 compatible = "rockchip,rk3066a";
27 enable-method = "rockchip,rk3066-smp";
31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
44 compatible = "snps,dw-apb-timer-osc";
45 reg = <0x20038000 0x100>;
46 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
47 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
48 clock-names = "timer", "pclk";
52 compatible = "snps,dw-apb-timer-osc";
53 reg = <0x2003a000 0x100>;
54 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
56 clock-names = "timer", "pclk";
60 compatible = "snps,dw-apb-timer-osc";
61 reg = <0x2000e000 0x100>;
62 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
64 clock-names = "timer", "pclk";
68 compatible = "mmio-sram";
69 reg = <0x10080000 0x10000>;
72 ranges = <0 0x10080000 0x10000>;
75 compatible = "rockchip,rk3066-smp-sram";
80 cru: clock-controller@20000000 {
81 compatible = "rockchip,rk3066a-cru";
82 reg = <0x20000000 0x1000>;
83 rockchip,grf = <&grf>;
90 compatible = "rockchip,rk3066a-pinctrl";
91 rockchip,grf = <&grf>;
96 gpio0: gpio0@20034000 {
97 compatible = "rockchip,gpio-bank";
98 reg = <0x20034000 0x100>;
99 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&cru PCLK_GPIO0>;
105 interrupt-controller;
106 #interrupt-cells = <2>;
109 gpio1: gpio1@2003c000 {
110 compatible = "rockchip,gpio-bank";
111 reg = <0x2003c000 0x100>;
112 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&cru PCLK_GPIO1>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
122 gpio2: gpio2@2003e000 {
123 compatible = "rockchip,gpio-bank";
124 reg = <0x2003e000 0x100>;
125 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&cru PCLK_GPIO2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
135 gpio3: gpio3@20080000 {
136 compatible = "rockchip,gpio-bank";
137 reg = <0x20080000 0x100>;
138 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&cru PCLK_GPIO3>;
144 interrupt-controller;
145 #interrupt-cells = <2>;
148 gpio4: gpio4@20084000 {
149 compatible = "rockchip,gpio-bank";
150 reg = <0x20084000 0x100>;
151 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&cru PCLK_GPIO4>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
161 gpio6: gpio6@2000a000 {
162 compatible = "rockchip,gpio-bank";
163 reg = <0x2000a000 0x100>;
164 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&cru PCLK_GPIO6>;
170 interrupt-controller;
171 #interrupt-cells = <2>;
174 pcfg_pull_default: pcfg_pull_default {
175 bias-pull-pin-default;
178 pcfg_pull_none: pcfg_pull_none {
183 uart0_xfer: uart0-xfer {
184 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
185 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
188 uart0_cts: uart0-cts {
189 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
192 uart0_rts: uart0-rts {
193 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
198 uart1_xfer: uart1-xfer {
199 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
200 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
203 uart1_cts: uart1-cts {
204 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
207 uart1_rts: uart1-rts {
208 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
213 uart2_xfer: uart2-xfer {
214 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
215 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
217 /* no rts / cts for uart2 */
221 uart3_xfer: uart3-xfer {
222 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
223 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
226 uart3_cts: uart3-cts {
227 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
230 uart3_rts: uart3-rts {
231 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
237 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
241 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
245 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
249 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
252 sd0_bus1: sd0-bus-width1 {
253 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
256 sd0_bus4: sd0-bus-width4 {
257 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
258 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
259 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
260 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
266 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
270 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
274 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
278 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
281 sd1_bus1: sd1-bus-width1 {
282 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
285 sd1_bus4: sd1-bus-width4 {
286 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
287 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
288 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
289 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&uart0_xfer>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart1_xfer>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&uart2_xfer>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&uart3_xfer>;