arch/arm/boot/dts/rk3066a.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/pinctrl/rockchip.h>
  18 #include <dt-bindings/clock/rk3066a-cru.h>
  19 #include "rk3xxx.dtsi"
  20 #include "rk3066a-clocks.dtsi"
  21
  22 / {
  23         compatible = "rockchip,rk3066a";
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28                 enable-method = "rockchip,rk3066-smp";
  29
  30                 cpu@0 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a9";
  33                         next-level-cache = <&L2>;
  34                         reg = <0x0>;
  35                 };
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a9";
  39                         next-level-cache = <&L2>;
  40                         reg = <0x1>;
  41                 };
  42         };
  43
  44         soc {
  45                 timer@20038000 {
  46                         compatible = "snps,dw-apb-timer-osc";
  47                         reg = <0x20038000 0x100>;
  48                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  49                         clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
  50                         clock-names = "timer", "pclk";
  51                 };
  52
  53                 timer@2003a000 {
  54                         compatible = "snps,dw-apb-timer-osc";
  55                         reg = <0x2003a000 0x100>;
  56                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  57                         clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
  58                         clock-names = "timer", "pclk";
  59                 };
  60
  61                 timer@2000e000 {
  62                         compatible = "snps,dw-apb-timer-osc";
  63                         reg = <0x2000e000 0x100>;
  64                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  65                         clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
  66                         clock-names = "timer", "pclk";
  67                 };
  68
  69                 sram: sram@10080000 {
  70                         compatible = "mmio-sram";
  71                         reg = <0x10080000 0x10000>;
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         ranges = <0 0x10080000 0x10000>;
  75
  76                         smp-sram@0 {
  77                                 compatible = "rockchip,rk3066-smp-sram";
  78                                 reg = <0x0 0x50>;
  79                         };
  80                 };
  81
  82                 cru: clock-controller@20000000 {
  83                         compatible = "rockchip,rk3066a-cru";
  84                         reg = <0x20000000 0x1000>;
  85                         rockchip,grf = <&grf>;
  86
  87                         #clock-cells = <1>;
  88                         #reset-cells = <1>;
  89                 };
  90
  91                 pinctrl@20008000 {
  92                         compatible = "rockchip,rk3066a-pinctrl";
  93                         rockchip,grf = <&grf>;
  94                         #address-cells = <1>;
  95                         #size-cells = <1>;
  96                         ranges;
  97
  98                         gpio0: gpio0@20034000 {
  99                                 compatible = "rockchip,gpio-bank";
 100                                 reg = <0x20034000 0x100>;
 101                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 102                                 clocks = <&cru PCLK_GPIO0>;
 103
 104                                 gpio-controller;
 105                                 #gpio-cells = <2>;
 106
 107                                 interrupt-controller;
 108                                 #interrupt-cells = <2>;
 109                         };
 110
 111                         gpio1: gpio1@2003c000 {
 112                                 compatible = "rockchip,gpio-bank";
 113                                 reg = <0x2003c000 0x100>;
 114                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 115                                 clocks = <&cru PCLK_GPIO1>;
 116
 117                                 gpio-controller;
 118                                 #gpio-cells = <2>;
 119
 120                                 interrupt-controller;
 121                                 #interrupt-cells = <2>;
 122                         };
 123
 124                         gpio2: gpio2@2003e000 {
 125                                 compatible = "rockchip,gpio-bank";
 126                                 reg = <0x2003e000 0x100>;
 127                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 128                                 clocks = <&cru PCLK_GPIO2>;
 129
 130                                 gpio-controller;
 131                                 #gpio-cells = <2>;
 132
 133                                 interrupt-controller;
 134                                 #interrupt-cells = <2>;
 135                         };
 136
 137                         gpio3: gpio3@20080000 {
 138                                 compatible = "rockchip,gpio-bank";
 139                                 reg = <0x20080000 0x100>;
 140                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 141                                 clocks = <&cru PCLK_GPIO3>;
 142
 143                                 gpio-controller;
 144                                 #gpio-cells = <2>;
 145
 146                                 interrupt-controller;
 147                                 #interrupt-cells = <2>;
 148                         };
 149
 150                         gpio4: gpio4@20084000 {
 151                                 compatible = "rockchip,gpio-bank";
 152                                 reg = <0x20084000 0x100>;
 153                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 154                                 clocks = <&cru PCLK_GPIO4>;
 155
 156                                 gpio-controller;
 157                                 #gpio-cells = <2>;
 158
 159                                 interrupt-controller;
 160                                 #interrupt-cells = <2>;
 161                         };
 162
 163                         gpio6: gpio6@2000a000 {
 164                                 compatible = "rockchip,gpio-bank";
 165                                 reg = <0x2000a000 0x100>;
 166                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 167                                 clocks = <&cru PCLK_GPIO6>;
 168
 169                                 gpio-controller;
 170                                 #gpio-cells = <2>;
 171
 172                                 interrupt-controller;
 173                                 #interrupt-cells = <2>;
 174                         };
 175
 176                         pcfg_pull_default: pcfg_pull_default {
 177                                 bias-pull-pin-default;
 178                         };
 179
 180                         pcfg_pull_none: pcfg_pull_none {
 181                                 bias-disable;
 182                         };
 183
 184                         uart0 {
 185                                 uart0_xfer: uart0-xfer {
 186                                         rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 187                                                         <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 188                                 };
 189
 190                                 uart0_cts: uart0-cts {
 191                                         rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 192                                 };
 193
 194                                 uart0_rts: uart0-rts {
 195                                         rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 196                                 };
 197                         };
 198
 199                         uart1 {
 200                                 uart1_xfer: uart1-xfer {
 201                                         rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 202                                                         <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 203                                 };
 204
 205                                 uart1_cts: uart1-cts {
 206                                         rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 207                                 };
 208
 209                                 uart1_rts: uart1-rts {
 210                                         rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 211                                 };
 212                         };
 213
 214                         uart2 {
 215                                 uart2_xfer: uart2-xfer {
 216                                         rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 217                                                         <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 218                                 };
 219                                 /* no rts / cts for uart2 */
 220                         };
 221
 222                         uart3 {
 223                                 uart3_xfer: uart3-xfer {
 224                                         rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 225                                                         <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 226                                 };
 227
 228                                 uart3_cts: uart3-cts {
 229                                         rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 230                                 };
 231
 232                                 uart3_rts: uart3-rts {
 233                                         rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 234                                 };
 235                         };
 236
 237                         sd0 {
 238                                 sd0_clk: sd0-clk {
 239                                         rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 240                                 };
 241
 242                                 sd0_cmd: sd0-cmd {
 243                                         rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 244                                 };
 245
 246                                 sd0_cd: sd0-cd {
 247                                         rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 248                                 };
 249
 250                                 sd0_wp: sd0-wp {
 251                                         rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 252                                 };
 253
 254                                 sd0_bus1: sd0-bus-width1 {
 255                                         rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 256                                 };
 257
 258                                 sd0_bus4: sd0-bus-width4 {
 259                                         rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 260                                                         <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 261                                                         <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 262                                                         <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 263                                 };
 264                         };
 265
 266                         sd1 {
 267                                 sd1_clk: sd1-clk {
 268                                         rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 269                                 };
 270
 271                                 sd1_cmd: sd1-cmd {
 272                                         rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 273                                 };
 274
 275                                 sd1_cd: sd1-cd {
 276                                         rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 277                                 };
 278
 279                                 sd1_wp: sd1-wp {
 280                                         rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 281                                 };
 282
 283                                 sd1_bus1: sd1-bus-width1 {
 284                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 285                                 };
 286
 287                                 sd1_bus4: sd1-bus-width4 {
 288                                         rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 289                                                         <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 290                                                         <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 291                                                         <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 292                                 };
 293                         };
 294                 };
 295         };
 296 };