2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
23 * This is a dummy clock, to be used as placeholder on
24 * other mux clocks when a specific parent clock is not
25 * yet implemented. It should be dropped when the driver
29 compatible = "fixed-clock";
30 clock-frequency = <0>;
35 compatible = "fixed-clock";
36 clock-frequency = <48000000>;
40 dummy150m: dummy150m {
41 compatible = "fixed-clock";
42 clock-frequency = <150000000>;
46 clk_gates0: gate-clk@200000d0 {
47 compatible = "rockchip,rk2928-gate-clk";
48 reg = <0x200000d0 0x4>;
49 clocks = <&dummy>, <&dummy>,
59 "gate_core_periph", "gate_cpu_gpll",
60 "gate_ddrphy", "gate_aclk_cpu",
61 "gate_hclk_cpu", "gate_pclk_cpu",
62 "gate_atclk_cpu", "gate_i2s0",
63 "gate_i2s0_frac", "gate_i2s1",
64 "gate_i2s1_frac", "gate_i2s2",
65 "gate_i2s2_frac", "gate_spdif",
66 "gate_spdif_frac", "gate_testclk";
71 clk_gates1: gate-clk@200000d4 {
72 compatible = "rockchip,rk2928-gate-clk";
73 reg = <0x200000d4 0x4>;
74 clocks = <&xin24m>, <&xin24m>,
84 "gate_timer0", "gate_timer1",
85 "gate_timer2", "gate_jtag",
86 "gate_aclk_lcdc1_src", "gate_otgphy0",
87 "gate_otgphy1", "gate_ddr_gpll",
88 "gate_uart0", "gate_frac_uart0",
89 "gate_uart1", "gate_frac_uart1",
90 "gate_uart2", "gate_frac_uart2",
91 "gate_uart3", "gate_frac_uart3";
96 clk_gates2: gate-clk@200000d8 {
97 compatible = "rockchip,rk2928-gate-clk";
98 reg = <0x200000d8 0x4>;
99 clocks = <&clk_gates2 1>, <&dummy>,
102 <&clk_gates2 3>, <&dummy>,
104 <&dummy>, <&dummy48m>,
105 <&dummy>, <&dummy48m>,
109 "gate_periph_src", "gate_aclk_periph",
110 "gate_hclk_periph", "gate_pclk_periph",
111 "gate_smc", "gate_mac",
112 "gate_hsadc", "gate_hsadc_frac",
113 "gate_saradc", "gate_spi0",
114 "gate_spi1", "gate_mmc0",
115 "gate_mac_lbtest", "gate_mmc1",
116 "gate_emmc", "gate_tsadc";
121 clk_gates3: gate-clk@200000dc {
122 compatible = "rockchip,rk2928-gate-clk";
123 reg = <0x200000dc 0x4>;
124 clocks = <&dummy>, <&dummy>,
134 "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
135 "gate_dclk_lcdc1", "gate_pclkin_cif0",
136 "gate_pclkin_cif1", "reserved",
137 "reserved", "gate_cif0_out",
138 "gate_cif1_out", "gate_aclk_vepu",
139 "gate_hclk_vepu", "gate_aclk_vdpu",
140 "gate_hclk_vdpu", "gate_gpu_src",
141 "reserved", "gate_xin27m";
146 clk_gates4: gate-clk@200000e0 {
147 compatible = "rockchip,rk2928-gate-clk";
148 reg = <0x200000e0 0x4>;
149 clocks = <&clk_gates2 2>, <&clk_gates2 3>,
150 <&clk_gates2 1>, <&clk_gates2 1>,
151 <&clk_gates2 1>, <&clk_gates2 2>,
152 <&clk_gates2 2>, <&clk_gates2 2>,
153 <&clk_gates0 4>, <&clk_gates0 4>,
154 <&clk_gates0 3>, <&clk_gates0 3>,
155 <&clk_gates0 3>, <&clk_gates2 3>,
159 "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
160 "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
161 "gate_aclk_pei_niu", "gate_hclk_usb_peri",
162 "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
163 "gate_hclk_cpubus", "gate_hclk_ahb2apb",
164 "gate_aclk_strc_sys", "gate_aclk_l2mem_con",
165 "gate_aclk_intmem", "gate_pclk_tsadc",
171 clk_gates5: gate-clk@200000e4 {
172 compatible = "rockchip,rk2928-gate-clk";
173 reg = <0x200000e4 0x4>;
174 clocks = <&clk_gates0 3>, <&clk_gates2 1>,
175 <&clk_gates0 5>, <&clk_gates0 5>,
176 <&clk_gates0 5>, <&clk_gates0 5>,
177 <&clk_gates0 4>, <&clk_gates0 5>,
178 <&clk_gates2 1>, <&clk_gates2 2>,
179 <&clk_gates2 2>, <&clk_gates2 2>,
180 <&clk_gates2 2>, <&clk_gates4 5>,
181 <&clk_gates4 5>, <&dummy>;
184 "gate_aclk_dmac1", "gate_aclk_dmac2",
185 "gate_pclk_efuse", "gate_pclk_tzpc",
186 "gate_pclk_grf", "gate_pclk_pmu",
187 "gate_hclk_rom", "gate_pclk_ddrupctl",
188 "gate_aclk_smc", "gate_hclk_nandc",
189 "gate_hclk_mmc0", "gate_hclk_mmc1",
190 "gate_hclk_emmc", "gate_hclk_otg0",
191 "gate_hclk_otg1", "gate_aclk_gpu";
196 clk_gates6: gate-clk@200000e8 {
197 compatible = "rockchip,rk2928-gate-clk";
198 reg = <0x200000e8 0x4>;
199 clocks = <&clk_gates3 0>, <&clk_gates0 4>,
200 <&clk_gates0 4>, <&clk_gates1 4>,
201 <&clk_gates0 4>, <&clk_gates3 0>,
202 <&clk_gates0 4>, <&clk_gates1 4>,
203 <&clk_gates3 0>, <&clk_gates0 4>,
204 <&clk_gates0 4>, <&clk_gates1 4>,
205 <&clk_gates0 4>, <&clk_gates3 0>,
209 "gate_aclk_lcdc0", "gate_hclk_lcdc0",
210 "gate_hclk_lcdc1", "gate_aclk_lcdc1",
211 "gate_hclk_cif0", "gate_aclk_cif0",
212 "gate_hclk_cif1", "gate_aclk_cif1",
213 "gate_aclk_ipp", "gate_hclk_ipp",
214 "gate_hclk_rga", "gate_aclk_rga",
215 "gate_hclk_vio_bus", "gate_aclk_vio0",
216 "gate_aclk_vcodec", "gate_shclk_vio_h2h";
221 clk_gates7: gate-clk@200000ec {
222 compatible = "rockchip,rk2928-gate-clk";
223 reg = <0x200000ec 0x4>;
224 clocks = <&clk_gates2 2>, <&clk_gates0 4>,
225 <&clk_gates0 4>, <&clk_gates0 4>,
226 <&clk_gates0 4>, <&clk_gates2 2>,
227 <&clk_gates2 2>, <&clk_gates0 5>,
228 <&clk_gates0 5>, <&clk_gates0 5>,
229 <&clk_gates0 5>, <&clk_gates2 3>,
230 <&clk_gates2 3>, <&clk_gates2 3>,
231 <&clk_gates2 3>, <&clk_gates2 3>;
234 "gate_hclk_emac", "gate_hclk_spdif",
235 "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
236 "gate_hclk_i2s_8ch", "gate_hclk_hsadc",
237 "gate_hclk_pidf", "gate_pclk_timer0",
238 "gate_pclk_timer1", "gate_pclk_timer2",
239 "gate_pclk_pwm01", "gate_pclk_pwm23",
240 "gate_pclk_spi0", "gate_pclk_spi1",
241 "gate_pclk_saradc", "gate_pclk_wdt";
246 clk_gates8: gate-clk@200000f0 {
247 compatible = "rockchip,rk2928-gate-clk";
248 reg = <0x200000f0 0x4>;
249 clocks = <&clk_gates0 5>, <&clk_gates0 5>,
250 <&clk_gates2 3>, <&clk_gates2 3>,
251 <&clk_gates0 5>, <&clk_gates0 5>,
252 <&clk_gates2 3>, <&clk_gates2 3>,
253 <&clk_gates2 3>, <&clk_gates0 5>,
254 <&clk_gates0 5>, <&clk_gates0 5>,
255 <&clk_gates2 3>, <&clk_gates2 3>,
256 <&dummy>, <&clk_gates0 5>;
259 "gate_pclk_uart0", "gate_pclk_uart1",
260 "gate_pclk_uart2", "gate_pclk_uart3",
261 "gate_pclk_i2c0", "gate_pclk_i2c1",
262 "gate_pclk_i2c2", "gate_pclk_i2c3",
263 "gate_pclk_i2c4", "gate_pclk_gpio0",
264 "gate_pclk_gpio1", "gate_pclk_gpio2",
265 "gate_pclk_gpio3", "gate_pclk_gpio4",
266 "reserved", "gate_pclk_gpio6";
271 clk_gates9: gate-clk@200000f4 {
272 compatible = "rockchip,rk2928-gate-clk";
273 reg = <0x200000f4 0x4>;
274 clocks = <&dummy>, <&clk_gates0 5>,
276 <&dummy>, <&clk_gates1 4>,
277 <&clk_gates0 5>, <&dummy>,
282 "gate_clk_core_dbg", "gate_pclk_dbg",
283 "gate_clk_trace", "gate_atclk",
284 "gate_clk_l2c", "gate_aclk_vio1",
285 "gate_pclk_publ", "gate_aclk_intmem0",
286 "gate_aclk_intmem1", "gate_aclk_intmem2",