arch/arm/boot/dts/rk3036.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4 #include "rk3036-clocks.dtsi"
   5 #include "rk3036-pinctrl.dtsi"
   6 #include <dt-bindings/suspend/rockchip-pm.h>
   7
   8 / {
   9         compatible = "rockchip,rk3036";
  10         rockchip,sram = <&sram>;
  11         interrupt-parent = <&gic>;
  12
  13         aliases {
  14                 serial0 = &uart0;
  15                 serial1 = &uart1;
  16                 serial2 = &uart2;
  17                 i2c0 = &i2c0;
  18                 i2c1 = &i2c1;
  19                 i2c2 = &i2c2;
  20                 lcdc = &lcdc;
  21                 spi0 = &spi0;
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a7";
  31                         reg = <0xf00>;
  32                 };
  33                 cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <0xf01>;
  37                 };
  38         };
  39
  40         gic: interrupt-controller@10139000 {
  41                 compatible = "arm,cortex-a15-gic";
  42                 interrupt-controller;
  43                 #interrupt-cells = <3>;
  44                 #address-cells = <0>;
  45                 reg = <0x10139000 0x1000>,
  46                       <0x1013a000 0x1000>;
  47         };
  48
  49         arm-pmu {
  50                 compatible = "arm,cortex-a7-pmu";
  51                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  52                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  53         };
  54
  55         cpu_axi_bus: cpu_axi_bus {
  56                 compatible = "rockchip,cpu_axi_bus";
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60
  61                 qos {
  62                         #address-cells = <1>;
  63                         #size-cells = <1>;
  64                         ranges;
  65
  66                         core {
  67                                 reg = <0x1012a000 0x20>;
  68                                 rockchip,priority = <3 2>;
  69                         };
  70                         peri {
  71                                 reg = <0x1012c000 0x20>;
  72                         };
  73                         gpu {
  74                                 reg = <0x1012d000 0x20>;
  75                         };
  76                         vpu {
  77                                 reg = <0x1012e000 0x20>;
  78                         };
  79                         hevc {
  80                                 reg = <0x1012e080 0x20>;
  81                         };
  82                         vio {
  83                                 reg = <0x1012f000 0x20>;
  84                                 rockchip,priority = <3 3>;
  85                         };
  86                 };
  87
  88                 msch {
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         ranges;
  92
  93                         msch@10128000 {
  94                                 reg = <0x10128000 0x40>;
  95                                 rockchip,read-latency = <0x80>;
  96                         };
  97                 };
  98         };
  99
 100         sram: sram@10080000 {
 101                 compatible = "mmio-sram";
 102                 reg = <0x10080000 0x2000>;
 103                 map-exec;
 104         };
 105
 106         timer {
 107                 compatible = "arm,armv7-timer";
 108                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 109                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 110                 clock-frequency = <24000000>;
 111         };
 112
 113         timer@20044000 {
 114                 compatible = "rockchip,timer";
 115                 reg = <0x20044000 0x20>;
 116                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 117                 rockchip,broadcast = <1>;
 118         };
 119
 120         watchdog: wdt@2004c000 {
 121                 compatible = "rockchip,watch dog";
 122                 reg = <0x2004c000 0x100>;
 123                 clocks = <&clk_gates7 15>;
 124                 clock-names = "pclk_wdt";
 125                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 126                 rockchip,irq = <1>;
 127                 rockchip,timeout = <60>;
 128                 rockchip,atboot = <1>;
 129                 rockchip,debug = <0>;
 130                 status = "disabled";
 131         };
 132
 133         amba {
 134                 #address-cells = <1>;
 135                 #size-cells = <1>;
 136                 compatible = "arm,amba-bus";
 137                 interrupt-parent = <&gic>;
 138                 ranges;
 139
 140                 pdma: pdma@20078000 {
 141                         compatible = "arm,pl330", "arm,primecell";
 142                         reg = <0x20078000 0x4000>;
 143                         clocks = <&clk_gates5 1>;
 144                         clock-names = "apb_pclk";
 145                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                 };
 149         };
 150
 151         reset: reset@20000110{
 152                 compatible = "rockchip,reset";
 153                 reg = <0x20000110 0x24>;
 154                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 155                 #reset-cells = <1>;
 156         };
 157
 158         nandc: nandc@10500000 {
 159                 compatible = "rockchip,rk-nandc";
 160                 reg = <0x10500000 0x4000>;
 161                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 162                 //pinctrl-names = "default";
 163                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 164                 nandc_id = <0>;
 165                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
 166                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 167         };
 168
 169         nandc0reg: nandc0@10500000 {
 170                 compatible = "rockchip,rk-nandc";
 171                 reg = <0x10500000 0x4000>;
 172         };
 173
 174         spi0: spi@20074000 {
 175                 compatible = "rockchip,rockchip-spi";
 176                 reg = <0x20074000 0x1000>;
 177                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 178                 #address-cells = <1>;
 179                 #size-cells = <0>;
 180                 pinctrl-names = "default";
 181                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 182                 rockchip,spi-src-clk = <0>;
 183                 num-cs = <2>;
 184                 clocks =<&clk_spi0>, <&clk_gates2 9>;
 185                 clock-names = "spi","pclk_spi0";
 186                 dmas = <&pdma 8>, <&pdma 9>;
 187                 #dma-cells = <2>;
 188                 dma-names = "tx", "rx";
 189                 status = "disabled";
 190         };
 191
 192         uart0: serial@20060000 {
 193                 compatible = "rockchip,serial";
 194                 reg = <0x20060000 0x100>;
 195                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 196                 clock-frequency = <24000000>;
 197                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 198                 clock-names = "sclk_uart", "pclk_uart";
 199                 reg-shift = <2>;
 200                 reg-io-width = <4>;
 201                 dmas = <&pdma 2>, <&pdma 3>;
 202                 #dma-cells = <2>;
 203                 pinctrl-names = "default";
 204                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 205                 status = "disabled";
 206         };
 207
 208         uart1: serial@20064000 {
 209                 compatible = "rockchip,serial";
 210                 reg = <0x20064000 0x100>;
 211                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 212                 clock-frequency = <24000000>;
 213                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 214                 clock-names = "sclk_uart", "pclk_uart";
 215                 reg-shift = <2>;
 216                 reg-io-width = <4>;
 217                 dmas = <&pdma 4>, <&pdma 5>;
 218                 #dma-cells = <2>;
 219                 pinctrl-names = "default";
 220                 pinctrl-0 = <&uart1_xfer>;
 221                 status = "disabled";
 222         };
 223
 224         uart2: serial@20068000 {
 225                 compatible = "rockchip,serial";
 226                 reg = <0x20068000 0x100>;
 227                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 228                 clock-frequency = <24000000>;
 229                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 230                 clock-names = "sclk_uart", "pclk_uart";
 231                 reg-shift = <2>;
 232                 reg-io-width = <4>;
 233                 dmas = <&pdma 6>, <&pdma 7>;
 234                 #dma-cells = <2>;
 235                 pinctrl-names = "default";
 236                 pinctrl-0 = <&uart2_xfer>;
 237                 status = "disabled";
 238         };
 239
 240         fiq-debugger {
 241                 compatible = "rockchip,fiq-debugger";
 242                 rockchip,serial-id = <2>;
 243                 rockchip,signal-irq = <106>;
 244                 rockchip,wake-irq = <0>;
 245                 status = "disabled";
 246         };
 247
 248         clocks-init{
 249                 compatible = "rockchip,clocks-init";
 250                 rockchip,clocks-init-parent =
 251                         <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
 252                         <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
 253                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 254                         <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
 255                         <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
 256                 rockchip,clocks-init-rate =
 257                         <&clk_core 1200000000>, <&clk_gpll 1188000000>,
 258                         <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
 259                         <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 150000000>,
 260                         <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
 261                         <&clk_gpu 400000000>,    <&aclk_vio_pre 300000000>,
 262                         <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
 263                         <&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
 264                         <&clk_mac_ref_div 25000000>;
 265         /*      rockchip,clocks-uboot-has-init =
 266                         <&aclk_vio1>;*/
 267         };
 268
 269         clocks-enable {
 270                 compatible = "rockchip,clocks-enable";
 271                 clocks =
 272                                 /*PD_CORE*/
 273                                 <&clk_gates0 0>, <&clk_gates0 7>,
 274
 275                                 /*PD_CPU*/
 276                                 <&clk_gates0 3>, <&clk_gates0 4>,
 277                                 <&clk_gates0 5>,
 278
 279                                 /*TIMER*/
 280                                 <&clk_gates1 0>, <&clk_gates1 1>,
 281                                 <&clk_gates2 4>, <&clk_gates2 5>,
 282
 283                                 /*PD_PERI*/
 284                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 285                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 286
 287                                 /*aclk_cpu_pre*/
 288                                 <&clk_gates4 12>,/*aclk_intmem*/
 289                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 290
 291                                 /*hclk_cpu_pre*/
 292                                 <&clk_gates5 6>,/*hclk_rom*/
 293
 294                                 /*pclk_cpu_pre*/
 295                                 <&clk_gates5 4>,/*pclk_grf*/
 296                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 297                                 <&clk_gates5 14>,/*pclk_acodec*/
 298                                 <&clk_gates3 8>,/*pclk_hdmi*/
 299
 300                                 /*aclk_peri_pre*/
 301                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 302                                 //<&clk_gates5 1>,/*aclk_dmac2*/
 303                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 304                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 305
 306                                 /*hclk_peri_pre*/
 307                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 308                                 <&clk_gates9 13>,/*hclk_usb_peri*/
 309                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 310
 311                                 /*pclk_peri_pre*/
 312                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 313
 314                                 /*hclk_vio_pre*/
 315                                 <&clk_gates6 12>,/*hclk_vio_bus*/
 316                                 <&clk_gates9 5>,/*hclk_lcdc*/
 317
 318                                 /*aclk_vio_pre*/
 319                                 <&clk_gates6 13>,/*aclk_vio*/
 320                                 <&clk_gates9 6>,/*aclk_lcdc*/
 321
 322                                 /*UART*/
 323                                 <&clk_gates1 12>,
 324                                 <&clk_gates1 13>,
 325                                 <&clk_gates8 2>,/*pclk_uart2*/
 326
 327                                 <&clk_gpu>,
 328
 329                                 /*jtag*/
 330                                 <&clk_gates1 3>;/*clk_jtag*/
 331         };
 332
 333         i2c0: i2c@20072000 {
 334                 compatible = "rockchip,rk30-i2c";
 335                 reg = <0x20072000 0x1000>;
 336                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 pinctrl-names = "default", "gpio";
 340                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 341                 pinctrl-1 = <&i2c0_gpio>;
 342                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 343                 clocks = <&clk_gates8 4>;
 344                 rockchip,check-idle = <1>;
 345                 status = "disabled";
 346         };
 347
 348         i2c1: i2c@20056000 {
 349                 compatible = "rockchip,rk30-i2c";
 350                 reg = <0x20056000 0x1000>;
 351                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 pinctrl-names = "default", "gpio";
 355                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 356                 pinctrl-1 = <&i2c1_gpio>;
 357                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 358                 clocks = <&clk_gates8 5>;
 359                 rockchip,check-idle = <1>;
 360                 status = "disabled";
 361         };
 362
 363         i2c2: i2c@2005a000 {
 364                 compatible = "rockchip,rk30-i2c";
 365                 reg = <0x2005a000 0x1000>;
 366                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 pinctrl-names = "default", "gpio";
 370                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 371                 pinctrl-1 = <&i2c2_gpio>;
 372                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 373                 clocks = <&clk_gates8 6>;
 374                 rockchip,check-idle = <1>;
 375                 status = "disabled";
 376         };
 377
 378         i2s: i2s@10220000 {
 379                 compatible = "rockchip-i2s";
 380                 reg = <0x10220000 0x1000>;
 381                 i2s-id = <0>;
 382                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
 383                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 384                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 385                 dmas = <&pdma 0>, <&pdma 1>;
 386                 //#dma-cells = <2>;
 387                 dma-names = "tx", "rx";
 388                 //pinctrl-names = "default", "sleep";
 389                 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 390                 //pinctrl-1 = <&i2s_gpio>;
 391         };
 392
 393         codec: codec@20030000 {
 394                 compatible = "rk3036-codec";
 395                 reg = <0x20030000 0x1000>;
 396                 spk_ctl_io = <&gpio1 GPIO_A0 0>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&i2s0_gpio>;
 399
 400                 boot_depop = <1>;
 401                 pa_enable_time = <1000>;
 402                 clocks = <&clk_gates5 14>;
 403                 clock-names = "g_pclk_acodec";
 404         };
 405
 406         spdif: spdif@10204000 {
 407                 compatible = "rockchip-spdif";
 408                 reg = <0x10204000 0x1000>;
 409                 clocks = <&clk_spdif>;
 410                 clock-names = "spdif_mclk";
 411                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 412                 dmas = <&pdma 13>;
 413                 //#dma-cells = <1>;
 414                 dma-names = "tx";
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&spdif_tx>;
 417         };
 418
 419         pwm0: pwm@20050000 {
 420                 compatible = "rockchip,rk-pwm";
 421                 reg = <0x20050000 0x10>;
 422                 #pwm-cells = <2>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&pwm0_pin>;
 425                 clocks = <&clk_gates7 10>;
 426                 clock-names = "pclk_pwm";
 427                 status = "disabled";
 428         };
 429
 430         pwm1: pwm@20050010 {
 431                 compatible = "rockchip,rk-pwm";
 432                 reg = <0x20050010 0x10>;
 433                 #pwm-cells = <2>;
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&pwm1_pin>;
 436                 clocks = <&clk_gates7 10>;
 437                 clock-names = "pclk_pwm";
 438                 status = "disabled";
 439         };
 440
 441         pwm2: pwm@20050020 {
 442                 compatible = "rockchip,rk-pwm";
 443                 reg = <0x20050020 0x10>;
 444                 #pwm-cells = <2>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&pwm2_pin>;
 447                 clocks = <&clk_gates7 10>;
 448                 clock-names = "pclk_pwm";
 449                 status = "disabled";
 450         };
 451
 452         pwm3: pwm@20050030 {
 453                 compatible = "rockchip,rk-pwm";
 454                 reg = <0x20050030 0x10>;
 455                 #pwm-cells = <2>;
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&pwm3_pin>;
 458                 clocks = <&clk_gates7 10>;
 459                 clock-names = "pclk_pwm";
 460                 status = "disabled";
 461         };
 462
 463         remotectl: pwm@20050030 {
 464                 compatible = "rockchip,remotectl-pwm";
 465                 reg = <0x20050030 0x10>;
 466                 #pwm-cells = <2>;
 467                 pinctrl-names = "default";
 468                 pinctrl-0 = <&pwm3_pin>;
 469                 clocks = <&clk_gates7 10>;
 470                 clock-names = "pclk_pwm";
 471                 remote_pwm_id = <3>;
 472                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 473                 status = "okay";
 474         };
 475
 476         emmc: rksdmmc@1021c000 {
 477                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 478                 reg = <0x1021c000 0x4000>;
 479                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 480                 #address-cells = <1>;
 481                 #size-cells = <0>;
 482                 //pinctrl-names = "default",,"suspend";
 483                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 484                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 485                 clock-names = "clk_mmc", "hclk_mmc";
 486                 dmas = <&pdma 12>;
 487                 dma-names = "dw_mci";
 488                 num-slots = <1>;
 489                 fifo-depth = <0x100>;
 490                 bus-width = <8>;
 491         };
 492
 493
 494         sdmmc: rksdmmc@10214000 {
 495                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 496                 reg = <0x10214000 0x4000>;
 497                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 498                 #address-cells = <1>;
 499                 #size-cells = <0>;
 500                 pinctrl-names = "default", "idle", "udbg";
 501                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 502                 pinctrl-1 = <&sdmmc0_gpio>;
 503                 pinctrl-2 = <&uart2_xfer &sdmmc0_dectn>;
 504                 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 505                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 506                 clock-names = "clk_mmc", "hclk_mmc";
 507                 dmas = <&pdma 10>;
 508                 dma-names = "dw_mci";
 509                 num-slots = <1>;
 510                 fifo-depth = <0x100>;
 511                 bus-width = <4>;
 512         };
 513
 514         sdio: rksdmmc@10218000 {
 515                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 516                 reg = <0x10218000 0x4000>;
 517                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 pinctrl-names = "default","idle";
 521                 pinctrl-0 = <&sdio0_clk &sdio0_cmd  &sdio0_bus4>;
 522                 pinctrl-1 = <&sdio0_gpio>;
 523                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 524                 clock-names = "clk_mmc", "hclk_mmc";
 525                 dmas = <&pdma 11>;
 526                 dma-names = "dw_mci";
 527                 num-slots = <1>;
 528                 fifo-depth = <0x100>;
 529                 bus-width = <4>;
 530         };
 531         gpu {
 532                 compatible = "arm,mali400";
 533                 reg = <0x10091000 0x200>,
 534                           <0x10090000 0x100>,
 535                           <0x10093000 0x100>,
 536                           <0x10098000 0x1100>,
 537                           <0x10094000 0x100>;
 538                 reg-names = "Mali_L2",
 539                                         "Mali_GP",
 540                                         "Mali_GP_MMU",
 541                                         "Mali_PP0",
 542                                         "Mali_PP0_MMU";
 543
 544             interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 545                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 546                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 547                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 548             interrupt-names = "Mali_GP_IRQ",
 549                                                   "Mali_GP_MMU_IRQ",
 550                                                   "Mali_PP0_IRQ",
 551                                                   "Mali_PP0_MMU_IRQ";
 552           };
 553         dwc_control_usb: dwc-control-usb@20008000 {
 554                 compatible = "rockchip,rk3036-dwc-control-usb";
 555                 reg = <0x20008000 0x4>;
 556                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 557                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 558                              <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 559                 interrupt-names = "otg_bvalid",
 560                                   "otg0_linestate",
 561                                   "otg1_linestate";
 562                 clocks = <&clk_gates9 13>;
 563                 clock-names = "hclk_usb_peri";
 564                 rockchip,remote_wakeup;
 565                 rockchip,usb_irq_wakeup;
 566                 resets = <&reset RK3036_RST_USBPOR>;
 567                 reset-names = "usbphy_por";
 568                 usb_bc{
 569                         compatible = "rockchip,ctrl";
 570                         rk_usb,bvalid   = <0x14c 8 1>;
 571                         rk_usb,iddig    = <0x14c 11 1>;
 572                         rk_usb,line     = <0x14c 9 2>;
 573                         rk_usb,softctrl = <0x17c 0 1>;
 574                         rk_usb,opmode   = <0x17c 2 2>;
 575                         rk_usb,xcvrsel  = <0x17c 4 2>;
 576                         rk_usb,termsel  = <0x17c 6 1>;
 577                 };
 578         };
 579         usb0: usb@10180000 {
 580                 compatible = "rockchip,rk3036_usb20_otg";
 581                 reg = <0x10180000 0x40000>;
 582                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 583                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 584                 clock-names = "clk_usbphy0", "hclk_usb0";
 585                 resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
 586                                 <&reset RK3036_RST_OTGC0>;
 587                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 588                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 589                 rockchip,usb-mode = <0>;
 590         };
 591
 592         usb1: usb@101c0000 {
 593                 compatible = "rockchip,rk3036_usb20_host";
 594                 reg = <0x101c0000 0x40000>;
 595                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 596                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 597                 clock-names = "clk_usbphy1", "hclk_usb1";
 598                 resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
 599                                 <&reset RK3036_RST_OTGC1>;
 600                 reset-names = "host_ahb", "host_phy", "host_controller";
 601         };
 602
 603         fb: fb{
 604                 compatible = "rockchip,rk-fb";
 605                 rockchip,disp-mode = <NO_DUAL>;
 606                 rockchip,disp-policy = <DISPLAY_POLICY_BOX>;
 607         };
 608
 609         rk_screen: rk_screen{
 610                 compatible = "rockchip,screen";
 611         };
 612
 613         lcdc: lcdc@10118000 {
 614                 compatible = "rockchip,rk3036-lcdc";
 615                 reg = <0x10118000 0x1000>;
 616                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 617                 status = "disabled";
 618                 clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
 619                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 620                 rockchip,iommu-enabled = <1>;
 621         };
 622
 623         hdmi: hdmi@20034000 {
 624                 compatible = "rockchip,rk3036-hdmi";
 625                 reg = <0x20034000 0x4000>;
 626                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 627                 rockchip,hdmi_lcdc_source = <0>;
 628                 pinctrl-names = "default", "gpio";
 629                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 630                 pinctrl-1 = <&hdmi_gpio>;
 631                 clocks = <&clk_gates3 8>;
 632                 clock-names = "pclk_hdmi";
 633                 status = "disabled";
 634         };
 635
 636         tve: tve{
 637                 compatible = "rockchip,rk3036-tve";
 638                 reg = <0x10118200 0x100>;
 639                 saturation = <0x00386346>;
 640                 brightcontrast = <0x00008b00>;
 641                 adjtiming = <0xa6c00880>;
 642                 lumafilter0 = <0x02ff0000>;
 643                 lumafilter1 = <0xf40202fd>;
 644                 lumafilter2 = <0xf332d919>;
 645                 daclevel = <0x3e>;
 646                 status = "disabled";
 647         };
 648
 649         ion {
 650                 compatible = "rockchip,ion";
 651                 #address-cells = <1>;
 652                 #size-cells = <0>;
 653
 654                 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
 655                         compatible = "rockchip,ion-heap";
 656                         rockchip,ion_heap = <4>;
 657                         reg = <0x00000000 0x00000000>; /* 0MB */
 658                 };
 659                 rockchip,ion-heap@0 { /* VMALLOC HEAP */
 660                         compatible = "rockchip,ion-heap";
 661                         rockchip,ion_heap = <0>;
 662                 };
 663         };
 664
 665         /*vpu: vpu_service@10108000 {
 666                 compatible = "vpu_service";
 667                 iommu_enabled = <1>;
 668                 reg = <0x10108000 0x800>;
 669                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 670                 interrupt-names = "irq_dec";
 671                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
 672                 clock-names = "aclk_vcodec", "hclk_vcodec";
 673                 name = "vpu_service";
 674                 status = "okay";
 675         };
 676
 677         hevc: hevc_service@1010c000 {
 678                 compatible = "rockchip,hevc_service";
 679                 iommu_enabled = <1>;
 680                 reg = <0x1010c000 0x400>;
 681                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 682                 interrupt-names = "irq_dec";
 683                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
 684                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 685                 name = "hevc_service";
 686                 status = "okay";
 687         };*/
 688         vpu: vpu_service {
 689                 compatible = "rockchip,vpu_sub";
 690                 iommu_enabled = <1>;
 691                 reg = <0x10108400 0x400>;
 692                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 693                 interrupt-names = "irq_dec";
 694                 dev_mode = <0>;
 695                 name = "vpu_service";
 696         };
 697
 698         hevc: hevc_service {
 699                 compatible = "rockchip,hevc_sub";
 700                 iommu_enabled = <1>;
 701                 reg = <0x1010c000 0x400>;
 702                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 703                 interrupt-names = "irq_dec";
 704                 dev_mode = <1>;
 705                 name = "hevc_service";
 706         };
 707
 708         vpu_combo: vpu_combo@ff9a0000 {
 709                 compatible = "rockchip,vpu_combo";
 710                 subcnt = <2>;
 711                 rockchip,sub = <&vpu>, <&hevc>;
 712                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
 713                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 714                 mode_bit = <3>;
 715                 mode_ctrl = <0x144>;
 716                 name = "vpu_combo";
 717                 status = "okay";
 718         };
 719
 720         vop_mmu {
 721                 dbgname = "vop";
 722                 compatible = "rockchip,vop_mmu";
 723                 reg = <0x10118300 0x100>;
 724                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 725                 interrupt-names = "vop_mmu";
 726         };
 727
 728         hevc_mmu {
 729                 dbgname = "hevc";
 730                 compatible = "rockchip,hevc_mmu";
 731                 reg = <0x1010c440 0x40>,
 732                       <0x1010c480 0x40>;
 733                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 734                 interrupt-names = "hevc_mmu";
 735         };
 736
 737         vpu_mmu {
 738                 dbgname = "vpu";
 739                 compatible = "rockchip,vpu_mmu";
 740                 reg = <0x10108800 0x100>;
 741                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 742                 interrupt-names = "vpu_mmu";
 743         };
 744
 745         rockchip_suspend: rockchip_suspend {
 746                 rockchip,ctrbits = <
 747                         (0
 748                          //|RKPM_CTR_PWR_DMNS
 749                         |RKPM_CTR_GTCLKS
 750                         |RKPM_CTR_PLLS
 751                         |RKPM_CTR_IDLESRAM_MD
 752                         |RKPM_CTR_DDR
 753                         |RKPM_CTR_VOLTS
 754                         |RKPM_CTR_VOL_PWM2
 755
 756                         //|RKPM_CTR_GPIOS
 757                         //|RKPM_CTR_SYSCLK_DIV
 758                         //|RKPM_CTR_IDLEAUTO_MD
 759                         //|RKPM_CTR_ARMOFF_LPMD
 760                         //|RKPM_CTR_ARMOFF_LOGDP_LPMD
 761                         )
 762                         >;
 763 /*
 764                 rockchip,pmic-suspend_gpios = <
 765                         RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
 766                         >;
 767                 rockchip,pmic-resume_gpios = <
 768                         RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
 769                         >;
 770 */
 771         };
 772
 773         vmac: eth@10200000 {
 774                 compatible = "rockchip,vmac";
 775                 reg = <0x10200000 0x4000>;
 776                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 777                 interrupt-names = "macirq";
 778                 clocks = <&clk_mac_pll>, <&clk_mac_ref>,
 779                         <&clk_mac_pll_div>, <&clk_mac_ref_div>,
 780                         <&clk_gates2 6>, <&clk_gates3 5>;
 781                 clock-names = "clk_mac_pll", "clk_mac_ref",
 782                           "clk_mac_pll_div", "clk_mac_ref_div",
 783                           "clk_tx_rx_gate", "hclk_mac";
 784                 pinctrl-names = "default";
 785                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_crs &mac_mdpins>;
 786         };
 787 };