arch/arm/boot/dts/rk3036.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4 #include "rk3036-clocks.dtsi"
   5
   6 / {
   7         compatible = "rockchip,rk3036";
   8         rockchip,sram = <&sram>;
   9         interrupt-parent = <&gic>;
  10
  11         aliases {
  12                 serial0 = &uart0;
  13                 serial1 = &uart1;
  14                 serial2 = &uart2;
  15                 i2c0 = &i2c0;
  16                 i2c1 = &i2c1;
  17                 i2c2 = &i2c2;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a7";
  27                         reg = <0xf00>;
  28                 };
  29                 cpu@1 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a7";
  32                         reg = <0xf01>;
  33                 };
  34         };
  35
  36         gic: interrupt-controller@10139000 {
  37                 compatible = "arm,cortex-a15-gic";
  38                 interrupt-controller;
  39                 #interrupt-cells = <3>;
  40                 #address-cells = <0>;
  41                 reg = <0x10139000 0x1000>,
  42                       <0x1013a000 0x1000>;
  43         };
  44
  45         arm-pmu {
  46                 compatible = "arm,cortex-a7-pmu";
  47                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  48                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  49         };
  50
  51         sram: sram@10080000 {
  52                 compatible = "mmio-sram";
  53                 reg = <0x10080000 0x2000>;
  54                 map-exec;
  55         };
  56
  57         timer {
  58                 compatible = "arm,armv7-timer";
  59                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  60                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  61                 clock-frequency = <24000000>;
  62         };
  63
  64         watchdog: wdt@2004c000 {
  65                 compatible = "rockchip,watch dog";
  66                 reg = <0x2004c000 0x100>;
  67                 clocks = <&clk_gates7 15>;
  68                 clock-names = "pclk_wdt";
  69                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  70                 rockchip,irq = <1>;
  71                 rockchip,timeout = <60>;
  72                 rockchip,atboot = <1>;
  73                 rockchip,debug = <0>;
  74                 status = "disabled";
  75         };
  76
  77         amba {
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80                 compatible = "arm,amba-bus";
  81                 interrupt-parent = <&gic>;
  82                 ranges;
  83
  84                 pdma: pdma@20078000 {
  85                         compatible = "arm,pl330", "arm,primecell";
  86                         reg = <0x20078000 0x4000>;
  87                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  88                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  89                         #dma-cells = <1>;
  90                 };
  91         };
  92
  93         nandc: nandc@10500000 {
  94                 compatible = "rockchip,rk-nandc";
  95                 reg = <0x10500000 0x4000>;
  96                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  97                 nandc_id = <0>;
  98                 clocks = <&clk_nandc>, <&clk_gates5 9>;
  99                 clock-names = "clk_nandc", "hclk_nandc";
 100         };
 101
 102         spi: spi@20074000 {
 103                 compatible = "rockchip,rockchip-spi";
 104                 reg = <0x20074000 0x1000>;
 105                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108                 //pinctrl-names = "default";
 109                 //pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 110                 rockchip,spi-src-clk = <0>;
 111                 num-cs = <2>;
 112                 clocks =<&clk_spi0>, <&clk_gates7 12>;
 113                 clock-names = "spi","pclk_spi0";
 114                 //dmas = <&pdma1 11>, <&pdma1 12>;
 115                 //#dma-cells = <2>;
 116                 //dma-names = "tx", "rx";
 117                 status = "disabled";
 118         };
 119
 120         uart0: serial@20060000 {
 121                 compatible = "rockchip,serial";
 122                 reg = <0x20060000 0x100>;
 123                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 124                 clock-frequency = <24000000>;
 125                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 126                 clock-names = "sclk_uart", "pclk_uart";
 127                 reg-shift = <2>;
 128                 reg-io-width = <4>;
 129                 dmas = <&pdma 2>, <&pdma 3>;
 130                 #dma-cells = <2>;
 131                 //pinctrl-names = "default";
 132                 //pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 133                 status = "disabled";
 134         };
 135
 136         uart1: serial@20064000 {
 137                 compatible = "rockchip,serial";
 138                 reg = <0x20064000 0x100>;
 139                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 140                 clock-frequency = <24000000>;
 141                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 142                 clock-names = "sclk_uart", "pclk_uart";
 143                 reg-shift = <2>;
 144                 reg-io-width = <4>;
 145                 dmas = <&pdma 4>, <&pdma 5>;
 146                 #dma-cells = <2>;
 147                 //pinctrl-names = "default";
 148                 //pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 149                 status = "disabled";
 150         };
 151
 152         uart2: serial@20068000 {
 153                 compatible = "rockchip,serial";
 154                 reg = <0x20068000 0x100>;
 155                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 156                 clock-frequency = <24000000>;
 157                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 158                 clock-names = "sclk_uart", "pclk_uart";
 159                 reg-shift = <2>;
 160                 reg-io-width = <4>;
 161                 dmas = <&pdma 6>, <&pdma 7>;
 162                 #dma-cells = <2>;
 163                 //pinctrl-names = "default";
 164                 //pinctrl-0 = <&uart2_xfer>;
 165                 status = "disabled";
 166         };
 167
 168         fiq-debugger {
 169                 compatible = "rockchip,fiq-debugger";
 170                 rockchip,serial-id = <2>;
 171                 rockchip,signal-irq = <106>;
 172                 rockchip,wake-irq = <0>;
 173                 status = "disabled";
 174         };
 175
 176         i2c0: i2c@20072000 {
 177                 compatible = "rockchip,rk30-i2c";
 178                 reg = <0x20072000 0x1000>;
 179                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 180                 #address-cells = <1>;
 181                 #size-cells = <0>;
 182                 //pinctrl-names = "default", "gpio";
 183                 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 184                 //pinctrl-1 = <&i2c0_gpio>;
 185                 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 186                 clocks = <&clk_gates8 4>;
 187                 rockchip,check-idle = <1>;
 188                 status = "disabled";
 189         };
 190
 191         i2c1: i2c@20056000 {
 192                 compatible = "rockchip,rk30-i2c";
 193                 reg = <0x20056000 0x1000>;
 194                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 //pinctrl-names = "default", "gpio";
 198                 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 199                 //pinctrl-1 = <&i2c1_gpio>;
 200                 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 201                 clocks = <&clk_gates8 5>;
 202                 rockchip,check-idle = <1>;
 203                 status = "disabled";
 204         };
 205
 206         i2c2: i2c@2005a000 {
 207                 compatible = "rockchip,rk30-i2c";
 208                 reg = <0x2005a000 0x1000>;
 209                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 //pinctrl-names = "default", "gpio";
 213                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 214                 //pinctrl-1 = <&i2c2_gpio>;
 215                 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 216                 clocks = <&clk_gates8 6>;
 217                 rockchip,check-idle = <1>;
 218                 status = "disabled";
 219         };
 220
 221         i2s: i2s@10220000 {
 222                 compatible = "rockchip-i2s";
 223                 reg = <0x10220000 0x1000>;
 224                 i2s-id = <0>;
 225                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
 226                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 227                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 228                 dmas = <&pdma 0>, <&pdma 1>;
 229                 //#dma-cells = <2>;
 230                 dma-names = "tx", "rx";
 231                 //pinctrl-names = "default", "sleep";
 232                 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 233                 //pinctrl-1 = <&i2s_gpio>;
 234         };
 235
 236         spdif: spdif@10204000 {
 237                 compatible = "rockchip-spdif";
 238                 reg = <0x10204000 0x1000>;
 239                 clocks = <&clk_spdif>;
 240                 clock-names = "spdif_mclk";
 241                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 242                 dmas = <&pdma 13>;
 243                 //#dma-cells = <1>;
 244                 dma-names = "tx";
 245                 //pinctrl-names = "default";
 246                 //pinctrl-0 = <&spdif_tx>;
 247         };
 248
 249         pwm: pwm@20050000 {
 250                 compatible = "rockchip,rk-pwm";
 251                 reg = <0x20050000 0x10>;
 252                 #pwm-cells = <2>;
 253                 //pinctrl-names = "default";
 254                 //pinctrl-0 = <&pwm_pin>;
 255                 clocks = <&clk_gates7 10>;
 256                 clock-names = "pclk_pwm";
 257                 status = "disabled";
 258         };
 259
 260         emmc: rksdmmc@1021c000 {
 261                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 262                 reg = <0x1021c000 0x4000>;
 263                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 //pinctrl-names = "default",,"suspend";
 267                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 268                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 269                 clock-names = "clk_mmc", "hclk_mmc";
 270                 num-slots = <1>;
 271                 fifo-depth = <0x100>;
 272                 bus-width = <8>;
 273         };
 274
 275
 276         sdmmc: rksdmmc@10214000 {
 277                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 278                 reg = <0x10214000 0x4000>;
 279                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 280                 #address-cells = <1>;
 281                 #size-cells = <0>;
 282                 //pinctrl-names = "default", "idle";
 283                 //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 284                 //pinctrl-1 = <&sdmmc0_gpio>;
 285                 //cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 286                 clocks = <&clk_sdmmc0>, <&clk_gates2 11>;
 287                 clock-names = "clk_mmc", "hclk_mmc";
 288                 num-slots = <1>;
 289                 fifo-depth = <0x100>;
 290                 bus-width = <4>;
 291         };
 292
 293         sdio: rksdmmc@10218000 {
 294                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 295                 reg = <0x10218000 0x4000>;
 296                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299                 //pinctrl-names = "default","idle";
 300                 //pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_wrprt &sdio_pwr &sdio_bkpwr &sdio_intn &sdio_bus4>;
 301                 //pinctrl-1 = <&sdio_gpio>;
 302                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 303                 clock-names = "clk_mmc", "hclk_mmc";
 304                 num-slots = <1>;
 305                 fifo-depth = <0x100>;
 306                 bus-width = <4>;
 307         };
 308 };