arch/arm/boot/dts/rk3036.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4 #include "rk3036-clocks.dtsi"
   5 #include "rk3036-pinctrl.dtsi"
   6
   7 / {
   8         compatible = "rockchip,rk3036";
   9         rockchip,sram = <&sram>;
  10         interrupt-parent = <&gic>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 serial2 = &uart2;
  16                 i2c0 = &i2c0;
  17                 i2c1 = &i2c1;
  18                 i2c2 = &i2c2;
  19                 spi0 = &spi0;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0xf00>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf01>;
  35                 };
  36         };
  37
  38         gic: interrupt-controller@10139000 {
  39                 compatible = "arm,cortex-a15-gic";
  40                 interrupt-controller;
  41                 #interrupt-cells = <3>;
  42                 #address-cells = <0>;
  43                 reg = <0x10139000 0x1000>,
  44                       <0x1013a000 0x1000>;
  45         };
  46
  47         arm-pmu {
  48                 compatible = "arm,cortex-a7-pmu";
  49                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  50                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  51         };
  52
  53         cpu_axi_bus: cpu_axi_bus {
  54                 compatible = "rockchip,cpu_axi_bus";
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 ranges;
  58
  59                 qos {
  60                         #address-cells = <1>;
  61                         #size-cells = <1>;
  62                         ranges;
  63
  64                         core {
  65                                 reg = <0x1012a000 0x20>;
  66                                 rockchip,priority = <3 2>;
  67                         };
  68                         peri {
  69                                 reg = <0x1012c000 0x20>;
  70                         };
  71                         gpu {
  72                                 reg = <0x1012d000 0x20>;
  73                         };
  74                         vpu {
  75                                 reg = <0x1012e000 0x20>;
  76                         };
  77                         hevc {
  78                                 reg = <0x1012e080 0x20>;
  79                         };
  80                         vio {
  81                                 reg = <0x1012f000 0x20>;
  82                                 rockchip,priority = <3 3>;
  83                         };
  84                 };
  85
  86                 msch {
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         ranges;
  90
  91                         msch@10128000 {
  92                                 reg = <0x10128000 0x40>;
  93                                 rockchip,read-latency = <0x80>;
  94                         };
  95                 };
  96         };
  97
  98         sram: sram@10080000 {
  99                 compatible = "mmio-sram";
 100                 reg = <0x10080000 0x2000>;
 101                 map-exec;
 102         };
 103
 104         timer {
 105                 compatible = "arm,armv7-timer";
 106                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 107                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 108                 clock-frequency = <24000000>;
 109         };
 110
 111         watchdog: wdt@2004c000 {
 112                 compatible = "rockchip,watch dog";
 113                 reg = <0x2004c000 0x100>;
 114                 clocks = <&clk_gates7 15>;
 115                 clock-names = "pclk_wdt";
 116                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 117                 rockchip,irq = <1>;
 118                 rockchip,timeout = <60>;
 119                 rockchip,atboot = <1>;
 120                 rockchip,debug = <0>;
 121                 status = "disabled";
 122         };
 123
 124         amba {
 125                 #address-cells = <1>;
 126                 #size-cells = <1>;
 127                 compatible = "arm,amba-bus";
 128                 interrupt-parent = <&gic>;
 129                 ranges;
 130
 131                 pdma: pdma@20078000 {
 132                         compatible = "arm,pl330", "arm,primecell";
 133                         reg = <0x20078000 0x4000>;
 134                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 135                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 136                         #dma-cells = <1>;
 137                 };
 138         };
 139
 140         reset: reset@20000110{
 141                 compatible = "rockchip,reset";
 142                 reg = <0x20000110 0x24>;
 143                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 144                 #reset-cells = <1>;
 145         };
 146
 147         nandc: nandc@10500000 {
 148                 compatible = "rockchip,rk-nandc";
 149                 reg = <0x10500000 0x4000>;
 150                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 151                 //pinctrl-names = "default";
 152                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 153                 nandc_id = <0>;
 154                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
 155                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 156         };
 157
 158         nandc0reg: nandc0@10500000 {
 159                 compatible = "rockchip,rk-nandc";
 160                 reg = <0x10500000 0x4000>;
 161         };
 162
 163         spi0: spi@20074000 {
 164                 compatible = "rockchip,rockchip-spi";
 165                 reg = <0x20074000 0x1000>;
 166                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 167                 #address-cells = <1>;
 168                 #size-cells = <0>;
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 171                 rockchip,spi-src-clk = <0>;
 172                 num-cs = <2>;
 173                 clocks =<&clk_spi0>, <&clk_gates2 9>;
 174                 clock-names = "spi","pclk_spi0";
 175                 dmas = <&pdma 8>, <&pdma 9>;
 176                 #dma-cells = <2>;
 177                 dma-names = "tx", "rx";
 178                 status = "disabled";
 179         };
 180
 181         uart0: serial@20060000 {
 182                 compatible = "rockchip,serial";
 183                 reg = <0x20060000 0x100>;
 184                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 185                 clock-frequency = <24000000>;
 186                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 187                 clock-names = "sclk_uart", "pclk_uart";
 188                 reg-shift = <2>;
 189                 reg-io-width = <4>;
 190                 dmas = <&pdma 2>, <&pdma 3>;
 191                 #dma-cells = <2>;
 192                 pinctrl-names = "default";
 193                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 194                 status = "disabled";
 195         };
 196
 197         uart1: serial@20064000 {
 198                 compatible = "rockchip,serial";
 199                 reg = <0x20064000 0x100>;
 200                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 201                 clock-frequency = <24000000>;
 202                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 203                 clock-names = "sclk_uart", "pclk_uart";
 204                 reg-shift = <2>;
 205                 reg-io-width = <4>;
 206                 dmas = <&pdma 4>, <&pdma 5>;
 207                 #dma-cells = <2>;
 208                 pinctrl-names = "default";
 209                 pinctrl-0 = <&uart1_xfer>;
 210                 status = "disabled";
 211         };
 212
 213         uart2: serial@20068000 {
 214                 compatible = "rockchip,serial";
 215                 reg = <0x20068000 0x100>;
 216                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 217                 clock-frequency = <24000000>;
 218                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 219                 clock-names = "sclk_uart", "pclk_uart";
 220                 reg-shift = <2>;
 221                 reg-io-width = <4>;
 222                 dmas = <&pdma 6>, <&pdma 7>;
 223                 #dma-cells = <2>;
 224                 pinctrl-names = "default";
 225                 pinctrl-0 = <&uart2_xfer>;
 226                 status = "disabled";
 227         };
 228
 229         fiq-debugger {
 230                 compatible = "rockchip,fiq-debugger";
 231                 rockchip,serial-id = <2>;
 232                 rockchip,signal-irq = <106>;
 233                 rockchip,wake-irq = <0>;
 234                 status = "disabled";
 235         };
 236
 237         clocks-init{
 238                 compatible = "rockchip,clocks-init";
 239                 rockchip,clocks-init-parent =
 240                         <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
 241                         <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
 242                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 243                         <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
 244                         <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
 245                 rockchip,clocks-init-rate =
 246                         <&clk_core 1000000000>, <&clk_gpll 594000000>,
 247                         <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
 248                         <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 150000000>,
 249                         <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
 250                         <&clk_gpu_pre 300000000>,        <&aclk_vio_pre 300000000>,
 251                         <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
 252                         <&clk_hevc_core 200000000>, <&clk_mac_ref_div 50000000>;
 253         /*      rockchip,clocks-uboot-has-init =
 254                         <&aclk_vio1>;*/
 255         };
 256
 257         clocks-enable {
 258                 compatible = "rockchip,clocks-enable";
 259                 clocks =
 260                                 /*PD_CORE*/
 261                                 <&clk_gates0 0>, <&clk_gates0 7>,
 262
 263                                 /*PD_CPU*/
 264                                 <&clk_gates0 3>, <&clk_gates0 4>,
 265                                 <&clk_gates0 5>,
 266
 267                                 /*TIMER*/
 268                                 <&clk_gates1 0>, <&clk_gates1 1>,
 269                                 <&clk_gates2 4>, <&clk_gates2 5>,
 270
 271                                 /*PD_PERI*/
 272                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 273                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 274
 275                                 /*aclk_cpu_pre*/
 276                                 <&clk_gates4 12>,/*aclk_intmem*/
 277                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 278
 279                                 /*hclk_cpu_pre*/
 280                                 <&clk_gates5 6>,/*hclk_rom*/
 281
 282                                 /*pclk_cpu_pre*/
 283                                 <&clk_gates5 4>,/*pclk_grf*/
 284                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 285                                 <&clk_gates5 14>,/*pclk_acodec*/
 286                                 <&clk_gates3 8>,/*pclk_hdmi*/
 287
 288                                 /*aclk_peri_pre*/
 289                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 290                                 <&clk_gates5 1>,/*aclk_dmac2*/
 291                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 292                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 293
 294                                 /*hclk_peri_pre*/
 295                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 296                                 <&clk_gates9 13>,/*hclk_usb_peri*/
 297                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 298
 299                                 /*pclk_peri_pre*/
 300                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 301
 302                                 /*hclk_vio_pre*/
 303                                 <&clk_gates6 12>,/*hclk_vio_bus*/
 304                                 <&clk_gates9 5>,/*hclk_lcdc*/
 305
 306                                 /*aclk_vio_pre*/
 307                                 <&clk_gates6 13>,/*aclk_vio*/
 308                                 <&clk_gates9 6>,/*aclk_lcdc*/
 309
 310                                 /*UART*/
 311                                 <&clk_gates1 12>,
 312                                 <&clk_gates1 13>,
 313                                 <&clk_gates8 2>,/*pclk_uart2*/
 314
 315                                 <&clk_gpu_pre>,
 316
 317                                 /*jtag*/
 318                                 <&clk_gates1 3>;/*clk_jtag*/
 319         };
 320
 321         i2c0: i2c@20072000 {
 322                 compatible = "rockchip,rk30-i2c";
 323                 reg = <0x20072000 0x1000>;
 324                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 pinctrl-names = "default", "gpio";
 328                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 329                 pinctrl-1 = <&i2c0_gpio>;
 330                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 331                 clocks = <&clk_gates8 4>;
 332                 rockchip,check-idle = <1>;
 333                 status = "disabled";
 334         };
 335
 336         i2c1: i2c@20056000 {
 337                 compatible = "rockchip,rk30-i2c";
 338                 reg = <0x20056000 0x1000>;
 339                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 pinctrl-names = "default", "gpio";
 343                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 344                 pinctrl-1 = <&i2c1_gpio>;
 345                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 346                 clocks = <&clk_gates8 5>;
 347                 rockchip,check-idle = <1>;
 348                 status = "disabled";
 349         };
 350
 351         i2c2: i2c@2005a000 {
 352                 compatible = "rockchip,rk30-i2c";
 353                 reg = <0x2005a000 0x1000>;
 354                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 pinctrl-names = "default", "gpio";
 358                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 359                 pinctrl-1 = <&i2c2_gpio>;
 360                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 361                 clocks = <&clk_gates8 6>;
 362                 rockchip,check-idle = <1>;
 363                 status = "disabled";
 364         };
 365
 366         i2s: i2s@10220000 {
 367                 compatible = "rockchip-i2s";
 368                 reg = <0x10220000 0x1000>;
 369                 i2s-id = <0>;
 370                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
 371                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 372                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 373                 dmas = <&pdma 0>, <&pdma 1>;
 374                 //#dma-cells = <2>;
 375                 dma-names = "tx", "rx";
 376                 //pinctrl-names = "default", "sleep";
 377                 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 378                 //pinctrl-1 = <&i2s_gpio>;
 379         };
 380
 381         spdif: spdif@10204000 {
 382                 compatible = "rockchip-spdif";
 383                 reg = <0x10204000 0x1000>;
 384                 clocks = <&clk_spdif>;
 385                 clock-names = "spdif_mclk";
 386                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 387                 dmas = <&pdma 13>;
 388                 //#dma-cells = <1>;
 389                 dma-names = "tx";
 390                 //pinctrl-names = "default";
 391                 //pinctrl-0 = <&spdif_tx>;
 392         };
 393
 394         pwm0: pwm@20050000 {
 395                 compatible = "rockchip,rk-pwm";
 396                 reg = <0x20050000 0x10>;
 397                 #pwm-cells = <2>;
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&pwm0_pin>;
 400                 clocks = <&clk_gates7 10>;
 401                 clock-names = "pclk_pwm";
 402                 status = "disabled";
 403         };
 404
 405         pwm1: pwm@20050010 {
 406                 compatible = "rockchip,rk-pwm";
 407                 reg = <0x20050010 0x10>;
 408                 #pwm-cells = <2>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&pwm1_pin>;
 411                 clocks = <&clk_gates7 10>;
 412                 clock-names = "pclk_pwm";
 413                 status = "disabled";
 414         };
 415
 416         pwm2: pwm@20050020 {
 417                 compatible = "rockchip,rk-pwm";
 418                 reg = <0x20050020 0x10>;
 419                 #pwm-cells = <2>;
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&pwm2_pin>;
 422                 clocks = <&clk_gates7 10>;
 423                 clock-names = "pclk_pwm";
 424                 status = "disabled";
 425         };
 426
 427         pwm3: pwm@20050030 {
 428                 compatible = "rockchip,rk-pwm";
 429                 reg = <0x20050030 0x10>;
 430                 #pwm-cells = <2>;
 431                 pinctrl-names = "default";
 432                 pinctrl-0 = <&pwm3_pin>;
 433                 clocks = <&clk_gates7 10>;
 434                 clock-names = "pclk_pwm";
 435                 status = "disabled";
 436         };
 437
 438         emmc: rksdmmc@1021c000 {
 439                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 440                 reg = <0x1021c000 0x4000>;
 441                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 //pinctrl-names = "default",,"suspend";
 445                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 446                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 447                 clock-names = "clk_mmc", "hclk_mmc";
 448                 dmas = <&pdma 12>;
 449                 dma-names = "dw_mci";
 450                 num-slots = <1>;
 451                 fifo-depth = <0x100>;
 452                 bus-width = <8>;
 453         };
 454
 455
 456         sdmmc: rksdmmc@10214000 {
 457                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 458                 reg = <0x10214000 0x4000>;
 459                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 pinctrl-names = "default", "idle";
 463                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 464                 pinctrl-1 = <&sdmmc0_gpio>;
 465                 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 466                 clocks = <&clk_sdmmc0>, <&clk_gates2 11>;
 467                 clock-names = "clk_mmc", "hclk_mmc";
 468                 dmas = <&pdma 10>;
 469                 dma-names = "dw_mci";
 470                 num-slots = <1>;
 471                 fifo-depth = <0x100>;
 472                 bus-width = <4>;
 473         };
 474
 475         sdio: rksdmmc@10218000 {
 476                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 477                 reg = <0x10218000 0x4000>;
 478                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 479                 #address-cells = <1>;
 480                 #size-cells = <0>;
 481                 pinctrl-names = "default","idle";
 482                 pinctrl-0 = <&sdio0_clk &sdio0_cmd  &sdio0_bus4>;
 483                 pinctrl-1 = <&sdio0_gpio>;
 484                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 485                 clock-names = "clk_mmc", "hclk_mmc";
 486                 dmas = <&pdma 11>;
 487                 dma-names = "dw_mci";
 488                 num-slots = <1>;
 489                 fifo-depth = <0x100>;
 490                 bus-width = <4>;
 491         };
 492         gpu {
 493                 compatible = "arm,mali400";
 494                 reg = <0x10091000 0x200>,
 495                           <0x10090000 0x100>,
 496                           <0x10093000 0x100>,
 497                           <0x10098000 0x1100>,
 498                           <0x10094000 0x100>;
 499                 reg-names = "Mali_L2",
 500                                         "Mali_GP",
 501                                         "Mali_GP_MMU",
 502                                         "Mali_PP0",
 503                                         "Mali_PP0_MMU";
 504
 505             interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 506                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 507                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 508                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 509             interrupt-names = "Mali_GP_IRQ",
 510                                                   "Mali_GP_MMU_IRQ",
 511                                                   "Mali_PP0_IRQ",
 512                                                   "Mali_PP0_MMU_IRQ";
 513           };
 514         dwc_control_usb: dwc-control-usb@20008000 {
 515                 compatible = "rockchip,rk3036-dwc-control-usb";
 516                 reg = <0x20008000 0x4>;
 517                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 518                 interrupt-names = "otg_bvalid";
 519                 clocks = <&clk_gates9 13>;
 520                 clock-names = "hclk_usb_peri";
 521                 rockchip,remote_wakeup;
 522                 rockchip,usb_irq_wakeup;
 523                 resets = <&reset RK3036_RST_USBPOR>;
 524                 reset-names = "usbphy_por";
 525                 usb_bc{
 526                         compatible = "rockchip,ctrl";
 527                         rk_usb,bvalid   = <0x14c 8 1>;
 528                         rk_usb,iddig    = <0x14c 11 1>;
 529                         rk_usb,line     = <0x14c 9 2>;
 530                         rk_usb,softctrl = <0x17c 0 1>;
 531                         rk_usb,opmode   = <0x17c 2 2>;
 532                         rk_usb,xcvrsel  = <0x17c 4 2>;
 533                         rk_usb,termsel  = <0x17c 6 1>;
 534                 };
 535         };
 536         usb0: usb@10180000 {
 537                 compatible = "rockchip,rk3036_usb20_otg";
 538                 reg = <0x10180000 0x40000>;
 539                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 540                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 541                 clock-names = "clk_usbphy0", "hclk_usb0";
 542                 resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
 543                                 <&reset RK3036_RST_OTGC0>;
 544                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 545                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 546                 rockchip,usb-mode = <0>;
 547         };
 548
 549         usb1: usb@101c0000 {
 550                 compatible = "rockchip,rk3036_usb20_host";
 551                 reg = <0x101c0000 0x40000>;
 552                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 553                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 554                 clock-names = "clk_usbphy1", "hclk_usb1";
 555                 resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
 556                                 <&reset RK3036_RST_OTGC1>;
 557                 reset-names = "host_ahb", "host_phy", "host_controller";
 558         };
 559
 560         fb: fb{
 561                 compatible = "rockchip,rk-fb";
 562                 rockchip,disp-mode = <NO_DUAL>;
 563         };
 564
 565         rk_screen: rk_screen{
 566                 compatible = "rockchip,screen";
 567         };
 568
 569         lcdc: lcdc@10118000 {
 570                 compatible = "rockchip,rk3036-lcdc";
 571                 reg = <0x10118000 0x200>;
 572                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 573                 status = "disabled";
 574                 clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
 575                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 576                 rockchip,iommu-enabled = <0>;
 577         };
 578
 579         hdmi: hdmi@20034000 {
 580                 compatible = "rockchip,rk3036-hdmi";
 581                 reg = <0x20034000 0x4000>;
 582                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 583                 rockchip,hdmi_lcdc_source = <0>;
 584                 pinctrl-names = "default", "gpio";
 585                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 586                 pinctrl-1 = <&hdmi_gpio>;
 587                 clocks = <&clk_gates3 8>;
 588                 clock-names = "pclk_hdmi";
 589                 status = "disabled";
 590         };
 591
 592         tve: tve{
 593                 compatible = "rockchip,rk3036-tve";
 594                 reg = <0x10118200 0x100>;
 595                 status = "disabled";
 596         };
 597
 598         ion {
 599                 compatible = "rockchip,ion";
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602
 603                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 604                         compatible = "rockchip,ion-reserve";
 605                         rockchip,ion_heap = <1>;
 606                         reg = <0x00000000 0x10000000>; /* 256MB */
 607                 };
 608                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 609                         rockchip,ion_heap = <3>;
 610                 };
 611         };
 612
 613         vpu: vpu_service@10108000 {
 614                 compatible = "vpu_service";
 615                 reg = <0x10108000 0x800>;
 616                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 617                 interrupt-names = "irq_dec";
 618                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
 619                 clock-names = "aclk_vcodec", "hclk_vcodec";
 620                 name = "vpu_service";
 621                 status = "okay";
 622         };
 623
 624         hevc: hevc_service@1010c000 {
 625                 compatible = "rockchip,hevc_service";
 626                 reg = <0x1010c000 0x400>;
 627                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 628                 interrupt-names = "irq_dec";
 629                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
 630                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 631                 name = "hevc_service";
 632                 status = "okay";
 633         };
 634
 635         vop_mmu {
 636                 dbgname = "vop";
 637                 compatible = "iommu,vop_mmu";
 638                 reg = <0x10118300 0x100>;
 639                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 640                 interrupt-names = "vop_mmu";
 641         };
 642
 643         hevc_mmu {
 644                 dbgname = "hevc";
 645                 compatible = "iommu,hevc_mmu";
 646                 reg = <0x1010c440 0x100>,
 647                       <0x1010c480 0x100>;
 648                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 649                 interrupt-names = "hevc_mmu";
 650         };
 651
 652         vpu_mmu {
 653                 dbgname = "vpu";
 654                 compatible = "iommu,vpu_mmu";
 655                 reg = <0x10108800 0x100>;
 656                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 657                 interrupt-names = "vpu_mmu";
 658         };
 659 };