arch/arm/boot/dts/rk3036.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4 #include "rk3036-clocks.dtsi"
   5 #include "rk3036-pinctrl.dtsi"
   6
   7 / {
   8         compatible = "rockchip,rk3036";
   9         rockchip,sram = <&sram>;
  10         interrupt-parent = <&gic>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 serial2 = &uart2;
  16                 i2c0 = &i2c0;
  17                 i2c1 = &i2c1;
  18                 i2c2 = &i2c2;
  19                 spi0 = &spi0;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0xf00>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf01>;
  35                 };
  36         };
  37
  38         gic: interrupt-controller@10139000 {
  39                 compatible = "arm,cortex-a15-gic";
  40                 interrupt-controller;
  41                 #interrupt-cells = <3>;
  42                 #address-cells = <0>;
  43                 reg = <0x10139000 0x1000>,
  44                       <0x1013a000 0x1000>;
  45         };
  46
  47         arm-pmu {
  48                 compatible = "arm,cortex-a7-pmu";
  49                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  50                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  51         };
  52
  53         sram: sram@10080000 {
  54                 compatible = "mmio-sram";
  55                 reg = <0x10080000 0x2000>;
  56                 map-exec;
  57         };
  58
  59         timer {
  60                 compatible = "arm,armv7-timer";
  61                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  62                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  63                 clock-frequency = <24000000>;
  64         };
  65
  66         watchdog: wdt@2004c000 {
  67                 compatible = "rockchip,watch dog";
  68                 reg = <0x2004c000 0x100>;
  69                 clocks = <&clk_gates7 15>;
  70                 clock-names = "pclk_wdt";
  71                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  72                 rockchip,irq = <1>;
  73                 rockchip,timeout = <60>;
  74                 rockchip,atboot = <1>;
  75                 rockchip,debug = <0>;
  76                 status = "disabled";
  77         };
  78
  79         amba {
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 compatible = "arm,amba-bus";
  83                 interrupt-parent = <&gic>;
  84                 ranges;
  85
  86                 pdma: pdma@20078000 {
  87                         compatible = "arm,pl330", "arm,primecell";
  88                         reg = <0x20078000 0x4000>;
  89                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  90                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  91                         #dma-cells = <1>;
  92                 };
  93         };
  94
  95         nandc: nandc@10500000 {
  96                 compatible = "rockchip,rk-nandc";
  97                 reg = <0x10500000 0x4000>;
  98                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
  99                 nandc_id = <0>;
 100                 clocks = <&clk_nandc>, <&clk_gates5 9>;
 101                 clock-names = "clk_nandc", "hclk_nandc";
 102         };
 103
 104         spi0: spi@20074000 {
 105                 compatible = "rockchip,rockchip-spi";
 106                 reg = <0x20074000 0x1000>;
 107                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 108                 #address-cells = <1>;
 109                 #size-cells = <0>;
 110                 //pinctrl-names = "default";
 111                 //pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 112                 rockchip,spi-src-clk = <0>;
 113                 num-cs = <2>;
 114                 //clocks =<&clk_spi0>, <&clk_gates7 12>;
 115                 //clock-names = "spi","pclk_spi0";
 116                 //dmas = <&pdma 8>, <&pdma 9>;
 117                 //#dma-cells = <2>;
 118                 //dma-names = "tx", "rx";
 119                 status = "disabled";
 120         };
 121
 122         uart0: serial@20060000 {
 123                 compatible = "rockchip,serial";
 124                 reg = <0x20060000 0x100>;
 125                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 126                 clock-frequency = <24000000>;
 127                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 128                 clock-names = "sclk_uart", "pclk_uart";
 129                 reg-shift = <2>;
 130                 reg-io-width = <4>;
 131                 dmas = <&pdma 2>, <&pdma 3>;
 132                 #dma-cells = <2>;
 133                 //pinctrl-names = "default";
 134                 //pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 135                 status = "disabled";
 136         };
 137
 138         uart1: serial@20064000 {
 139                 compatible = "rockchip,serial";
 140                 reg = <0x20064000 0x100>;
 141                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 142                 clock-frequency = <24000000>;
 143                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 144                 clock-names = "sclk_uart", "pclk_uart";
 145                 reg-shift = <2>;
 146                 reg-io-width = <4>;
 147                 dmas = <&pdma 4>, <&pdma 5>;
 148                 #dma-cells = <2>;
 149                 //pinctrl-names = "default";
 150                 //pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 151                 status = "disabled";
 152         };
 153
 154         uart2: serial@20068000 {
 155                 compatible = "rockchip,serial";
 156                 reg = <0x20068000 0x100>;
 157                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 158                 clock-frequency = <24000000>;
 159                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 160                 clock-names = "sclk_uart", "pclk_uart";
 161                 reg-shift = <2>;
 162                 reg-io-width = <4>;
 163                 dmas = <&pdma 6>, <&pdma 7>;
 164                 #dma-cells = <2>;
 165                 //pinctrl-names = "default";
 166                 //pinctrl-0 = <&uart2_xfer>;
 167                 status = "disabled";
 168         };
 169
 170         fiq-debugger {
 171                 compatible = "rockchip,fiq-debugger";
 172                 rockchip,serial-id = <2>;
 173                 rockchip,signal-irq = <106>;
 174                 rockchip,wake-irq = <0>;
 175                 status = "disabled";
 176         };
 177
 178         clocks-init{
 179                 compatible = "rockchip,clocks-init";
 180                 rockchip,clocks-init-parent =
 181                         <&clk_core_pre &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
 182                         <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
 183                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>;
 184                 rockchip,clocks-init-rate =
 185                         <&clk_core_pre 1464000000>, <&clk_gpll 297000000>,
 186                         <&aclk_cpu_pre 300000000>, <&hclk_cpu_pre 150000000>,
 187                         <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 300000000>,
 188                         <&hclk_peri_pre 150000000>, <&pclk_peri_pre 75000000>,
 189                         <&clk_gpu_pre 200000000>,        <&aclk_vio_pre 300000000>,
 190                         <&hclk_vio_pre 150000000>,       <&aclk_vcodec_pre 400000000>,
 191                         <&clk_hevc_core 300000000>,  <&clk_mac_ref_div 125000000>;
 192         /*      rockchip,clocks-uboot-has-init =
 193                         <&aclk_vio1>;*/
 194         };
 195
 196         clocks-enable {
 197                 compatible = "rockchip,clocks-enable";
 198                 clocks =
 199                                 /*PD_CORE*/
 200                                 <&clk_gates0 0>, <&clk_gates0 7>,
 201
 202                                 /*PD_CPU*/
 203                                 <&clk_gates0 3>, <&clk_gates0 4>,
 204                                 <&clk_gates0 5>,
 205
 206                                 /*TIMER*/
 207                                 <&clk_gates1 0>, <&clk_gates1 1>,
 208                                 <&clk_gates2 4>, <&clk_gates2 5>,
 209
 210                                 /*PD_PERI*/
 211                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 212                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 213
 214                                 /*aclk_cpu_pre*/
 215                                 <&clk_gates4 12>,/*aclk_intmem*/
 216                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 217
 218                                 /*hclk_cpu_pre*/
 219                                 <&clk_gates5 6>,/*hclk_rom*/
 220
 221                                 /*pclk_cpu_pre*/
 222                                 <&clk_gates5 4>,/*pclk_grf*/
 223                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 224                                 <&clk_gates5 14>,/*pclk_acodec*/
 225                                 <&clk_gates3 8>,/*pclk_hdmi*/
 226
 227                                 /*aclk_peri_pre*/
 228                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 229                                 <&clk_gates5 1>,/*aclk_dmac2*/
 230                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 231                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 232
 233                                 /*hclk_peri_pre*/
 234                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 235                                 <&clk_gates9 13>,/*hclk_usb_peri*/
 236                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 237
 238                                 /*pclk_peri_pre*/
 239                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 240
 241                                 /*hclk_vio_pre*/
 242                                 <&clk_gates6 12>,/*hclk_vio_bus*/
 243                                 <&clk_gates9 5>,/*hclk_lcdc*/
 244
 245                                 /*aclk_vio_pre*/
 246                                 <&clk_gates6 13>,/*aclk_vio*/
 247                                 <&clk_gates9 6>,/*aclk_lcdc*/
 248
 249                                 /*UART*/
 250                                 <&clk_gates1 12>,
 251                                 <&clk_gates1 13>,
 252                                 <&clk_gates8 2>,/*pclk_uart2*/
 253
 254                                 /*jtag*/
 255                                 <&clk_gates1 3>;/*clk_jtag*/
 256         };
 257
 258         i2c0: i2c@20072000 {
 259                 compatible = "rockchip,rk30-i2c";
 260                 reg = <0x20072000 0x1000>;
 261                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264                 //pinctrl-names = "default", "gpio";
 265                 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 266                 //pinctrl-1 = <&i2c0_gpio>;
 267                 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 268                 clocks = <&clk_gates8 4>;
 269                 rockchip,check-idle = <1>;
 270                 status = "disabled";
 271         };
 272
 273         i2c1: i2c@20056000 {
 274                 compatible = "rockchip,rk30-i2c";
 275                 reg = <0x20056000 0x1000>;
 276                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 //pinctrl-names = "default", "gpio";
 280                 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 281                 //pinctrl-1 = <&i2c1_gpio>;
 282                 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 283                 clocks = <&clk_gates8 5>;
 284                 rockchip,check-idle = <1>;
 285                 status = "disabled";
 286         };
 287
 288         i2c2: i2c@2005a000 {
 289                 compatible = "rockchip,rk30-i2c";
 290                 reg = <0x2005a000 0x1000>;
 291                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 //pinctrl-names = "default", "gpio";
 295                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 296                 //pinctrl-1 = <&i2c2_gpio>;
 297                 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 298                 clocks = <&clk_gates8 6>;
 299                 rockchip,check-idle = <1>;
 300                 status = "disabled";
 301         };
 302
 303         i2s: i2s@10220000 {
 304                 compatible = "rockchip-i2s";
 305                 reg = <0x10220000 0x1000>;
 306                 i2s-id = <0>;
 307                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
 308                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 309                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 310                 dmas = <&pdma 0>, <&pdma 1>;
 311                 //#dma-cells = <2>;
 312                 dma-names = "tx", "rx";
 313                 //pinctrl-names = "default", "sleep";
 314                 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 315                 //pinctrl-1 = <&i2s_gpio>;
 316         };
 317
 318         spdif: spdif@10204000 {
 319                 compatible = "rockchip-spdif";
 320                 reg = <0x10204000 0x1000>;
 321                 clocks = <&clk_spdif>;
 322                 clock-names = "spdif_mclk";
 323                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 324                 dmas = <&pdma 13>;
 325                 //#dma-cells = <1>;
 326                 dma-names = "tx";
 327                 //pinctrl-names = "default";
 328                 //pinctrl-0 = <&spdif_tx>;
 329         };
 330
 331         pwm0: pwm@20050000 {
 332                 compatible = "rockchip,rk-pwm";
 333                 reg = <0x20050000 0x10>;
 334                 #pwm-cells = <2>;
 335                 //pinctrl-names = "default";
 336                 //pinctrl-0 = <&pwm_pin>;
 337                 clocks = <&clk_gates7 10>;
 338                 clock-names = "pclk_pwm";
 339                 status = "disabled";
 340         };
 341
 342         pwm1: pwm@20050010 {
 343                 compatible = "rockchip,rk-pwm";
 344                 reg = <0x20050010 0x10>;
 345                 #pwm-cells = <2>;
 346                 //pinctrl-names = "default";
 347                 //pinctrl-0 = <&pwm_pin>;
 348                 clocks = <&clk_gates7 10>;
 349                 clock-names = "pclk_pwm";
 350                 status = "disabled";
 351         };
 352
 353         pwm2: pwm@20050020 {
 354                 compatible = "rockchip,rk-pwm";
 355                 reg = <0x20050020 0x10>;
 356                 #pwm-cells = <2>;
 357                 //pinctrl-names = "default";
 358                 //pinctrl-0 = <&pwm_pin>;
 359                 clocks = <&clk_gates7 10>;
 360                 clock-names = "pclk_pwm";
 361                 status = "disabled";
 362         };
 363
 364         pwm3: pwm@20050030 {
 365                 compatible = "rockchip,rk-pwm";
 366                 reg = <0x20050030 0x10>;
 367                 #pwm-cells = <2>;
 368                 //pinctrl-names = "default";
 369                 //pinctrl-0 = <&pwm_pin>;
 370                 clocks = <&clk_gates7 10>;
 371                 clock-names = "pclk_pwm";
 372                 status = "disabled";
 373         };
 374
 375         emmc: rksdmmc@1021c000 {
 376                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 377                 reg = <0x1021c000 0x4000>;
 378                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 //pinctrl-names = "default",,"suspend";
 382                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 383                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 384                 clock-names = "clk_mmc", "hclk_mmc";
 385                 num-slots = <1>;
 386                 fifo-depth = <0x100>;
 387                 bus-width = <8>;
 388         };
 389
 390
 391         sdmmc: rksdmmc@10214000 {
 392                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 393                 reg = <0x10214000 0x4000>;
 394                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 395                 #address-cells = <1>;
 396                 #size-cells = <0>;
 397                 //pinctrl-names = "default", "idle";
 398                 //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 399                 //pinctrl-1 = <&sdmmc0_gpio>;
 400                 //cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 401                 clocks = <&clk_sdmmc0>, <&clk_gates2 11>;
 402                 clock-names = "clk_mmc", "hclk_mmc";
 403                 num-slots = <1>;
 404                 fifo-depth = <0x100>;
 405                 bus-width = <4>;
 406         };
 407
 408         sdio: rksdmmc@10218000 {
 409                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 410                 reg = <0x10218000 0x4000>;
 411                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 //pinctrl-names = "default","idle";
 415                 //pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_wrprt &sdio_pwr &sdio_bkpwr &sdio_intn &sdio_bus4>;
 416                 //pinctrl-1 = <&sdio_gpio>;
 417                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 418                 clock-names = "clk_mmc", "hclk_mmc";
 419                 num-slots = <1>;
 420                 fifo-depth = <0x100>;
 421                 bus-width = <4>;
 422         };
 423         gpu {
 424                 compatible = "arm,mali400";
 425                 reg = <0x10091000 0x200>,
 426                           <0x10090000 0x100>,
 427                           <0x10093000 0x100>,
 428                           <0x10098000 0x1100>,
 429                           <0x10094000 0x100>;
 430                 reg-names = "Mali_L2",
 431                                         "Mali_GP",
 432                                         "Mali_GP_MMU",
 433                                         "Mali_PP0",
 434                                         "Mali_PP0_MMU";
 435
 436             interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 437                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 438                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 439                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 440             interrupt-names = "Mali_GP_IRQ",
 441                                                   "Mali_GP_MMU_IRQ",
 442                                                   "Mali_PP0_IRQ",
 443                                                   "Mali_PP0_MMU_IRQ";
 444           };
 445         dwc_control_usb: dwc-control-usb@20008000 {
 446                 compatible = "rockchip,rk3188-dwc-control-usb";
 447                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 448                 interrupt-names = "otg_bvalid";
 449                 //gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 450                 clocks = <&clk_gates9 13>;
 451                 clock-names = "hclk_usb_peri";
 452                 rockchip,remote_wakeup;
 453                 rockchip,usb_irq_wakeup;
 454
 455                 usb_bc{
 456                         compatible = "rockchip,ctrl";
 457                         rk_usb,bvalid   = <0x14c 8 1>;
 458                         rk_usb,iddig    = <0x14c 11 1>;
 459                         rk_usb,line     = <0x14c 9 2>;
 460                         rk_usb,softctrl = <0x17c 0 1>;
 461                         rk_usb,opmode   = <0x17c 2 2>;
 462                         rk_usb,xcvrsel  = <0x17c 4 2>;
 463                         rk_usb,termsel  = <0x118 6 1>;
 464                 };
 465         };
 466         usb0: usb@10180000 {
 467                 compatible = "rockchip,rk3188_usb20_otg";
 468                 reg = <0x10180000 0x40000>;
 469                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 470                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 471                 clock-names = "clk_usbphy0", "hclk_usb0";
 472                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 473                 rockchip,usb-mode = <0>;
 474         };
 475
 476         usb1: usb@101c0000 {
 477                 compatible = "rockchip,rk3188_usb20_host";
 478                 reg = <0x101c0000 0x40000>;
 479                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 480                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 481                 clock-names = "clk_usbphy1", "hclk_usb1";
 482         };
 483
 484         lcdc: lcdc@10118000 {
 485                 compatible = "rockchip,rk3036-lcdc";
 486                 reg = <0x10118000 0x4000>;
 487                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 488                 status = "disabled";
 489                 clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
 490                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 491                 rockchip,iommu-enabled = <1>;
 492         };
 493
 494         hdmi: hdmi@20034000 {
 495                 compatible = "rockchip,rk3036-hdmi";
 496                 reg = <0x20034000 0x4000>;
 497                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 498                 rockchip,hdmi_lcdc_source = <0>;
 499                 pinctrl-names = "default", "gpio";
 500                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 501                 pinctrl-1 = <&hdmi_gpio>;
 502                 clocks = <&clk_gates3 8>;
 503                 clock-names = "pclk_hdmi";
 504                 status = "disabled";
 505         };
 506 /*
 507         vpu: vpu_service@10108000 {
 508                 compatible = "vpu_service";
 509                 reg = <0x10108000 0x800>;
 510                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 511                 interrupt-names = "irq_enc", "irq_dec";
 512                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 513                 clock-names = "aclk_vcodec", "hclk_vcodec";
 514                 name = "vpu_service";
 515                 status = "disabled";
 516         };
 517
 518         hevc: hevc_service@1010c000 {
 519                 compatible = "rockchip,hevc_service";
 520                 reg = <0x1010c000 0x800>;
 521                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 522                 interrupt-names = "irq_dec";
 523                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
 524                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
 525                 name = "hevc_service";
 526                 status = "disabled";
 527 */
 528         vop_mmu {
 529                 dbgname = "vop";
 530                 compatible = "iommu,vop_mmu";
 531                 reg = <0x10118300 0x100>;
 532                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 533                 interrupt-names = "vop_mmu";
 534         };
 535
 536         hevc_mmu {
 537                 dbgname = "hevc";
 538                 compatible = "iommu,hevc_mmu";
 539                 reg = <0x1010c440 0x100>,
 540                       <0x1010c480 0x100>;
 541                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 542                 interrupt-names = "hevc_mmu";
 543         };
 544
 545         vpu_mmu {
 546                 dbgname = "vpu";
 547                 compatible = "iommu,vpu_mmu";
 548                 reg = <0x10108800 0x100>;
 549                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 550                 interrupt-names = "vpu_mmu";
 551         };
 552 };