arch/arm/boot/dts/rk3036.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4 #include "rk3036-clocks.dtsi"
   5 #include "rk3036-pinctrl.dtsi"
   6
   7 / {
   8         compatible = "rockchip,rk3036";
   9         rockchip,sram = <&sram>;
  10         interrupt-parent = <&gic>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 serial2 = &uart2;
  16                 i2c0 = &i2c0;
  17                 i2c1 = &i2c1;
  18                 i2c2 = &i2c2;
  19                 spi0 = &spi0;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0xf00>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf01>;
  35                 };
  36         };
  37
  38         gic: interrupt-controller@10139000 {
  39                 compatible = "arm,cortex-a15-gic";
  40                 interrupt-controller;
  41                 #interrupt-cells = <3>;
  42                 #address-cells = <0>;
  43                 reg = <0x10139000 0x1000>,
  44                       <0x1013a000 0x1000>;
  45         };
  46
  47         arm-pmu {
  48                 compatible = "arm,cortex-a7-pmu";
  49                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  50                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  51         };
  52
  53         cpu_axi_bus: cpu_axi_bus {
  54                 compatible = "rockchip,cpu_axi_bus";
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 ranges;
  58
  59                 qos {
  60                         #address-cells = <1>;
  61                         #size-cells = <1>;
  62                         ranges;
  63
  64                         core {
  65                                 reg = <0x1012a000 0x20>;
  66                                 rockchip,priority = <3 2>;
  67                         };
  68                         peri {
  69                                 reg = <0x1012c000 0x20>;
  70                         };
  71                         gpu {
  72                                 reg = <0x1012d000 0x20>;
  73                         };
  74                         vpu {
  75                                 reg = <0x1012e000 0x20>;
  76                         };
  77                         hevc {
  78                                 reg = <0x1012e080 0x20>;
  79                         };
  80                         vio {
  81                                 reg = <0x1012f000 0x20>;
  82                                 rockchip,priority = <3 3>;
  83                         };
  84                 };
  85
  86                 msch {
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         ranges;
  90
  91                         msch@10128000 {
  92                                 reg = <0x10128000 0x40>;
  93                                 rockchip,read-latency = <0x80>;
  94                         };
  95                 };
  96         };
  97
  98         sram: sram@10080000 {
  99                 compatible = "mmio-sram";
 100                 reg = <0x10080000 0x2000>;
 101                 map-exec;
 102         };
 103
 104         timer {
 105                 compatible = "arm,armv7-timer";
 106                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 107                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 108                 clock-frequency = <24000000>;
 109         };
 110
 111         timer@20044000 {
 112                 compatible = "rockchip,timer";
 113                 reg = <0x20044000 0x20>;
 114                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 115                 rockchip,broadcast = <1>;
 116         };
 117
 118         watchdog: wdt@2004c000 {
 119                 compatible = "rockchip,watch dog";
 120                 reg = <0x2004c000 0x100>;
 121                 clocks = <&clk_gates7 15>;
 122                 clock-names = "pclk_wdt";
 123                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 124                 rockchip,irq = <1>;
 125                 rockchip,timeout = <60>;
 126                 rockchip,atboot = <1>;
 127                 rockchip,debug = <0>;
 128                 status = "disabled";
 129         };
 130
 131         amba {
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 compatible = "arm,amba-bus";
 135                 interrupt-parent = <&gic>;
 136                 ranges;
 137
 138                 pdma: pdma@20078000 {
 139                         compatible = "arm,pl330", "arm,primecell";
 140                         reg = <0x20078000 0x4000>;
 141                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 142                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 143                         #dma-cells = <1>;
 144                 };
 145         };
 146
 147         reset: reset@20000110{
 148                 compatible = "rockchip,reset";
 149                 reg = <0x20000110 0x24>;
 150                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 151                 #reset-cells = <1>;
 152         };
 153
 154         nandc: nandc@10500000 {
 155                 compatible = "rockchip,rk-nandc";
 156                 reg = <0x10500000 0x4000>;
 157                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 158                 //pinctrl-names = "default";
 159                 //pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 160                 nandc_id = <0>;
 161                 clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
 162                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 163         };
 164
 165         nandc0reg: nandc0@10500000 {
 166                 compatible = "rockchip,rk-nandc";
 167                 reg = <0x10500000 0x4000>;
 168         };
 169
 170         spi0: spi@20074000 {
 171                 compatible = "rockchip,rockchip-spi";
 172                 reg = <0x20074000 0x1000>;
 173                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 174                 #address-cells = <1>;
 175                 #size-cells = <0>;
 176                 pinctrl-names = "default";
 177                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 178                 rockchip,spi-src-clk = <0>;
 179                 num-cs = <2>;
 180                 clocks =<&clk_spi0>, <&clk_gates2 9>;
 181                 clock-names = "spi","pclk_spi0";
 182                 dmas = <&pdma 8>, <&pdma 9>;
 183                 #dma-cells = <2>;
 184                 dma-names = "tx", "rx";
 185                 status = "disabled";
 186         };
 187
 188         uart0: serial@20060000 {
 189                 compatible = "rockchip,serial";
 190                 reg = <0x20060000 0x100>;
 191                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 192                 clock-frequency = <24000000>;
 193                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 194                 clock-names = "sclk_uart", "pclk_uart";
 195                 reg-shift = <2>;
 196                 reg-io-width = <4>;
 197                 dmas = <&pdma 2>, <&pdma 3>;
 198                 #dma-cells = <2>;
 199                 pinctrl-names = "default";
 200                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 201                 status = "disabled";
 202         };
 203
 204         uart1: serial@20064000 {
 205                 compatible = "rockchip,serial";
 206                 reg = <0x20064000 0x100>;
 207                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 208                 clock-frequency = <24000000>;
 209                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 210                 clock-names = "sclk_uart", "pclk_uart";
 211                 reg-shift = <2>;
 212                 reg-io-width = <4>;
 213                 dmas = <&pdma 4>, <&pdma 5>;
 214                 #dma-cells = <2>;
 215                 pinctrl-names = "default";
 216                 pinctrl-0 = <&uart1_xfer>;
 217                 status = "disabled";
 218         };
 219
 220         uart2: serial@20068000 {
 221                 compatible = "rockchip,serial";
 222                 reg = <0x20068000 0x100>;
 223                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 224                 clock-frequency = <24000000>;
 225                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 226                 clock-names = "sclk_uart", "pclk_uart";
 227                 reg-shift = <2>;
 228                 reg-io-width = <4>;
 229                 dmas = <&pdma 6>, <&pdma 7>;
 230                 #dma-cells = <2>;
 231                 pinctrl-names = "default";
 232                 pinctrl-0 = <&uart2_xfer>;
 233                 status = "disabled";
 234         };
 235
 236         fiq-debugger {
 237                 compatible = "rockchip,fiq-debugger";
 238                 rockchip,serial-id = <2>;
 239                 rockchip,signal-irq = <106>;
 240                 rockchip,wake-irq = <0>;
 241                 status = "disabled";
 242         };
 243
 244         clocks-init{
 245                 compatible = "rockchip,clocks-init";
 246                 rockchip,clocks-init-parent =
 247                         <&clk_core &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
 248                         <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
 249                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 250                         <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
 251                         <&aclk_vio_pre &clk_gpll>, <&clk_mac_pll &clk_apll>;
 252                 rockchip,clocks-init-rate =
 253                         <&clk_core 1000000000>, <&clk_gpll 594000000>,
 254                         <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
 255                         <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 150000000>,
 256                         <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
 257                         <&clk_gpu_pre 300000000>,        <&aclk_vio_pre 300000000>,
 258                         <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
 259                         <&clk_hevc_core 200000000>, <&clk_mac_pll_div 50000000>,
 260                         <&clk_mac_ref_div 25000000>;
 261         /*      rockchip,clocks-uboot-has-init =
 262                         <&aclk_vio1>;*/
 263         };
 264
 265         clocks-enable {
 266                 compatible = "rockchip,clocks-enable";
 267                 clocks =
 268                                 /*PD_CORE*/
 269                                 <&clk_gates0 0>, <&clk_gates0 7>,
 270
 271                                 /*PD_CPU*/
 272                                 <&clk_gates0 3>, <&clk_gates0 4>,
 273                                 <&clk_gates0 5>,
 274
 275                                 /*TIMER*/
 276                                 <&clk_gates1 0>, <&clk_gates1 1>,
 277                                 <&clk_gates2 4>, <&clk_gates2 5>,
 278
 279                                 /*PD_PERI*/
 280                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 281                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 282
 283                                 /*aclk_cpu_pre*/
 284                                 <&clk_gates4 12>,/*aclk_intmem*/
 285                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 286
 287                                 /*hclk_cpu_pre*/
 288                                 <&clk_gates5 6>,/*hclk_rom*/
 289
 290                                 /*pclk_cpu_pre*/
 291                                 <&clk_gates5 4>,/*pclk_grf*/
 292                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 293                                 <&clk_gates5 14>,/*pclk_acodec*/
 294                                 <&clk_gates3 8>,/*pclk_hdmi*/
 295
 296                                 /*aclk_peri_pre*/
 297                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 298                                 <&clk_gates5 1>,/*aclk_dmac2*/
 299                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 300                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 301
 302                                 /*hclk_peri_pre*/
 303                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 304                                 <&clk_gates9 13>,/*hclk_usb_peri*/
 305                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 306
 307                                 /*pclk_peri_pre*/
 308                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 309
 310                                 /*hclk_vio_pre*/
 311                                 <&clk_gates6 12>,/*hclk_vio_bus*/
 312                                 <&clk_gates9 5>,/*hclk_lcdc*/
 313
 314                                 /*aclk_vio_pre*/
 315                                 <&clk_gates6 13>,/*aclk_vio*/
 316                                 <&clk_gates9 6>,/*aclk_lcdc*/
 317
 318                                 /*UART*/
 319                                 <&clk_gates1 12>,
 320                                 <&clk_gates1 13>,
 321                                 <&clk_gates8 2>,/*pclk_uart2*/
 322
 323                                 <&clk_gpu_pre>,
 324
 325                                 /*jtag*/
 326                                 <&clk_gates1 3>;/*clk_jtag*/
 327         };
 328
 329         i2c0: i2c@20072000 {
 330                 compatible = "rockchip,rk30-i2c";
 331                 reg = <0x20072000 0x1000>;
 332                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335                 pinctrl-names = "default", "gpio";
 336                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 337                 pinctrl-1 = <&i2c0_gpio>;
 338                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 339                 clocks = <&clk_gates8 4>;
 340                 rockchip,check-idle = <1>;
 341                 status = "disabled";
 342         };
 343
 344         i2c1: i2c@20056000 {
 345                 compatible = "rockchip,rk30-i2c";
 346                 reg = <0x20056000 0x1000>;
 347                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350                 pinctrl-names = "default", "gpio";
 351                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 352                 pinctrl-1 = <&i2c1_gpio>;
 353                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 354                 clocks = <&clk_gates8 5>;
 355                 rockchip,check-idle = <1>;
 356                 status = "disabled";
 357         };
 358
 359         i2c2: i2c@2005a000 {
 360                 compatible = "rockchip,rk30-i2c";
 361                 reg = <0x2005a000 0x1000>;
 362                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 363                 #address-cells = <1>;
 364                 #size-cells = <0>;
 365                 pinctrl-names = "default", "gpio";
 366                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 367                 pinctrl-1 = <&i2c2_gpio>;
 368                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 369                 clocks = <&clk_gates8 6>;
 370                 rockchip,check-idle = <1>;
 371                 status = "disabled";
 372         };
 373
 374         i2s: i2s@10220000 {
 375                 compatible = "rockchip-i2s";
 376                 reg = <0x10220000 0x1000>;
 377                 i2s-id = <0>;
 378                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
 379                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 380                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 381                 dmas = <&pdma 0>, <&pdma 1>;
 382                 //#dma-cells = <2>;
 383                 dma-names = "tx", "rx";
 384                 //pinctrl-names = "default", "sleep";
 385                 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 386                 //pinctrl-1 = <&i2s_gpio>;
 387         };
 388
 389         codec: codec@20030000 {
 390                 compatible = "rk3036-codec";
 391                 reg = <0x20030000 0x1000>;
 392                 spk_ctl_io = <&gpio1 GPIO_A0 0>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&i2s0_gpio>;
 395
 396                 boot_depop = <1>;
 397                 pa_enable_time = <1000>;
 398                 clocks = <&clk_gates5 14>;
 399                 clock-names = "g_pclk_acodec";
 400         };
 401
 402         spdif: spdif@10204000 {
 403                 compatible = "rockchip-spdif";
 404                 reg = <0x10204000 0x1000>;
 405                 clocks = <&clk_spdif>;
 406                 clock-names = "spdif_mclk";
 407                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 408                 dmas = <&pdma 13>;
 409                 //#dma-cells = <1>;
 410                 dma-names = "tx";
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&spdif_tx>;
 413         };
 414
 415         pwm0: pwm@20050000 {
 416                 compatible = "rockchip,rk-pwm";
 417                 reg = <0x20050000 0x10>;
 418                 #pwm-cells = <2>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&pwm0_pin>;
 421                 clocks = <&clk_gates7 10>;
 422                 clock-names = "pclk_pwm";
 423                 status = "disabled";
 424         };
 425
 426         pwm1: pwm@20050010 {
 427                 compatible = "rockchip,rk-pwm";
 428                 reg = <0x20050010 0x10>;
 429                 #pwm-cells = <2>;
 430                 pinctrl-names = "default";
 431                 pinctrl-0 = <&pwm1_pin>;
 432                 clocks = <&clk_gates7 10>;
 433                 clock-names = "pclk_pwm";
 434                 status = "disabled";
 435         };
 436
 437         pwm2: pwm@20050020 {
 438                 compatible = "rockchip,rk-pwm";
 439                 reg = <0x20050020 0x10>;
 440                 #pwm-cells = <2>;
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&pwm2_pin>;
 443                 clocks = <&clk_gates7 10>;
 444                 clock-names = "pclk_pwm";
 445                 status = "disabled";
 446         };
 447
 448         pwm3: pwm@20050030 {
 449                 compatible = "rockchip,rk-pwm";
 450                 reg = <0x20050030 0x10>;
 451                 #pwm-cells = <2>;
 452                 pinctrl-names = "default";
 453                 pinctrl-0 = <&pwm3_pin>;
 454                 clocks = <&clk_gates7 10>;
 455                 clock-names = "pclk_pwm";
 456                 status = "disabled";
 457         };
 458
 459         remotectl: pwm@20050030 {
 460                 compatible = "rockchip,remotectl-pwm";
 461                 reg = <0x20050030 0x10>;
 462                 #pwm-cells = <2>;
 463                 pinctrl-names = "default";
 464                 pinctrl-0 = <&pwm3_pin>;
 465                 clocks = <&clk_gates7 10>;
 466                 clock-names = "pclk_pwm";
 467                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 468                 status = "okay";
 469         };
 470
 471         emmc: rksdmmc@1021c000 {
 472                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 473                 reg = <0x1021c000 0x4000>;
 474                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 //pinctrl-names = "default",,"suspend";
 478                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 479                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 480                 clock-names = "clk_mmc", "hclk_mmc";
 481                 dmas = <&pdma 12>;
 482                 dma-names = "dw_mci";
 483                 num-slots = <1>;
 484                 fifo-depth = <0x100>;
 485                 bus-width = <8>;
 486         };
 487
 488
 489         sdmmc: rksdmmc@10214000 {
 490                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 491                 reg = <0x10214000 0x4000>;
 492                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 pinctrl-names = "default", "idle";
 496                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 497                 pinctrl-1 = <&sdmmc0_gpio>;
 498                 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 499                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 500                 clock-names = "clk_mmc", "hclk_mmc";
 501                 dmas = <&pdma 10>;
 502                 dma-names = "dw_mci";
 503                 num-slots = <1>;
 504                 fifo-depth = <0x100>;
 505                 bus-width = <4>;
 506         };
 507
 508         sdio: rksdmmc@10218000 {
 509                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 510                 reg = <0x10218000 0x4000>;
 511                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 pinctrl-names = "default","idle";
 515                 pinctrl-0 = <&sdio0_clk &sdio0_cmd  &sdio0_bus4>;
 516                 pinctrl-1 = <&sdio0_gpio>;
 517                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 518                 clock-names = "clk_mmc", "hclk_mmc";
 519                 dmas = <&pdma 11>;
 520                 dma-names = "dw_mci";
 521                 num-slots = <1>;
 522                 fifo-depth = <0x100>;
 523                 bus-width = <4>;
 524         };
 525         gpu {
 526                 compatible = "arm,mali400";
 527                 reg = <0x10091000 0x200>,
 528                           <0x10090000 0x100>,
 529                           <0x10093000 0x100>,
 530                           <0x10098000 0x1100>,
 531                           <0x10094000 0x100>;
 532                 reg-names = "Mali_L2",
 533                                         "Mali_GP",
 534                                         "Mali_GP_MMU",
 535                                         "Mali_PP0",
 536                                         "Mali_PP0_MMU";
 537
 538             interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 539                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 540                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 541                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 542             interrupt-names = "Mali_GP_IRQ",
 543                                                   "Mali_GP_MMU_IRQ",
 544                                                   "Mali_PP0_IRQ",
 545                                                   "Mali_PP0_MMU_IRQ";
 546           };
 547         dwc_control_usb: dwc-control-usb@20008000 {
 548                 compatible = "rockchip,rk3036-dwc-control-usb";
 549                 reg = <0x20008000 0x4>;
 550                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 551                 interrupt-names = "otg_bvalid";
 552                 clocks = <&clk_gates9 13>;
 553                 clock-names = "hclk_usb_peri";
 554                 rockchip,remote_wakeup;
 555                 rockchip,usb_irq_wakeup;
 556                 resets = <&reset RK3036_RST_USBPOR>;
 557                 reset-names = "usbphy_por";
 558                 usb_bc{
 559                         compatible = "rockchip,ctrl";
 560                         rk_usb,bvalid   = <0x14c 8 1>;
 561                         rk_usb,iddig    = <0x14c 11 1>;
 562                         rk_usb,line     = <0x14c 9 2>;
 563                         rk_usb,softctrl = <0x17c 0 1>;
 564                         rk_usb,opmode   = <0x17c 2 2>;
 565                         rk_usb,xcvrsel  = <0x17c 4 2>;
 566                         rk_usb,termsel  = <0x17c 6 1>;
 567                 };
 568         };
 569         usb0: usb@10180000 {
 570                 compatible = "rockchip,rk3036_usb20_otg";
 571                 reg = <0x10180000 0x40000>;
 572                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 573                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 574                 clock-names = "clk_usbphy0", "hclk_usb0";
 575                 resets = <&reset RK3036_RST_USBOTG0>, <&reset RK3036_RST_UTMI0>,
 576                                 <&reset RK3036_RST_OTGC0>;
 577                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
 578                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 579                 rockchip,usb-mode = <0>;
 580         };
 581
 582         usb1: usb@101c0000 {
 583                 compatible = "rockchip,rk3036_usb20_host";
 584                 reg = <0x101c0000 0x40000>;
 585                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 586                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 587                 clock-names = "clk_usbphy1", "hclk_usb1";
 588                 resets = <&reset RK3036_RST_USBOTG1>, <&reset RK3036_RST_UTMI1>,
 589                                 <&reset RK3036_RST_OTGC1>;
 590                 reset-names = "host_ahb", "host_phy", "host_controller";
 591         };
 592
 593         fb: fb{
 594                 compatible = "rockchip,rk-fb";
 595                 rockchip,disp-mode = <NO_DUAL>;
 596         };
 597
 598         rk_screen: rk_screen{
 599                 compatible = "rockchip,screen";
 600         };
 601
 602         lcdc: lcdc@10118000 {
 603                 compatible = "rockchip,rk3036-lcdc";
 604                 reg = <0x10118000 0x200>;
 605                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 606                 status = "disabled";
 607                 clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
 608                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 609                 rockchip,iommu-enabled = <1>;
 610         };
 611
 612         hdmi: hdmi@20034000 {
 613                 compatible = "rockchip,rk3036-hdmi";
 614                 reg = <0x20034000 0x4000>;
 615                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 616                 rockchip,hdmi_lcdc_source = <0>;
 617                 pinctrl-names = "default", "gpio";
 618                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 619                 pinctrl-1 = <&hdmi_gpio>;
 620                 clocks = <&clk_gates3 8>;
 621                 clock-names = "pclk_hdmi";
 622                 status = "disabled";
 623         };
 624
 625         tve: tve{
 626                 compatible = "rockchip,rk3036-tve";
 627                 reg = <0x10118200 0x100>;
 628                 status = "disabled";
 629         };
 630
 631         ion {
 632                 compatible = "rockchip,ion";
 633                 #address-cells = <1>;
 634                 #size-cells = <0>;
 635
 636                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 637                         compatible = "rockchip,ion-reserve";
 638                         rockchip,ion_heap = <1>;
 639                         reg = <0x00000000 0x10000000>; /* 256MB */
 640                 };
 641                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 642                         rockchip,ion_heap = <3>;
 643                 };
 644         };
 645
 646         vpu: vpu_service@10108000 {
 647                 compatible = "vpu_service";
 648                 reg = <0x10108000 0x800>;
 649                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 650                 interrupt-names = "irq_dec";
 651                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
 652                 clock-names = "aclk_vcodec", "hclk_vcodec";
 653                 name = "vpu_service";
 654                 status = "okay";
 655         };
 656
 657         hevc: hevc_service@1010c000 {
 658                 compatible = "rockchip,hevc_service";
 659                 reg = <0x1010c000 0x400>;
 660                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 661                 interrupt-names = "irq_dec";
 662                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
 663                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 664                 name = "hevc_service";
 665                 status = "okay";
 666         };
 667
 668         vop_mmu {
 669                 dbgname = "vop";
 670                 compatible = "iommu,vop_mmu";
 671                 reg = <0x10118300 0x100>;
 672                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 673                 interrupt-names = "vop_mmu";
 674         };
 675
 676         hevc_mmu {
 677                 dbgname = "hevc";
 678                 compatible = "iommu,hevc_mmu";
 679                 reg = <0x1010c440 0x100>,
 680                       <0x1010c480 0x100>;
 681                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 682                 interrupt-names = "hevc_mmu";
 683         };
 684
 685         vpu_mmu {
 686                 dbgname = "vpu";
 687                 compatible = "iommu,vpu_mmu";
 688                 reg = <0x10108800 0x100>;
 689                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 690                 interrupt-names = "vpu_mmu";
 691         };
 692
 693         vmac: eth@10200000 {
 694                 compatible = "rockchip,vmac";
 695                 reg = <0x10200000 0x4000>;
 696                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 697                 interrupt-names = "macirq";
 698                 clocks = <&clk_mac_pll>, <&clk_mac_ref>,
 699                         <&clk_mac_pll_div>, <&clk_mac_ref_div>,
 700                         <&clk_gates2 6>, <&clk_gates3 5>;
 701                 clock-names = "clk_mac_pll", "clk_mac_ref",
 702                           "clk_mac_pll_div", "clk_mac_ref_div",
 703                           "clk_tx_rx_gate", "hclk_mac";
 704                 pinctrl-names = "default";
 705                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_crs &mac_mdpins>;
 706         };
 707 };