arch/arm/boot/dts/rk3036.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2
   3 #include "skeleton.dtsi"
   4 #include "rk3036-clocks.dtsi"
   5 #include "rk3036-pinctrl.dtsi"
   6
   7 / {
   8         compatible = "rockchip,rk3036";
   9         rockchip,sram = <&sram>;
  10         interrupt-parent = <&gic>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 serial2 = &uart2;
  16                 i2c0 = &i2c0;
  17                 i2c1 = &i2c1;
  18                 i2c2 = &i2c2;
  19                 spi0 = &spi0;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0xf00>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf01>;
  35                 };
  36         };
  37
  38         gic: interrupt-controller@10139000 {
  39                 compatible = "arm,cortex-a15-gic";
  40                 interrupt-controller;
  41                 #interrupt-cells = <3>;
  42                 #address-cells = <0>;
  43                 reg = <0x10139000 0x1000>,
  44                       <0x1013a000 0x1000>;
  45         };
  46
  47         arm-pmu {
  48                 compatible = "arm,cortex-a7-pmu";
  49                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  50                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  51         };
  52
  53         sram: sram@10080000 {
  54                 compatible = "mmio-sram";
  55                 reg = <0x10080000 0x2000>;
  56                 map-exec;
  57         };
  58
  59         timer {
  60                 compatible = "arm,armv7-timer";
  61                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  62                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  63                 clock-frequency = <24000000>;
  64         };
  65
  66         watchdog: wdt@2004c000 {
  67                 compatible = "rockchip,watch dog";
  68                 reg = <0x2004c000 0x100>;
  69                 clocks = <&clk_gates7 15>;
  70                 clock-names = "pclk_wdt";
  71                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  72                 rockchip,irq = <1>;
  73                 rockchip,timeout = <60>;
  74                 rockchip,atboot = <1>;
  75                 rockchip,debug = <0>;
  76                 status = "disabled";
  77         };
  78
  79         amba {
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 compatible = "arm,amba-bus";
  83                 interrupt-parent = <&gic>;
  84                 ranges;
  85
  86                 pdma: pdma@20078000 {
  87                         compatible = "arm,pl330", "arm,primecell";
  88                         reg = <0x20078000 0x4000>;
  89                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  90                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  91                         #dma-cells = <1>;
  92                 };
  93         };
  94
  95         reset: reset@20000110{
  96                 compatible = "rockchip,reset";
  97                 reg = <0x20000110 0x24>;
  98                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
  99                 #reset-cells = <1>;
 100         };
 101
 102         nandc: nandc@10500000 {
 103                 compatible = "rockchip,rk-nandc";
 104                 reg = <0x10500000 0x4000>;
 105                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 106                 nandc_id = <0>;
 107                 clocks = <&clk_nandc>, <&clk_gates5 9>;
 108                 clock-names = "clk_nandc", "hclk_nandc";
 109         };
 110
 111         spi0: spi@20074000 {
 112                 compatible = "rockchip,rockchip-spi";
 113                 reg = <0x20074000 0x1000>;
 114                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 115                 #address-cells = <1>;
 116                 #size-cells = <0>;
 117                 pinctrl-names = "default";
 118                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 119                 rockchip,spi-src-clk = <0>;
 120                 num-cs = <2>;
 121                 clocks =<&clk_spi0>, <&clk_gates7 12>;
 122                 clock-names = "spi","pclk_spi0";
 123                 //dmas = <&pdma 8>, <&pdma 9>;
 124                 //#dma-cells = <2>;
 125                 //dma-names = "tx", "rx";
 126                 status = "disabled";
 127         };
 128
 129         uart0: serial@20060000 {
 130                 compatible = "rockchip,serial";
 131                 reg = <0x20060000 0x100>;
 132                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 133                 clock-frequency = <24000000>;
 134                 clocks = <&clk_uart0>, <&clk_gates8 0>;
 135                 clock-names = "sclk_uart", "pclk_uart";
 136                 reg-shift = <2>;
 137                 reg-io-width = <4>;
 138                 dmas = <&pdma 2>, <&pdma 3>;
 139                 #dma-cells = <2>;
 140                 pinctrl-names = "default";
 141                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 142                 status = "disabled";
 143         };
 144
 145         uart1: serial@20064000 {
 146                 compatible = "rockchip,serial";
 147                 reg = <0x20064000 0x100>;
 148                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 149                 clock-frequency = <24000000>;
 150                 clocks = <&clk_uart1>, <&clk_gates8 1>;
 151                 clock-names = "sclk_uart", "pclk_uart";
 152                 reg-shift = <2>;
 153                 reg-io-width = <4>;
 154                 dmas = <&pdma 4>, <&pdma 5>;
 155                 #dma-cells = <2>;
 156                 pinctrl-names = "default";
 157                 pinctrl-0 = <&uart1_xfer>;
 158                 status = "disabled";
 159         };
 160
 161         uart2: serial@20068000 {
 162                 compatible = "rockchip,serial";
 163                 reg = <0x20068000 0x100>;
 164                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 165                 clock-frequency = <24000000>;
 166                 clocks = <&clk_uart2>, <&clk_gates8 2>;
 167                 clock-names = "sclk_uart", "pclk_uart";
 168                 reg-shift = <2>;
 169                 reg-io-width = <4>;
 170                 dmas = <&pdma 6>, <&pdma 7>;
 171                 #dma-cells = <2>;
 172                 pinctrl-names = "default";
 173                 pinctrl-0 = <&uart2_xfer>;
 174                 status = "disabled";
 175         };
 176
 177         fiq-debugger {
 178                 compatible = "rockchip,fiq-debugger";
 179                 rockchip,serial-id = <2>;
 180                 rockchip,signal-irq = <106>;
 181                 rockchip,wake-irq = <0>;
 182                 status = "disabled";
 183         };
 184
 185         clocks-init{
 186                 compatible = "rockchip,clocks-init";
 187                 rockchip,clocks-init-parent =
 188                         <&clk_core_pre &clk_apll>, <&aclk_cpu_pre &clk_gpll>,
 189                         <&aclk_peri_pre &clk_gpll>, <&clk_uart_pll &clk_gpll>,
 190                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 191                         <&aclk_vcodec_pre &clk_gpll>, <&clk_hevc_core &clk_gpll>,
 192                         <&clk_mac_pll &clk_apll>;
 193                 rockchip,clocks-init-rate =
 194                         <&clk_core_pre 816000000>, <&clk_gpll 594000000>,
 195                         <&aclk_cpu_pre 150000000>, <&hclk_cpu_pre 75000000>,
 196                         <&pclk_cpu_pre 75000000>,        <&aclk_peri_pre 150000000>,
 197                         <&hclk_peri_pre 75000000>, <&pclk_peri_pre 75000000>,
 198                         <&clk_gpu_pre 300000000>,        <&aclk_vio_pre 300000000>,
 199                         <&hclk_vio_pre 150000000>, <&aclk_vcodec_pre 300000000>,
 200                         <&clk_hevc_core 300000000>, <&clk_mac_ref_div 50000000>;
 201         /*      rockchip,clocks-uboot-has-init =
 202                         <&aclk_vio1>;*/
 203         };
 204
 205         clocks-enable {
 206                 compatible = "rockchip,clocks-enable";
 207                 clocks =
 208                                 /*PD_CORE*/
 209                                 <&clk_gates0 0>, <&clk_gates0 7>,
 210
 211                                 /*PD_CPU*/
 212                                 <&clk_gates0 3>, <&clk_gates0 4>,
 213                                 <&clk_gates0 5>,
 214
 215                                 /*TIMER*/
 216                                 <&clk_gates1 0>, <&clk_gates1 1>,
 217                                 <&clk_gates2 4>, <&clk_gates2 5>,
 218
 219                                 /*PD_PERI*/
 220                                 <&clk_gates2 0>, <&hclk_peri_pre>,
 221                                 <&pclk_peri_pre>, <&clk_gates2 1>,
 222
 223                                 /*aclk_cpu_pre*/
 224                                 <&clk_gates4 12>,/*aclk_intmem*/
 225                                 <&clk_gates4 10>,/*aclk_strc_sys*/
 226
 227                                 /*hclk_cpu_pre*/
 228                                 <&clk_gates5 6>,/*hclk_rom*/
 229
 230                                 /*pclk_cpu_pre*/
 231                                 <&clk_gates5 4>,/*pclk_grf*/
 232                                 <&clk_gates5 7>,/*pclk_ddrupctl*/
 233                                 <&clk_gates5 14>,/*pclk_acodec*/
 234                                 <&clk_gates3 8>,/*pclk_hdmi*/
 235
 236                                 /*aclk_peri_pre*/
 237                                 <&clk_gates4 3>,/*aclk_peri_axi_matrix*/
 238                                 <&clk_gates5 1>,/*aclk_dmac2*/
 239                                 <&clk_gates9 15>,/*aclk_peri_niu*/
 240                                 <&clk_gates4 2>,/*aclk_cpu_peri*/
 241
 242                                 /*hclk_peri_pre*/
 243                                 <&clk_gates4 0>,/*hclk_peri_matrix*/
 244                                 <&clk_gates9 13>,/*hclk_usb_peri*/
 245                                 <&clk_gates9 14>,/*hclk_peri_arbi*/
 246
 247                                 /*pclk_peri_pre*/
 248                                 <&clk_gates4 1>,/*pclk_peri_axi_matrix*/
 249
 250                                 /*hclk_vio_pre*/
 251                                 <&clk_gates6 12>,/*hclk_vio_bus*/
 252                                 <&clk_gates9 5>,/*hclk_lcdc*/
 253
 254                                 /*aclk_vio_pre*/
 255                                 <&clk_gates6 13>,/*aclk_vio*/
 256                                 <&clk_gates9 6>,/*aclk_lcdc*/
 257
 258                                 /*UART*/
 259                                 <&clk_gates1 12>,
 260                                 <&clk_gates1 13>,
 261                                 <&clk_gates8 2>,/*pclk_uart2*/
 262
 263                                 /*jtag*/
 264                                 <&clk_gates1 3>;/*clk_jtag*/
 265         };
 266
 267         i2c0: i2c@20072000 {
 268                 compatible = "rockchip,rk30-i2c";
 269                 reg = <0x20072000 0x1000>;
 270                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 271                 #address-cells = <1>;
 272                 #size-cells = <0>;
 273                 pinctrl-names = "default", "gpio";
 274                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 275                 pinctrl-1 = <&i2c0_gpio>;
 276                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 277                 clocks = <&clk_gates8 4>;
 278                 rockchip,check-idle = <1>;
 279                 status = "disabled";
 280         };
 281
 282         i2c1: i2c@20056000 {
 283                 compatible = "rockchip,rk30-i2c";
 284                 reg = <0x20056000 0x1000>;
 285                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 pinctrl-names = "default", "gpio";
 289                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 290                 pinctrl-1 = <&i2c1_gpio>;
 291                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 292                 clocks = <&clk_gates8 5>;
 293                 rockchip,check-idle = <1>;
 294                 status = "disabled";
 295         };
 296
 297         i2c2: i2c@2005a000 {
 298                 compatible = "rockchip,rk30-i2c";
 299                 reg = <0x2005a000 0x1000>;
 300                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 pinctrl-names = "default", "gpio";
 304                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 305                 pinctrl-1 = <&i2c2_gpio>;
 306                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 307                 clocks = <&clk_gates8 6>;
 308                 rockchip,check-idle = <1>;
 309                 status = "disabled";
 310         };
 311
 312         i2s: i2s@10220000 {
 313                 compatible = "rockchip-i2s";
 314                 reg = <0x10220000 0x1000>;
 315                 i2s-id = <0>;
 316                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates7 2>;
 317                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 318                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 319                 dmas = <&pdma 0>, <&pdma 1>;
 320                 //#dma-cells = <2>;
 321                 dma-names = "tx", "rx";
 322                 //pinctrl-names = "default", "sleep";
 323                 //pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 324                 //pinctrl-1 = <&i2s_gpio>;
 325         };
 326
 327         spdif: spdif@10204000 {
 328                 compatible = "rockchip-spdif";
 329                 reg = <0x10204000 0x1000>;
 330                 clocks = <&clk_spdif>;
 331                 clock-names = "spdif_mclk";
 332                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 333                 dmas = <&pdma 13>;
 334                 //#dma-cells = <1>;
 335                 dma-names = "tx";
 336                 //pinctrl-names = "default";
 337                 //pinctrl-0 = <&spdif_tx>;
 338         };
 339
 340         pwm0: pwm@20050000 {
 341                 compatible = "rockchip,rk-pwm";
 342                 reg = <0x20050000 0x10>;
 343                 #pwm-cells = <2>;
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&pwm0_pin>;
 346                 clocks = <&clk_gates7 10>;
 347                 clock-names = "pclk_pwm";
 348                 status = "disabled";
 349         };
 350
 351         pwm1: pwm@20050010 {
 352                 compatible = "rockchip,rk-pwm";
 353                 reg = <0x20050010 0x10>;
 354                 #pwm-cells = <2>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&pwm1_pin>;
 357                 clocks = <&clk_gates7 10>;
 358                 clock-names = "pclk_pwm";
 359                 status = "disabled";
 360         };
 361
 362         pwm2: pwm@20050020 {
 363                 compatible = "rockchip,rk-pwm";
 364                 reg = <0x20050020 0x10>;
 365                 #pwm-cells = <2>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&pwm2_pin>;
 368                 clocks = <&clk_gates7 10>;
 369                 clock-names = "pclk_pwm";
 370                 status = "disabled";
 371         };
 372
 373         pwm3: pwm@20050030 {
 374                 compatible = "rockchip,rk-pwm";
 375                 reg = <0x20050030 0x10>;
 376                 #pwm-cells = <2>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&pwm3_pin>;
 379                 clocks = <&clk_gates7 10>;
 380                 clock-names = "pclk_pwm";
 381                 status = "disabled";
 382         };
 383
 384         emmc: rksdmmc@1021c000 {
 385                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 386                 reg = <0x1021c000 0x4000>;
 387                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 //pinctrl-names = "default",,"suspend";
 391                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 392                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 393                 clock-names = "clk_mmc", "hclk_mmc";
 394                 dmas = <&pdma 12>;
 395                 dma-names = "dw_mci";
 396                 num-slots = <1>;
 397                 fifo-depth = <0x100>;
 398                 bus-width = <8>;
 399         };
 400
 401
 402         sdmmc: rksdmmc@10214000 {
 403                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 404                 reg = <0x10214000 0x4000>;
 405                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 pinctrl-names = "default", "idle";
 409                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 410                 pinctrl-1 = <&sdmmc0_gpio>;
 411                 cd-gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 412                 clocks = <&clk_sdmmc0>, <&clk_gates2 11>;
 413                 clock-names = "clk_mmc", "hclk_mmc";
 414                 dmas = <&pdma 10>;
 415                 dma-names = "dw_mci";
 416                 num-slots = <1>;
 417                 fifo-depth = <0x100>;
 418                 bus-width = <4>;
 419         };
 420
 421         sdio: rksdmmc@10218000 {
 422                 compatible = "rockchip,rk_mmc", "rockchip,rk3036-sdmmc";
 423                 reg = <0x10218000 0x4000>;
 424                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 pinctrl-names = "default","idle";
 428                 pinctrl-0 = <&sdio0_clk &sdio0_cmd  &sdio0_bus4>;
 429                 pinctrl-1 = <&sdio0_gpio>;
 430                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 431                 clock-names = "clk_mmc", "hclk_mmc";
 432                 dmas = <&pdma 11>;
 433                 dma-names = "dw_mci";
 434                 num-slots = <1>;
 435                 fifo-depth = <0x100>;
 436                 bus-width = <4>;
 437         };
 438         gpu {
 439                 compatible = "arm,mali400";
 440                 reg = <0x10091000 0x200>,
 441                           <0x10090000 0x100>,
 442                           <0x10093000 0x100>,
 443                           <0x10098000 0x1100>,
 444                           <0x10094000 0x100>;
 445                 reg-names = "Mali_L2",
 446                                         "Mali_GP",
 447                                         "Mali_GP_MMU",
 448                                         "Mali_PP0",
 449                                         "Mali_PP0_MMU";
 450
 451             interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 452                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 453                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 454                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 455             interrupt-names = "Mali_GP_IRQ",
 456                                                   "Mali_GP_MMU_IRQ",
 457                                                   "Mali_PP0_IRQ",
 458                                                   "Mali_PP0_MMU_IRQ";
 459           };
 460         dwc_control_usb: dwc-control-usb@20008000 {
 461                 compatible = "rockchip,rk3188-dwc-control-usb";
 462                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 463                 interrupt-names = "otg_bvalid";
 464                 //gpios = <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D5 GPIO_ACTIVE_LOW>;
 465                 clocks = <&clk_gates9 13>;
 466                 clock-names = "hclk_usb_peri";
 467                 rockchip,remote_wakeup;
 468                 rockchip,usb_irq_wakeup;
 469
 470                 usb_bc{
 471                         compatible = "rockchip,ctrl";
 472                         rk_usb,bvalid   = <0x14c 8 1>;
 473                         rk_usb,iddig    = <0x14c 11 1>;
 474                         rk_usb,line     = <0x14c 9 2>;
 475                         rk_usb,softctrl = <0x17c 0 1>;
 476                         rk_usb,opmode   = <0x17c 2 2>;
 477                         rk_usb,xcvrsel  = <0x17c 4 2>;
 478                         rk_usb,termsel  = <0x118 6 1>;
 479                 };
 480         };
 481         usb0: usb@10180000 {
 482                 compatible = "rockchip,rk3188_usb20_otg";
 483                 reg = <0x10180000 0x40000>;
 484                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 485                 clocks = <&clk_gates1 5>, <&clk_gates5 13>;
 486                 clock-names = "clk_usbphy0", "hclk_usb0";
 487                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 488                 rockchip,usb-mode = <0>;
 489         };
 490
 491         usb1: usb@101c0000 {
 492                 compatible = "rockchip,rk3188_usb20_host";
 493                 reg = <0x101c0000 0x40000>;
 494                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 495                 clocks = <&clk_gates1 6>, <&clk_gates7 3>;
 496                 clock-names = "clk_usbphy1", "hclk_usb1";
 497         };
 498
 499         fb: fb{
 500                 compatible = "rockchip,rk-fb";
 501                 rockchip,disp-mode = <NO_DUAL>;
 502         };
 503
 504         rk_screen: rk_screen{
 505                 compatible = "rockchip,screen";
 506         };
 507
 508         lcdc: lcdc@10118000 {
 509                 compatible = "rockchip,rk3036-lcdc";
 510                 reg = <0x10118000 0x4000>;
 511                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 512                 status = "disabled";
 513                 clocks = <&clk_gates9 6>, <&dclk_lcdc1>, <&clk_gates9 5>;
 514                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 515                 rockchip,iommu-enabled = <1>;
 516         };
 517
 518         hdmi: hdmi@20034000 {
 519                 compatible = "rockchip,rk3036-hdmi";
 520                 reg = <0x20034000 0x4000>;
 521                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 522                 rockchip,hdmi_lcdc_source = <0>;
 523                 pinctrl-names = "default", "gpio";
 524                 pinctrl-0 = <&hdmi_cec &hdmi_sda &hdmi_scl &hdmi_hpd>;
 525                 pinctrl-1 = <&hdmi_gpio>;
 526                 clocks = <&clk_gates3 8>;
 527                 clock-names = "pclk_hdmi";
 528                 status = "disabled";
 529         };
 530
 531         tve {
 532                 compatible = "rockchip,rk3036-tve";
 533                 reg = <0x10118200 0x100>;
 534                 status = "disabled";
 535         };
 536
 537         vpu: vpu_service@10108000 {
 538                 compatible = "vpu_service";
 539                 reg = <0x10108000 0x800>;
 540                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 541                 interrupt-names = "irq_enc", "irq_dec";
 542                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>;
 543                 clock-names = "aclk_vcodec", "hclk_vcodec";
 544                 name = "vpu_service";
 545                 status = "disabled";
 546         };
 547
 548         hevc: hevc_service@1010c000 {
 549                 compatible = "rockchip,hevc_service";
 550                 reg = <0x1010c000 0x800>;
 551                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 552                 interrupt-names = "irq_dec";
 553                 clocks = <&aclk_vcodec_pre>, <&clk_gates3 12>, <&clk_hevc_core>;
 554                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
 555                 name = "hevc_service";
 556                 status = "disabled";
 557         };
 558
 559         vop_mmu {
 560                 dbgname = "vop";
 561                 compatible = "iommu,vop_mmu";
 562                 reg = <0x10118300 0x100>;
 563                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 564                 interrupt-names = "vop_mmu";
 565         };
 566
 567         hevc_mmu {
 568                 dbgname = "hevc";
 569                 compatible = "iommu,hevc_mmu";
 570                 reg = <0x1010c440 0x100>,
 571                       <0x1010c480 0x100>;
 572                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 573                 interrupt-names = "hevc_mmu";
 574         };
 575
 576         vpu_mmu {
 577                 dbgname = "vpu";
 578                 compatible = "iommu,vpu_mmu";
 579                 reg = <0x10108800 0x100>;
 580                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 581                 interrupt-names = "vpu_mmu";
 582         };
 583 };